Where devices only have one consumer, passing a consumer clock ID
has no real benefit. Remove it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1. add a CPUID table in the comment
2. make cpu_is_pxa25x() true for PXA210/250/255/26x
3. PXA210 is treated as PXA25x, all related code modified to
reflect this
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now get_ro() callback must return 0/1 values for its logical states, and
negative errno values in case of error. If particular host instance doesn't
support RO/WP switch, it should return -ENOSYS.
This patch changes some hosts in two ways:
1. Now functions should be smart to not return negative values in
"RO asserted" case (particularly gpio_ calls could return negative
values for the outermost GPIOs).
Also, board code usually passes get_ro() callbacks that directly return
gpioreg & bit result, so at91_mci, imxmmc, pxamci and mmc_spi's get_ro()
handlers need take special care when returning platform's values to the
mmc core.
2. In case of host instance didn't implement get_ro() callback, it should
really return -ENOSYS and let the mmc core decide what to do about it
(mmc core thinks the same way as the hosts, so it isn't functional
change).
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
The pxa27x DMA controller defaults to 64-bit alignment. This caused
the SCR reads to fail (and, depending on card type, error out) when
card->raw_scr was not aligned on a 8-byte boundary.
For performance reasons all scatter-gather addresses passed to
pxamci_request should be aligned on 8-byte boundaries, but if
this can't be guaranteed, byte aligned DMA transfers in the
have to be enabled in the controller to get correct behaviour.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Since 43cc71eed1, the platform modalias is
prefixed with "platform:". Add MODULE_ALIAS() to the hotpluggable MMC host
platform drivers, to re-enable auto loading.
Also, add missing owner declarations in driver init.
[dbrownell@users.sourceforge.net: registration fixes]
Signed-off-by: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Acked-by: Pierre Ossman <drzeus@drzeus.cx>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This patch is to move pxamci DMA specific code to corresponding
platform layer because using DRCMRRXMMC/DRCMRTXMMC in pxamci.c makes
the driver code dedicated to platform which is not extensible.
It is applicable to all pxa platforms.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
pxa3[0|1]0 mmc controller can support 26MHz clock mode, they support
SD spec 1.1 and MMC spec 4.0 which specify high speed mode. So host
caps will include MMC_CAP_MMC_HIGHSPEED and MMC_CAP_SD_HIGHSPEED for
pxa3[0|1]0.
This patch is to add 26MHz support for them. pxa host clock will be
set to 26MHz mode when the card supported max clock rate is higher
than or equal to 26MHz.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Acked-by: Pierre Ossman <drzeus@drzeus.cx>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix:
WARNING: at arch/arm/mach-pxa/clock.c:69 clk_disable()
[<c002d7c8>] (dump_stack+0x0/0x14) from [<c00334f4>] (clk_disable+0x34/0xa0)
[<c00334c0>] (clk_disable+0x0/0xa0) from [<c028a43c>] (pxamci_set_ios+0x74/0xf0)
[<c028a3c8>] (pxamci_set_ios+0x0/0xf0) from [<c0281548>] (mmc_power_off+0x90/0x9c)
[<c02814b8>] (mmc_power_off+0x0/0x9c) from [<c0281a30>] (mmc_start_host+0x18/0x28)
[<c0281a18>] (mmc_start_host+0x0/0x28) from [<c02825a0>] (mmc_add_host+0xe8/0x104)
[<c02824b8>] (mmc_add_host+0x0/0x104) from [<c028a7d0>] (pxamci_probe+0x24c/0x2f4)
[<c028a584>] (pxamci_probe+0x0/0x2f4) from [<c01e5948>] (platform_drv_probe+0x20/0x24)
...
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Do a full scan of the directory to try and be a bit more proactive,
instead of waiting for things to break.
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
The PXA has two transmit FIFOes, each32 byte deep. when one FIFO is
full and the other one has been transmitted, they are automatically
swapped and DMA is triggered for another 32 byte burst. However, when
there is less than 32 bytes left to send, the FIFO swap has to be done
manually. This is required for some SDIO transfers which are not
required to be multiples of 32 bytes.
A DMA completion interrupt is set for each descriptor which length isn't
a multiple of 32 in order to force the FIFO swap. While at it, the DMA
interrupt handler has been made a bit more resilient against errors.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Again, only available from PXA27x.
Signed-off-by: Bridge Wu <mingqiao.wu@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
From PXA27x, it is possible to do 4-bit data transfers.
Signed-off-by: Bridge Wu <mingqiao.wu@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
From PXA27x, it is possible to do 2048-byte block transfers.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Pending interrupts should be determined from both I_REG and I_MASK
registers.
Signed-off-by: Bridge Wu <mingqiao.wu@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
... and make it depend on the response flag instead of the command type.
Signed-off-by: Nicolas Pitre <npitre@mvista.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
