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46 Commits

Author SHA1 Message Date
Takeshi Kihara
c50378efa9 clk: renesas: r8a7796: Add Z2 clock 
This patch adds Z2 clock for R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-02-12 15:10:18 +01:00
Takeshi Kihara
72f2a6b315 clk: renesas: r8a7796: Add Z clock 
This patch adds Z clock for R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-02-12 15:10:18 +01:00
ABE Hiroshige
a115f6362c clk: renesas: r8a7796: Add FDP clock 
This patch adds FDP1-0 clock to the R8A7796 SoC.

Signed-off-by: ABE Hiroshige <hiroshige.abe.zc@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: s/fdp0/fdp1-0/]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 2018-01-05 11:14:38 +01:00
Geert Uytterhoeven
6e7ddf89d6 clk: renesas: r8a7796: Correct parent clock of INTC-AP 
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
September 8, 2017, the parent clock of the INTC-AP module clock on R-Car
M3-W is S0D3.

This change has no functional impact.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-10-16 09:38:38 +02:00
Hiromitsu Yamasaki
c29f82951b clk: renesas: r8a7796: Add USB3.0 clock 
This patch adds USB3.0-IF0 clock for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-08-17 09:22:26 +02:00
Geert Uytterhoeven
09a7dea9d5 clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 
On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one.  Extend struct rcar_gen3_cpg_pll_config to handle
this.  As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
 2017-08-16 09:51:47 +02:00
Takeshi Kihara
8a187f0c62 clk: renesas: r8a7796: Add INTC-EX clock 
Add the "intc-ex" clock to the R8A7796 CPG MSSR driver.

According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.

[takeshi.kihara.df: Ported from commit f099aa0757 ("clk: shmobile:
 r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Harunobu Kurokawa
9097f5e3c2 clk: renesas: r8a7796: Add PCIe clocks 
This patch adds PCIEC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Ryo Kodama
a0b381faff clk: renesas: r8a7796: Add PWM clock 
This patch adds PWM clock for PWM.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clock]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi
a703e11f41 clk: renesas: r8a7796: Add HS-USB clock 
This patch adds HS-USB-IF clock for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi
60c2db767a clk: renesas: r8a7796: Add Sound DVC clocks 
This patch adds adds SCU(DVC{0,1}) clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi
df42e584f2 clk: renesas: r8a7796: Add Sound SRC clock 
This patch adds SCU(all), SCU(SRC{0,1,2,3,4,5,6,7,8,9}), SCU(CTU00,
CTU01, CTU02, CTU03, MIX0) and SCU (CTU10, CTU11, CTU12, CTU13, MIX1)
clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi
8fe3574280 clk: renesas: r8a7796: Add Sound SSI clock 
This patch adds SSI(all) and SSI{0,1,2,3,4,5,6,7,8,9} clocks for R8A7796
SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Hiromitsu Yamasaki
7cb1ce2688 clk: renesas: r8a7796: Add USB-DMAC clocks 
This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Hiromitsu Yamasaki
c1da6b4b84 clk: renesas: r8a7796: Add Audio-DMAC clocks 
This patch adds A-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clocks, preserve sort order]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi
f4c542923d clk: renesas: r8a7796: Add EHCI/OHCI clocks 
This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Koji Matsuoka
12390605ac clk: renesas: r8a7796: Add HDMI clock 
This patch adds HDMI-IF0 clock for R8A7796 SoC.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-05-15 09:46:31 +02:00
Geert Uytterhoeven
5f3a432a44 clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() 
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-03-21 11:12:23 +01:00
Geert Uytterhoeven
c013fc7d23 clk: renesas: r8a7796: Reformat core clock table 
For easier comparison with other clock drivers.
No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-03-21 11:12:22 +01:00
Geert Uytterhoeven
89aa58a395 clk: renesas: r8a7796: Correct name of watchdog clock 
There's only a single watchdog clock, and it's named "rwdt".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-03-21 11:12:21 +01:00
Sergei Shtylyov
6c8a931294 clk: renesas: r8a7796: Add IMR clocks 
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[geert: Correct parent clocks]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-03-06 11:48:33 +01:00
Khiem Nguyen
d963654e10 clk: renesas: r8a7796: Add IIC-DVFS clock 
This patch adds DVFS clock for R8A7796 SoC.

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2017-01-27 08:59:24 +01:00
Hiromitsu Yamasaki
e6bdf28eff clk: renesas: r8a7796: Add MSIOF controller clocks 
This patch adds MSIOF{0,1,2,3} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-12-27 10:56:08 +01:00
Chris Paterson
0ece46c24f clk: renesas: r8a7796: Add CAN FD peripheral clock 
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-12-27 10:56:08 +01:00
Chris Paterson
9e620beecd clk: renesas: r8a7796: Add CANFD clock 
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-12-27 10:56:07 +01:00
Chris Paterson
e00d20c99d clk: renesas: r8a7796: Add CAN peripheral clock 
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-12-27 10:56:07 +01:00
Niklas Söderlund
e6e3558626 clk: renesas: r8a7796: Add VIN clocks 
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-11-07 15:16:18 +01:00
Niklas Söderlund
5fccac6d94 clk: renesas: r8a7796: Add CSI2 clocks 
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-11-07 15:16:17 +01:00
Geert Uytterhoeven
a05de66ea6 Merge branch 'rcar-rst' into clk-renesas-for-v4.10 
soc: renesas: Add R-Car RST driver for obtaining mode pin state
 2016-11-02 20:53:26 +01:00
Geert Uytterhoeven
05972d48d2 clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver 
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 2016-11-02 20:43:56 +01:00
Laurent Pinchart
dbdcc4f996 clk: renesas: r8a7796: Add DU and LVDS clocks 
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-11-02 20:40:08 +01:00
Laurent Pinchart
88ddc1f8e3 clk: renesas: r8a7796: Add VSP clocks 
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-11-02 20:40:07 +01:00
Laurent Pinchart
f4407a6e26 clk: renesas: r8a7796: Add FCP clocks 
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-11-02 20:40:07 +01:00
Ramesh Shanmugasundaram
cf31bc71c0 clk: renesas: r8a7796: Add DRIF clock 
This patch adds DRIF module clocks for r8a7796 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-11-02 20:39:55 +01:00
Ulrich Hecht
878f8baa02 clk: renesas: r8a7796: Add I2C clocks 
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-10-17 15:56:21 +02:00
Ulrich Hecht
28aa831949 clk: renesas: r8a7796: Add HSCIF clocks 
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-10-17 15:56:21 +02:00
Ulrich Hecht
951456c37d clk: renesas: r8a7796: Add SCIF clocks 
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-10-17 15:56:20 +02:00
Ulrich Hecht
cf8fe97cad clk: renesas: r8a7796: Add SYS-DMAC clocks 
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-10-17 15:56:20 +02:00
Bui Duc Phuc
5fad71f58f clk: renesas: r8a7796: Add CMT clocks 
This patch adds CMT module clocks for r8a7796 SoC.

Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-09-12 11:08:01 +02:00
Laurent Pinchart
5576df81d2 clk: renesas: r8a7796: Add RAVB clock 
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-09-12 11:08:00 +02:00
Khiem Nguyen
5086b0d6ce clk: renesas: r8a7796: Add THS/TSC clock 
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-09-05 14:16:25 +02:00
Simon Horman
0749698133 clk: renesas: r8a7796: Add SDIF clocks 
This patch adds SDIF clocks for R8A7796 SoC.

Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-08-23 10:30:41 +02:00
Takeshi Kihara
4e09508a89 clk: renesas: r8a7796: Add GPIO clocks 
Add GPIO clocks for the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-08-19 09:38:40 +02:00
Geert Uytterhoeven
b51d527501 clk: renesas: r8a7796: Add watchdog module clock 
Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-08-09 09:53:47 +02:00
Geert Uytterhoeven
2570d4005d clk: renesas: r8a7796: Add watchdog core clocks 
Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2016-08-09 09:53:47 +02:00
Geert Uytterhoeven
e4e2d7c388 clk: renesas: cpg-mssr: Add support for R-Car M3-W 
Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
 2016-06-06 11:58:35 +02:00