Commit Graph

257 Commits

Author SHA1 Message Date
Tudor Ambarus
502c4b0a14
mtd: spi-nor: Group all Reg Ops to avoid forward declarations
Group all register methods up in the file, to avoid forward
declarations.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:28:38 +02:00
Tudor Ambarus
40b04958fa
mtd: spi-nor: Drop duplicated new line
Two new lines, one after another, drop one.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:28:33 +02:00
Tudor Ambarus
567c2983ef
mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methods
All the core functions should begin with "spi_nor_".

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:27:22 +02:00
Tudor Ambarus
4539778753
mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'
Move all SPI NOR controller driver specific ops in a dedicated
structure. 'struct spi_nor' becomes lighter.

Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'.
Rename wite/read_buf to buf, the name of the functions are
suggestive enough. Constify buf in int (*write_reg). Comply with these
changes in the SPI NOR controller drivers.

Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23 09:27:21 +03:00
DENG Qingfang
172b33212d
mtd: spi-nor: add support for en25qh16
Tested on HiWiFi C526A

Datasheet is available at:
http://www.xinyahong.com/upLoad/product/month_1411/201411201256018276.pdf

Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-23 09:27:19 +03:00
Tudor Ambarus
41e086e155 mtd: spi-nor: Fix direction of the write_sr() transfer
write_sr() sends data to the SPI memory, fix the direction.

Fixes: b35b9a1036 ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Reported-by: John Garry <john.garry@huawei.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: John Garry <john.garry@huawei.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-04 18:09:01 +02:00
Ashish Kumar
9607af6f85
mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"
n25q512a was rebranded to mt25qu512a after its spin off from STM.
mt25qu512a is different only in terms of operating frequency, the
JEDEC id is the same as in n25q512a.

Dual reads are supported (0x3b, 0x3c), set the SPI_NOR_DUAL_READ flag.
4-byte opcodes are supported, set the SPI_NOR_4B_OPCODES flag.

Tested Single I/O and QUAD I/O mode on LS1046FRWY.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
[tudor.ambarus@microchip.com: rename entry to "mt25qu512a (n25q512a)",
reword commit message, order entry by size, drop comment as it looked
redundant]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-30 10:11:50 +03:00
Ashish Kumar
173c3d4773
mtd: spi-nor: Add support for mt35xu02g
mt35xu02g is an Octal flash supporting Single and OCTAL I/O.
Tested on LS1028ARDB.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
[tudor.ambarus@microchip.com: reword commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-30 10:07:34 +03:00
Tudor Ambarus
3a960339e0
mtd: spi-nor: remove superfluous pass of nor->info->sector_size
We already pass a pointer to nor, we can obtain the sector_size
by dereferencing it.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-29 13:39:56 +03:00
Zhuohao Lee
dcc935b06f
mtd: spi-nor: enable the debugfs for the partname and partid
This patch adds spi_nor_debugfs_init() for the debugfs initialization.
With this patch, we can read the partname and partid through the
debugfs.

The output of new debugfs nodes on my device are:
cat /sys/kernel/debug/mtd/mtd0/partid
spi-nor:ef6017
cat /sys/kernel/debug/mtd/mtd0/partname
w25q64dw

Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-29 10:36:54 +03:00
Tudor Ambarus
620df24974
mtd: spi-nor: Introduce spi_nor_get_flash_info()
Dedicate a function for getting the pointer to the flash_info
const struct. Trim a bit the spi_nor_scan() huge function.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:30 +03:00
Tudor Ambarus
696ce50f4e
mtd: spi-nor: Introduce spi_nor_set_addr_width()
Parsing of flash parameters were interleaved with setting of the
nor addr width. Dedicate a function for setting nor addr width.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:30 +03:00
Tudor Ambarus
07920dfcf0
mtd: spi-nor: Bring flash params init together
Bring all flash parameters default initialization in
spi_nor_legacy_params_init().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:30 +03:00
Boris Brezillon
ad3bba06b6
mtd: spi-nor: Add the SPI_NOR_XSR_RDY flag
S3AN flashes use a specific opcode to read the status register.
We currently use the SPI_S3AN flag to decide whether this specific
SR read opcode should be used, but SPI_S3AN is about to disappear, so
let's add a new flag.

Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and
vice versa.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:30 +03:00
Tudor Ambarus
641edddb4f
mtd: spi-nor: Add s3an_post_sfdp_fixups()
s3an_nor_scan() was overriding the opcode selection done in
spi_nor_default_setup(). Set nor->setup() method in order to
avoid the unnecessary call to spi_nor_default_setup().

Now that the call to spi_nor_default_setup() is skipped, set
mtd.erasesize to nor->info->sector_size, as it was when
spi_nor_select_erase() was called.

No dummy byte is required for the S3AN's Random Read command (0x03),
so no need to set nor->read_dummy.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:29 +03:00
Tudor Ambarus
2d7ff858e5
mtd: spi-nor: Add a ->setup() method
nor->params.setup() configures the SPI NOR memory. Useful for SPI NOR
flashes that have peculiarities to the SPI NOR standard, e.g.
different opcodes, specific address calculation, page size, etc.
Right now the only user will be the S3AN chips, but other
manufacturers can implement it if needed.

Move spi_nor_setup() related code in order to avoid a forward
declaration to spi_nor_default_setup().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:29 +03:00
Boris Brezillon
3649959628
mtd: spi-nor: Add a ->convert_addr() method
In order to separate manufacturer quirks from the core we need to get
rid of all the manufacturer specific flags, like the
SNOR_F_S3AN_ADDR_DEFAULT one.

This can easily be replaced by a ->convert_addr() hook, which when
implemented will provide the core with an easy way to convert an
absolute address into something the flash understands.

Right now the only user are the S3AN chips, but other manufacturers
can implement it if needed.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:29 +03:00
Boris Brezillon
92094ebc38
mtd: spi-nor: Add spansion_post_sfdp_fixups()
Add a spansion_post_sfdp_fixups() function to fix the erase opcode,
erase sector size and set the SNOR_F_4B_OPCODES flag.
This way, all spansion related quirks are placed in the
spansion_post_sfdp_fixups() function.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:29 +03:00
Boris Brezillon
2b12ae1f2f
mtd: spi-nor: Add post_sfdp() hook to tweak flash config
SFDP tables are sometimes wrong and we need a way to override the
config chosen by the SFDP parsing logic without discarding all of it.

Add a new hook called after the SFDP parsing has taken place to deal
with such problems.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:28 +03:00
Boris Brezillon
dff972458a
mtd: spi-nor: Rework the SPI NOR lock/unlock logic
Add the SNOR_F_HAS_LOCK flag and set it when SPI_NOR_HAS_LOCK is set
in the flash_info entry or when it's a Micron or ST flash.

Move the locking hooks in a separate struct so that we have just
one field to update when we change the locking implementation.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
[tudor.ambarus@microchip.com: use ->default_init() hook, introduce
spi_nor_late_init_params(), set ops in nor->params]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:28 +03:00
Boris Brezillon
64c160f322
mtd: spi-nor: Create a ->set_4byte() method
The procedure used to enable 4 byte addressing mode depends on the NOR
device, so let's provide a hook so that manufacturer specific handling
can be implemented in a sane way.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
[tudor.ambarus@microchip.com: use nor->params.set_4byte() instead of
nor->set_4byte()]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:28 +03:00
Tudor Ambarus
1c1d8d98e1
mtd: spi-nor: Split spi_nor_init_params()
Add functions to delimit what the chunks of code do:

static void spi_nor_init_params()
{
	spi_nor_info_init_params()
	spi_nor_manufacturer_init_params()
	spi_nor_sfdp_init_params()
}

Add descriptions to all methods.

spi_nor_init_params() becomes of type void, as all its children
return void.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:28 +03:00
Tudor Ambarus
22f2eaac3f
mtd: spi-nor: Move manufacturer quad_enable() in ->default_init()
The goal is to move the quad_enable manufacturer specific init in the
nor->manufacturer->fixups->default_init()

The legacy quad_enable() implementation is spansion_quad_enable(),
select this method by default.

Set specific manufacturer fixups->default_init() hooks to overwrite
the default quad_enable() implementation when needed.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:27 +03:00
Boris Brezillon
48e4d973ae
mtd: spi-nor: Add a default_init() fixup hook for gd25q256
gd25q256 needs to tweak the ->quad_enable() implementation and the
->default_init() fixup hook is the perfect place to do that. This way,
if we ever need to tweak more things for this flash, we won't have to
add new fields in flash_info.

We can get rid of the flash_info->quad_enable field as gd25q256 was
the only user.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
[tudor.ambarus@microchip.com: use ->default_init() hook instead of
->post_sfdp()]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:27 +03:00
Tudor Ambarus
ce0b6f3f3c
mtd: spi-nor: Add default_init() hook to tweak flash parameters
As of now, the flash parameters initialization logic is as following:

a/ default flash parameters init in spi_nor_init_params()
b/ manufacturer specific flash parameters updates, split across entire
   spi-nor core code
c/ flash parameters updates based on SFDP tables
d/ post BFPT flash parameter updates

In the quest of removing the manufacturer specific code from the spi-nor
core, we want to impose a timeline/priority on how the flash parameters
are updated. The following sequence of calls is pursued:

1/ spi-nor core parameters init based on 'flash_info' struct:
	spi_nor_info_init_params()

which can be overwritten by:
2/ MFR-based manufacturer flash parameters init:
	nor->manufacturer->fixups->default_init()

which can be overwritten by:
3/ specific flash_info tweeks done when decisions can not be done just on
   MFR:
	nor->info->fixups->default_init()

which can be overwritten by:
4/ SFDP tables flash parameters init - SFDP knows better:
	spi_nor_sfdp_init_params()

which can be overwritten by:
5/ post SFDP tables flash parameters updates - in case manufacturers get
   the serial flash tables wrong or incomplete.
	nor->info->fixups->post_sfdp()
   The later can be extended to nor->manufacturer->fixups->post_sfdp() if
   needed.

This patch opens doors for steps 2/ and 3/.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:27 +03:00
Tudor Ambarus
c46872170a
mtd: spi-nor: Move erase_map to 'struct spi_nor_flash_parameter'
All flash parameters and settings should reside inside
'struct spi_nor_flash_parameter'. Move the SMPT parsed erase map
from 'struct spi_nor' to 'struct spi_nor_flash_parameter'.

Please note that there is a roll-back mechanism for the flash
parameter and settings, for cases when SFDP parser fails. The SFDP
parser receives a Stack allocated copy of nor->params, called
sfdp_params, and uses it to retrieve the serial flash discoverable
parameters. JESD216 SFDP is a standard and has a higher priority
than the default initialized flash parameters, so will overwrite the
sfdp_params data when needed. All SFDP code uses the local copy of
nor->params, that will overwrite it in the end, if the parser succeds.

Saving and restoring the nor->params.erase_map is no longer needed,
since the SFDP code does not touch it.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:27 +03:00
Tudor Ambarus
42f5994724
mtd: spi-nor: Drop quad_enable() from 'struct spi-nor'
All flash parameters and settings should reside inside
'struct spi_nor_flash_parameter'. Drop the local copy of
quad_enable() and use the one from 'struct spi_nor_flash_parameter'.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:26 +03:00
Tudor Ambarus
1e35a56781
mtd: spi-nor: Use nor->params
The Flash parameters and settings are now stored in 'struct spi_nor'.
Use this instead of the stack allocated params.

Few functions stop passing pointer to params, as they can get it from
'struct spi_nor'. spi_nor_parse_sfdp() and children will keep passing
pointer to params because of the roll-back mechanism: in case the
parsing of SFDP fails, the legacy flash parameter and settings will be
restored.

Zeroing params is no longer needed because all SPI NOR users kzalloc
'struct spi_nor'.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:26 +03:00
Tudor Ambarus
47599127a2
mtd: spi-nor: Regroup flash parameter and settings
The scope is to move all [FLASH-SPECIFIC] parameters and settings
from 'struct spi_nor' to 'struct spi_nor_flash_parameter'.

'struct spi_nor_flash_parameter' describes the hardware capabilities
and associated settings of the SPI NOR flash memory. It includes
legacy flash parameters and settings that can be overwritten by the
spi_nor_fixups hooks, or dynamically when parsing the JESD216
Serial Flash Discoverable Parameters (SFDP) tables. All SFDP params
and settings will fit inside 'struct spi_nor_flash_parameter'.

Move spi_nor_hwcaps related code to avoid forward declarations.
Add a forward declaration that we can't avoid: 'struct spi_nor' will
be used in 'struct spi_nor_flash_parameter'.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28 12:40:26 +03:00
Tudor Ambarus
1e05a7e6eb Linux 5.3-rc6
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Merge tag 'v5.3-rc6' into spi-nor/next

Linux 5.3-rc6

Merge back latest release candidate, to include a fix that
we depend on for new development:
834de5c1aa ("mtd: spi-nor: Fix the disabling of write protection at init")
2019-08-28 12:38:40 +03:00
Wenwen Wang
313aca5a9c
mtd: spi-nor: fix a memory leak bug
In spi_nor_parse_4bait(), 'dwords' is allocated through kmalloc(). However,
it is not deallocated in the following execution if spi_nor_read_sfdp()
fails, leading to a memory leak. To fix this issue, free 'dwords' before
returning the error.

Fixes: 816873eaee ("mtd: spi-nor: parse SFDP 4-byte Address Instruction Table")
Signed-off-by: Wenwen Wang <wenwen@cs.uga.edu>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-21 11:08:01 +03:00
Dan Carpenter
3e9e38d918
mtd: spi-nor: Fix an error code in spi_nor_read_raw()
The problem is that if "ret" is negative then when we check if
"ret > len", that condition is going to be true because of type
promotion.  So this patch re-orders the code to check for negatives
first and preserve those error codes.

Fixes: f384b352cb ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-21 11:01:55 +03:00
Jungseung Lee
e702389803
mtd: spi-nor : Remove SPI_NOR_HAS_TB flag on s25fl512s
Currently, the Top/Bottom protection function (SPI_NOR_HAS_TB) is
implemented to fit some flashes with TB bit on SR.

s25fl512s has TBPROT bit on CR1, so the TB protection is not working on it.
Fix the wrong flag on s25fl512s.

Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-20 18:09:01 +03:00
Eugeniy Paltsev
6dc944db29
mtd: spi-nor: add support for sst26wf016b memory IC
This commit adds support for the SST sst26wf016b flash memory IC.
This IC was tested with  "snps,dw-apb-ssi" SPI controller.
We don't test dual/quad reads however sst26wf016b flash's datasheet
advertises both dual and quad reads (and support of corresponding
commands)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-20 17:35:21 +03:00
Avi Fishman
3123db1d26
mtd: spi-nor: Add Winbond w25q256jvm
Similar to w25q256 (besides not supporting QPI mode) but with different ID.
The "JVM" suffix is in the datasheet.
The datasheet indicates DUAL and QUAD are supported.
https://www.winbond.com/resource-files/w25q256jv%20spi%20revi%2010232018%20plus.pdf

Signed-off-by: Avi Fishman <avifishman70@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-20 17:20:54 +03:00
Tudor Ambarus
834de5c1aa mtd: spi-nor: Fix the disabling of write protection at init
spi_nor_spansion_clear_sr_bp() depends on spansion_quad_enable().
While spansion_quad_enable() is selected as default when
initializing the flash parameters, the nor->quad_enable() method
can be overwritten later on when parsing BFPT.

Select the write protection disable mechanism at spi_nor_init() time,
when the nor->quad_enable() method is already known.

Fixes: 191f5c2ed4 ("mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
2019-08-13 14:34:42 +02:00
Boris Brezillon
c76f508979
mtd: spi-nor: Rework hwcaps selection for the spi-mem case
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.

Rework the hwcaps selection logic to use spi_mem_supports_op() when
nor->spimem != NULL.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-12 11:02:54 +03:00
Boris Brezillon
b35b9a1036
mtd: spi-nor: Move m25p80 code in spi-nor.c
The m25p80 driver is actually a generic wrapper around the spi-mem
layer. Not only the driver name is misleading, but we'd expect such a
common logic to be directly available in the core. Another reason for
moving this code is that SPI NOR controller drivers should
progressively be replaced by SPI controller drivers implementing the
spi_mem_ops interface, and when the conversion is done, we should have
a single spi-nor driver directly interfacing with the spi-mem layer.

While moving the code we also fix a longstanding issue when
non-DMA-able buffers are passed by the MTD layer.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-12 10:54:12 +03:00
Vignesh Raghavendra
f173f26a4d
mtd: spi-nor: always use bounce buffer for register read/writes
spi-mem layer expects all buffers passed to it to be DMA'able. But
spi-nor layer mostly allocates buffers on stack for reading/writing to
registers and therefore are not DMA'able. Introduce bounce buffer to be
used to read/write to registers. This ensures that buffer passed to
spi-mem layer during register read/writes is DMA'able. With this change
nor->cmd-buf is no longer used, so drop it.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-12 10:53:48 +03:00
Linus Torvalds
3f06962273 This pull-request contains the following changes for MTD:
MTD core changes:
 - New Hyperbus framework
 - New _is_locked (concat) implementation
 - Various cleanups
 
 NAND core changes:
 - use longest matching pattern in ->exec_op() default parser
 - export NAND operation tracer
 - add flag to indicate panic_write in MTD
 - use kzalloc() instead of kmalloc() and memset()
 
 Raw NAND controller drivers changes:
 - brcmnand:
   * fix BCH ECC layout for large page NAND parts
   * fallback to detected ecc-strength, ecc-step-size
   * when oops in progress use pio and interrupt polling
   * code refactor code to introduce helper functions
   * add support for v7.3 controller
 - FSMC:
   * use nand_op_trace for operation tracing
 - GPMI:
   * move all driver code into single file
   * various cleanups (including dmaengine changes)
   * use runtime PM to manage clocks
   * implement exec_op
 - MTK:
   * correct low level time calculation of r/w cycle
   * improve data sampling timing for read cycle
   * add validity check for CE# pin setting
   * fix wrongly assigned OOB buffer pointer issue
   * re-license MTK NAND driver as Dual MIT/GPL
 - STM32:
   * manage the get_irq error case
   * increase DMA completion timeouts
 
 Raw NAND chips drivers changes:
 - Macronix: add read-retry support
 
 Onenand driver changes:
 - add support for 8Gb datasize chips
 - avoid fall-through warnings
 
 SPI-NAND changes:
 - define macros for page-read ops with three-byte addresses
 - add support for two-byte device IDs and then for GigaDevice
   GD5F1GQ4UFxxG
 - add initial support for Paragon PN26G0xA
 - handle the case where the last page read has bitflips
 
 SPI-NOR core changes:
 - add support for the mt25ql02g and w25q16jv flashes
 - print error in case of jedec read id fails
 - is25lp256: add post BFPT fix to correct the addr_width
 
 SPI NOR controller drivers changes:
 - intel-spi: Add support for Intel Elkhart Lake SPI serial flash
 - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c
 - cadence-quadspi: add reset control
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Merge tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD updates from Miquel Raynal:
 "This contains the following changes for MTD:

  MTD core changes:
   - New Hyperbus framework
   - New _is_locked (concat) implementation
   - Various cleanups

  NAND core changes:
   - use longest matching pattern in ->exec_op() default parser
   - export NAND operation tracer
   - add flag to indicate panic_write in MTD
   - use kzalloc() instead of kmalloc() and memset()

  Raw NAND controller drivers changes:
   - brcmnand:
       - fix BCH ECC layout for large page NAND parts
       - fallback to detected ecc-strength, ecc-step-size
       - when oops in progress use pio and interrupt polling
       - code refactor code to introduce helper functions
       - add support for v7.3 controller
   - FSMC:
       - use nand_op_trace for operation tracing
   - GPMI:
       - move all driver code into single file
       - various cleanups (including dmaengine changes)
       - use runtime PM to manage clocks
       - implement exec_op
   - MTK:
       - correct low level time calculation of r/w cycle
       - improve data sampling timing for read cycle
       - add validity check for CE# pin setting
       - fix wrongly assigned OOB buffer pointer issue
       - re-license MTK NAND driver as Dual MIT/GPL
   - STM32:
       - manage the get_irq error case
       - increase DMA completion timeouts

  Raw NAND chips drivers changes:
   - Macronix: add read-retry support

  Onenand driver changes:
   - add support for 8Gb datasize chips
   - avoid fall-through warnings

  SPI-NAND changes:
   - define macros for page-read ops with three-byte addresses
   - add support for two-byte device IDs and then for GigaDevice
     GD5F1GQ4UFxxG
   - add initial support for Paragon PN26G0xA
   - handle the case where the last page read has bitflips

  SPI-NOR core changes:
   - add support for the mt25ql02g and w25q16jv flashes
   - print error in case of jedec read id fails
   - is25lp256: add post BFPT fix to correct the addr_width

  SPI NOR controller drivers changes:
   - intel-spi: Add support for Intel Elkhart Lake SPI serial flash
   - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c
   - cadence-quadspi: add reset control"

* tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (60 commits)
  mtd: concat: implement _is_locked mtd operation
  mtd: concat: refactor concat_lock/concat_unlock
  mtd: abi: do not use C++ style comments in uapi header
  mtd: afs: remove unneeded NULL check
  mtd: rawnand: stm32_fmc2: increase DMA completion timeouts
  mtd: rawnand: Use kzalloc() instead of kmalloc() and memset()
  mtd: hyperbus: Add driver for TI's HyperBus memory controller
  mtd: spinand: read returns badly if the last page has bitflips
  mtd: spinand: Add initial support for Paragon PN26G0xA
  mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPL
  mtd: rawnand: gpmi: remove double assignment to block_size
  dt-bindings: mtd: brcmnand: Add brcmnand, brcmnand-v7.3 support
  mtd: rawnand: brcmnand: Add support for v7.3 controller
  mtd: rawnand: brcmnand: Refactored code to introduce helper functions
  mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling
  mtd: Add flag to indicate panic_write
  mtd: rawnand: Add Macronix NAND read retry support
  mtd: onenand: Avoid fall-through warnings
  mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG
  mtd: spinand: Add support for two-byte device IDs
  ...
2019-07-13 15:42:44 -07:00
Liu Xiang
cf580a9240
mtd: spi-nor: fix nor->addr_width when its value configured from SFDP does not match the actual width
IS25LP256 gets BFPT_DWORD1_ADDRESS_BYTES_3_ONLY from BFPT table for
address width. But in actual fact the flash can support 4-byte address.
Use a post bfpt fixup hook to overwrite the address width advertised by
the BFPT.

Signed-off-by: Liu Xiang <liu.xiang6@zte.com.cn>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-06-27 17:13:22 +03:00
Tudor Ambarus
191f5c2ed4 mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes
SPI memory devices from different manufacturers have widely
different configurations for Status, Control and Configuration
registers. JEDEC 216C defines a new map for these common register
bits and their functions, and describes how the individual bits may
be accessed for a specific device. For the JEDEC 216B compliant
flashes, we can partially deduce Status and Configuration registers
functions by inspecting the 16th DWORD of BFPT. Older flashes that
don't declare the SFDP tables (SPANSION FL512SAIFG1 311QQ063 A ©11
SPANSION) let the software decide how to interact with these registers.

The commit dcb4b22eea ("spi-nor: s25fl512s supports region locking")
uncovered a probe error for s25fl512s, when the Quad Enable bit CR[1]
was set to one in the bootloader. When this bit is one, only the Write
Status (01h) command with two data byts may be used, the 01h command with
one data byte is not recognized and hence the error when trying to clear
the block protection bits.

Fix the above by using the Write Status (01h) command with two data bytes
when the Quad Enable bit is one.

Backward compatibility should be fine. The newly introduced
spi_nor_spansion_clear_sr_bp() is tightly coupled with the
spansion_quad_enable() function. Both assume that the Write Register
with 16 bits, together with the Read Configuration Register (35h)
instructions are supported.

Fixes: dcb4b22eea ("spi-nor: s25fl512s supports region locking")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Jonas Bonn <jonas@norrbonn.se>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-06-23 20:03:34 +02:00
Geert Uytterhoeven
2d60d1f64b
mtd: spi-nor: Spelling s/Writ/Write/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-06-22 12:10:58 +03:00
Robert Marko
88489c29de
mtd: spi-nor: Add Winbond w25q16jv support
Testing done on Mikrotik Routerboard RB450Gx4 board under
4.14.119 and 4.19.43 kernels. The test board does not support
Dual or Quad modes.

Datasheet at:
https://www.winbond.com/resource-files/w25q16jv%20spi%20revg%2003222018%20plus.pdf

Signed-off-by: Robert Marko <robimarko@gmail.com>
[tudor.ambarus@microchip.com: w25q16jv-im/jm and w25q16jv-iq/jq
have different jedec ids, fix flash name.]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-06-22 12:03:02 +03:00
Flavio Suligoi
92aae4ce84
mtd: spi-nor: change "error reading JEDEC id" from dbg to err
In case of SPI error during the reading of the nor Id,
the probe fails without any error message related to
the JEDEC Id reading procedure.

Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-06-07 07:49:41 +03:00
Andrey Smirnov
21ed90acd1
mtd: spi-nor: Add Micron MT25QL02 support
Add an entry for Micron MT25QL02 which is a 3V variant of already
supported MT25QU02.

Testing was done on a ZII VF610 Dev Board (rev. B).

Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: linux-mtd@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
[tudor.ambarus@microchip.com: order entry alphabetically, wrap to
80 chars limit]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-06-07 07:10:39 +03:00
Jonas Bonn
dcb4b22eea spi-nor: s25fl512s supports region locking
Both the BP[0-2] bits and the TBPROT bit are supported on this chip.
Tested and verified on a Cypress s25fl512s.

Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-01 14:37:42 +02:00
Alexander Sverdlin
706707341b mtd: spi-nor: Fix comment of spi_nor_find_best_erase_type()
Erase types are sorted *smallest* type first, refer to
spi_nor_sort_erase_mask().

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21 17:24:32 +01:00
Geert Uytterhoeven
3ddc8adbbc mtd: spi-nor: Print all JEDEC ID bytes on error
If identification of an SPI NOR FLASH fails, the JEDEC ID is printed,
which is stored in the first 3 bytes of the ID read from the FLASH.
However, the extended JEDEC ID, which is stored in the remaining bytes,
also matters, as it is used for identification of some FLASH types.

Print all (currently 6) ID bytes read to ease failure analysis and
debugging.

Suggested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21 17:24:11 +01:00
Roger Pueyo Centelles
30a2c8aa3c mtd: spi-nor: Add support for en25qh64
The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip found
on recent wireless routers. Its 32, 128 and 256 Mbit siblings
are already supported.

Tested on a COMFAST CF-E120A v3 router board.

Signed-off-by: Roger Pueyo Centelles <roger.pueyo@guifi.net>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-21 08:57:18 +01:00