Commit Graph

548476 Commits

Author SHA1 Message Date
Vladimir Zapolskiy
4d5821a71c drm/sti: hdmi use of_get_i2c_adapter_by_node interface
This change is needed to properly lock I2C bus device and driver,
which serve DDC lines. Without this change I2C bus driver module
may gone in runtime and this won't be noticed by the driver.

Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2015-11-03 13:04:54 +01:00
Vladimir Zapolskiy
807642d731 drm/sti: hdmi fix i2c adapter device refcounting
The commit 53bdcf5f02 ("drm: sti: fix sub-components bind") moves
i2c adapter search and locking from .bind() to .probe(), however
proper error path in the modified .probe() is not implemented and
leftover of the related error path in .bind() remains. This change
fixes these issues.

Fixes: 53bdcf5f02 ("drm: sti: fix sub-components bind")
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2015-11-03 13:04:54 +01:00
Thierry Reding
3a36e186ba drm/sti: Do not export symbols
None of these exported symbols are used outside of the drm-sti driver,
so there is no reason to export them.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2015-11-03 13:04:54 +01:00
Thierry Reding
dcec16efd6 drm/sti: Build monolithic driver
There's no use building the individual drivers as separate modules
because they are all only useful if combined into a single DRM/KMS
device.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2015-11-03 13:04:54 +01:00
Thierry Reding
2388693e10 drm/sti: Use drm_crtc_vblank_*() API
Non-legacy drivers should only use this API to allow per-CRTC data to be
eventually moved into struct drm_crtc.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2015-11-03 13:04:53 +01:00
Thierry Reding
df00d029d7 drm/sti: Store correct CRTC index in events
A negative pipe causes a special case to be triggered for drivers that
don't have proper VBLANK support. STi does support VBLANKs, so there is
no need for the fallback code.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2015-11-03 13:04:53 +01:00
Thierry Reding
1352be6eb0 drm/sti: Select FW_LOADER
Select FW_LOADER explicitly to satify the direct dependency of
FW_LOADER_USER_HELPER_FALLBACK.

Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-03 13:04:53 +01:00
Ville Syrjälä
c5de48539c drm/sti: Constify function pointer structs
Moves a bunch of junk to .rodata from .data.

 drivers/gpu/drm/sti/sticompositor.ko:
-.text                       12216
+.text                       12212
-.rodata                      1284
+.rodata                      1400
-.data                         488
+.data                         372

 drivers/gpu/drm/sti/sti_drv.ko:
-.rodata                      516
+.rodata                      544
-.data                        368
+.data                        340

 drivers/gpu/drm/sti/stidvo.ko:
-.text                       3356
+.text                       3348
-.rodata                      188
+.rodata                      256
-.data                        572
+.data                        504

 drivers/gpu/drm/sti/sti_hda.ko:
-.text                       3008
+.text                       3004
-.rodata                     2820
+.rodata                     2888
-.data                        684
+.data                        616

 drivers/gpu/drm/sti/stihdmi.ko:
-.text                        6988
+.text                        6980
-.rodata                      1340
+.rodata                      1408
-.data                         176
+.data                         108

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-03 13:04:53 +01:00
Dave Airlie
1c431cb461 Merge branch 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- Vast improvements to gk20a instmem handling.
- Improved PGOB detection + GK107 support.
- Compatibility between old/new interfaces added, final missing piece to
finally enabling userspace to start using them.
- Kepler GDDR5 PLL stability improvements
- Support for non-GPIO (PWM) voltage controllers
- G8x/GT2xx memory clock improvements
- Misc other fixes

* 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (45 commits)
  drm/nouveau: bump patchlevel to indicate availability of abi16/nvif interop
  drm/nouveau/abi16: implement limited interoperability with usif/nvif
  drm/nouveau/abi16: introduce locked variant of nouveau_abi16_get()
  drm/nouveau/abi16: remove unused argument from nouveau_abi16_get()
  drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
  drm/nouveau/pci: enable c800 magic for Lenovo Y510P
  drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5
  drm/nouveau/clk/g84: Enable reclocking for GDDR3 G94-G200
  drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristic
  drm/nouveau/fb/ramnv50: Script changes for G94 and up
  drm/nouveau/fb/ramnv50: Deal with cards without timing entries
  drm/nouveau/fb/ramnv50: Voltage GPIOs
  drm/nouveau/fb/ramgt215: Restructure r111100 calculation for DDR2
  drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for it
  drm/nouveau/fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to generic
  drm/nouveau/bios/rammap: Identify DLLoff for >= GF100
  drm/nouveau/pci: Handle 5-bit and 8-bit tag field
  drm/nouveau/disp,pm: constify nvkm_object_func structures
  drm/nouveau/gr: add FERMI_COMPUTE_B class to GF110+
  drm/nouveau/gr: document mp error 0x10
  ...
2015-11-03 15:42:59 +10:00
Dave Airlie
b459004796 Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
This pull request includes comprehensive cleanups to HDMI part and
   several fixups. In addition, this pull request includes also a defconfig
   patch which enables mixer driver as default. For this, I got already
   Acked-by from Krzysztof Kozlowski who is a Exynos SoC maintainer.

* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (34 commits)
  drm/exynos/gem: remove DMA-mapping hacks used for constructing page array
  ARM: exynos_defconfig: enable Exynos DRM Mixer driver
  drm/exynos: simplify Kconfig component names
  drm/exynos: re-arrange Kconfig entries
  drm/exynos: abstract out common dependency
  drm/exynos: separate Mixer and HDMI drivers
  drm/exynos/mixer: replace direct cross-driver call with drm mode validation
  drm/exynos: add atomic_check callback to exynos_crtc
  drm/exynos/decon5433: add support for DECON-TV
  drm/exynos/decon5433: remove duplicated initialization
  drm/exynos/decon5433: merge different flag fields
  drm/exynos/decon5433: add function to set particular register bits
  drm/exynos/decon5433: fix timing registers writes
  drm/exynos/decon5433: add PCLK clock
  drm/exynos: cleanup name of gem object for exynos_drm
  drm/exynos: fix to detach device of iommu
  drm/exynos: add cursor plane support
  drm/exynos: add global macro for the default primary plane
  drm/exynos: fix spelling errors
  drm: exynos: mixer: fix using usleep() in atomic context
  ...
2015-11-03 15:42:10 +10:00
Ben Skeggs
79ef5dca5e drm/nouveau: bump patchlevel to indicate availability of abi16/nvif interop
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
2621a41647 drm/nouveau/abi16: implement limited interoperability with usif/nvif
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
786a57ef2c drm/nouveau/abi16: introduce locked variant of nouveau_abi16_get()
USIF already takes the client mutex, but will need access to ABI16 data
in order to provide some limited interoperability.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
09433f24e6 drm/nouveau/abi16: remove unused argument from nouveau_abi16_get()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin
b41c48571d drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin
a2736b07df drm/nouveau/pci: enable c800 magic for Lenovo Y510P
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Karol Herbst
78eaf335e4 drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5
This patch uses an approach closer to the nvidia driver to configure
both PLLs for high gddr5 memory clocks (usually above 2400MHz)

Previously nouveau used the one PLL as it was used for the lower clocks
and just adjusted the second PLL to get as close as possible to the
requested clock.  This means for my card, that I got a 4050 MHz clock
although 4008 MHz was requested.

Now the driver iterates over a list of PLL configuration also used by
the nvidia driver and then adjust the second PLL to get near the
requested clock.  Also it hold to some restriction I found while
analyzing the PLL configurations

This won't fix all gddr5 high clock issues itself, but it should be
fine on hybrid gpu systems as found on many laptops these days.  Also
switching while normal desktop usage should be a lot more stable than
before.

v2: move the pll code into ramgk104

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
0d42743dfa drm/nouveau/clk/g84: Enable reclocking for GDDR3 G94-G200
Your milage may vary, as it's only been tested on a single G94 and one G96.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
271c27665c drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristic
Avoids waiting for VBLANKS that never arrive on headless or otherwise
unconventional set-ups. Strategy taken from MEMX.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
4d9faafa0f drm/nouveau/fb/ramnv50: Script changes for G94 and up
10053c is not even read on some cards, and I have no idea exactly what the
criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables
all features that are never used. The practical effect should be the same
as this implementation though.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
797eb6ed8f drm/nouveau/fb/ramnv50: Deal with cards without timing entries
Like Pierre's G94. We might want to structure Kepler similarly in a follow-up.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
1cf688dd1b drm/nouveau/fb/ramnv50: Voltage GPIOs
Does not seem to be necessary for NVA0, hence untested by me.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
0b0b78cd7d drm/nouveau/fb/ramgt215: Restructure r111100 calculation for DDR2
Seems to be mostly equal to DDR3 on < GT218, should improve stability for
DDR2 reclocks.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
ef6e8f4c7f drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for it
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
e0a37f85fc drm/nouveau/fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to generic
In preparation of changing FBVDDQ, as observed on at least one GDDR3 card.
While at it, adhere to func.log[1] properly for consistency.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Roy Spliet
b4f2bf33bb drm/nouveau/bios/rammap: Identify DLLoff for >= GF100
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Pierre Moreau
5d5b43f59b drm/nouveau/pci: Handle 5-bit and 8-bit tag field
If the hardware supports extended tag field (8-bit ones), then enable it.

This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).

In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.

Fixes: fdo#86537

v2: Restrict changes to chipsets >= 0x84
v3:
  * Add nvkm_pci_mask to pci.h
  * Mask bit 8 before setting it
v4:
  * Rename `add` argument of nvkm_pci_mask to `value`
  * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
    checks
v5:
  * Rebase code on latest PCI structure
  * Restore PCIe check
  * Fix namings in nvkm_pci_mask
  * Rephrase part of the commit message

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Julia Lawall
354a224966 drm/nouveau/disp,pm: constify nvkm_object_func structures
These nvkm_object_func structures are never modified.  All other
nvkm_object_func structures are declared as const.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin
2e69a5cd25 drm/nouveau/gr: add FERMI_COMPUTE_B class to GF110+
GF110+ supports both the A and B compute classes, make sure to accept
both.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin
3988f645f0 drm/nouveau/gr: document mp error 0x10
NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE,
which apparently happens when trying to use an atomic operation on
local or shared memory (instead of global memory).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Sudip Mukherjee
bad4274a69 drm/nouveau: fix memory leak
If pm_runtime_get_sync() we were going to "out" but we missed freeing
vma.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Sudip Mukherjee
4458c5639b drm/nouveau: remove unused function
coverity.com reported that memset was using a buffer of size 0, on
checking the code it turned out that the function was not being used. So
remove it.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
3c9aca3181 drm/nouveau/pmu/gk107: enable PGOB codepaths
Reported to be needed as per fdo#70354 comment #61.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
560f989fe4 drm/nouveau/pmu/gk104: check fuse to determine presence of PGOB
Not 100% confirmed, but seems to match from the few boards I've looked
at so far.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
779d16aacc drm/nouveau/pci: prepare for chipset-specific initialisation tasks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
c4266a9c7b drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default
Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
b31505c472 drm/nouveau/pci/g94: split implementation from nv40
An upcoming patch will implement functionality that we don't use on any
NV40 chipset.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
3e55b53bc7 drm/nouveau/pci/g84: split implementation from nv50
An upcoming patch will implement functionality that we don't use on the
original NV50.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Samuel Pitoiset
b6afa2650c drm/nouveau/ibus/gf100: increase wait timeout to avoid read faults
Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.

This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres
24580d1c31 drm/nouveau/gm204/6: add voltage control using the new gk104 volt class
I got confirmation that we can read and change the voltage with the same code.
The divider is also computed correctly on the gm204 we got our hands on.

Thanks to Yoshimo on IRC for executing the tests on his gm204!

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres
dc47700f7d drm/nouveau/gm107: add voltage control using the new gk104 volt class
Let's ignore the other desktop Maxwells until I get my hands on one and confirm
that we still can change the voltage.

Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03 15:02:18 +10:00
Martin Peres
1531dbbb56 drm/nouveau/volt/gk104: add support for pwm and gpio modes
Most Keplers actually use the GPIO-based voltage management instead of the new
PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles
the case where no GPIOs exist.

All the Maxwells seem to use the PWM method though.

v2:
 - Do not forget to commit the PWM configuration change!

Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03 15:02:18 +10:00
Martin Peres
4c58a05b4a drm/nouveau/volt: add support for non-vid-based voltage controllers
This patch is not ideal but it definitely beats a rewrite of the current
interface and is very self-contained.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres
7bddeba966 drm/nouveau/bios/volt: add support for pwm-based volt management
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot
b31cf78b93 drm/nouveau/ttm: set the DMA mask for platform devices
So far the DMA mask was not set for platform devices, which limited them
to a 32-bit physical space. Allow dma_set_mask() to be called for
non-PCI devices, and also take the IOMMU bit into account since it could
restrict the physically addressable space.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot
524883bb48 drm/nouveau/ttm: convert to DMA API
The pci_dma_* functions are now superseeded in the kernel by the DMA
API. Make the conversion to this more generic API.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot
68b566534c drm/nouveau/instmem/gk20a: make use of the IOMMU bit
Use the IOMMU bit specified in platform data instead of hardcoding it to
the bit used by current Tegra GPUs.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot
e396ecd178 drm/nouveau/platform: allow to specify the IOMMU bit
Current Tegra code taking advantage of the IOMMU assumes a hardcoded
value for the IOMMU bit. Make it a platform property instead for
flexibility.

v2 (Ben Skeggs): remove nvkm dependence on drm structures

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Alexandre Courbot
69c4938249 drm/nouveau/instmem/gk20a: use direct CPU access
The Great Nouveau Refactoring Take II brought us a lot of goodness,
including acquire/release methods that are called before and after an
instobj is modified. These functions can be used as synchronization
points to manage CPU/GPU coherency if we modify an instobj using the
CPU.

This patch replaces the legacy and slow PRAMIN access for gk20a instmem
with CPU mappings and writes. A LRU list is used to unmap unused
mappings after a certain threshold (currently 1MB) of mapped instobjs is
reached. This allows mappings to be reused most of the time.

Accessing instobjs using the CPU requires to maintain the GPU L2 cache,
which we do in the acquire/release functions. This triggers a lot of L2
flushes/invalidates, but most of them are performed on an empty cache
(and thus return immediately), and overall context setup performance
greatly benefits from this (from 250ms to 160ms on Jetson TK1 for a
simple libdrm program).

Making L2 management more explicit should allow us to grab some more
performance in the future.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
fcf3f91c34 drm/nouveau: remove unnecessary usage of object handles
No longer required in a lot of cases, as objects are identified over NVIF
via an alternate mechanism since the rework.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00