There is no need to set PCI bus mastering when device is not doing any DMA. It
includes MSI type of interrupts. Currently only UART on Denverton, which is DMA
capable, might have MSI enabled.
Taking above into account enable bus mastering for Denverton case only.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Enable MSI type of interrupt if PCI BIOS supports it.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Starting from Tangier B0 and continuing on Anniedale the HSU DMA interrupt
line is actually shared with UART. Handling them independently is racy and
quite often comes with the following traceback.
irq 54: nobody cared (try booting with the "irqpoll" option)
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.9.0-rc6-edison64-86244934+ #1
Hardware name: Intel Corporation Merrifield/BODEGA BAY, BIOS 542 2015.01.21:18.19.48
ffff88003f203eb0 ffffffff8130e718 ffff880032627000 ffff88003262709c
ffff88003f203ed8 ffffffff810a3960 ffff880032627000 0000000000000000
ffff880032627000 ffff88003f203f10 ffffffff810a3cc7 ffff880032627000
Call Trace:
<IRQ>
[<ffffffff8130e718>] dump_stack+0x4d/0x65
[<ffffffff810a3960>] __report_bad_irq+0x30/0xc0
[<ffffffff810a3cc7>] note_interrupt+0x227/0x270
[<ffffffff810a1380>] handle_irq_event_percpu+0x40/0x50
[<ffffffff810a13b7>] handle_irq_event+0x27/0x50
[<ffffffff810a42d5>] handle_fasteoi_irq+0x85/0x150
[<ffffffff8101d7fe>] handle_irq+0x6e/0x120
[<ffffffff8105b8bc>] ? _local_bh_enable+0x1c/0x50
[<ffffffff8101d0d6>] do_IRQ+0x46/0xd0
[<ffffffff818cef3f>] common_interrupt+0x7f/0x7f
<EOI>
[<ffffffff818cdead>] ? mwait_idle+0x7d/0x140
[<ffffffff81024c9a>] arch_cpu_idle+0xa/0x10
[<ffffffff818ce150>] default_idle_call+0x20/0x30
[<ffffffff810908fd>] cpu_startup_entry+0x16d/0x1d0
[<ffffffff818c882d>] rest_init+0x6d/0x70
[<ffffffff81f93e8f>] start_kernel+0x3e2/0x3ef
[<ffffffff81f9343d>] x86_64_start_reservations+0x38/0x3a
[<ffffffff81f93529>] x86_64_start_kernel+0xea/0xed
handlers:
[<ffffffff81411670>] serial8250_interrupt
Disabling IRQ #54
Fix this by handling interrupt only in one place.
The issue is discussed here: https://github.com/andy-shev/linux/issues/5
Moreover this also fixes another bug when Rx DMA returns wrong residue and we
can't rely on it.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Fix the following Calltrace:
[ 77.768221] WARNING: CPU: 5 PID: 645 at drivers/dma/dmaengine.c:1069 dma_async_device_unregister+0xe2/0xf0
[ 77.775058] dma_async_device_unregister called while 1 clients hold a reference
[ 77.825048] CPU: 5 PID: 645 Comm: sh Not tainted 4.8.8-WR9.0.0.0_standard+ #3
[ 77.832550] Hardware name: Intel Corp. Aspen Cove/Server, BIOS HAVLCRB1.X64.0012.D58.1604140405 04/14/2016
[ 77.840396] 0000000000000000 ffffc90008adbc80 ffffffff81403456 ffffc90008adbcd0
[ 77.848245] 0000000000000000 ffffc90008adbcc0 ffffffff8105e2e1 0000042d08adbf20
[ 77.855934] ffff88046a861c18 ffff88046a85c420 ffffffff820d4200 ffff88046ae92318
[ 77.863601] Call Trace:
[ 77.871113] [<ffffffff81403456>] dump_stack+0x4f/0x69
[ 77.878655] [<ffffffff8105e2e1>] __warn+0xd1/0xf0
[ 77.886102] [<ffffffff8105e34f>] warn_slowpath_fmt+0x4f/0x60
[ 77.893508] [<ffffffff814187a9>] ? find_next_bit+0x19/0x20
[ 77.900730] [<ffffffff814bf83e>] ? dma_channel_rebalance+0x23e/0x270
[ 77.907814] [<ffffffff814bfee2>] dma_async_device_unregister+0xe2/0xf0
[ 77.914992] [<ffffffff814c53aa>] hsu_dma_remove+0x1a/0x60
[ 77.921977] [<ffffffff814ee14c>] dnv_exit+0x1c/0x20
[ 77.928752] [<ffffffff814edff6>] mid8250_remove+0x26/0x40
[ 77.935607] [<ffffffff8144f1b9>] pci_device_remove+0x39/0xc0
[ 77.942292] [<ffffffff8160cfea>] __device_release_driver+0x9a/0x140
[ 77.948836] [<ffffffff8160d0b3>] device_release_driver+0x23/0x30
[ 77.955364] [<ffffffff81447dcc>] pci_stop_bus_device+0x8c/0xa0
[ 77.961769] [<ffffffff81447f0a>] pci_stop_and_remove_bus_device_locked+0x1a/0x30
[ 77.968113] [<ffffffff81450d4e>] remove_store+0x5e/0x70
[ 77.974267] [<ffffffff81607ed8>] dev_attr_store+0x18/0x30
[ 77.980243] [<ffffffff8123006a>] sysfs_kf_write+0x3a/0x50
[ 77.986180] [<ffffffff8122f5ab>] kernfs_fop_write+0x10b/0x190
[ 77.992118] [<ffffffff811bf1c8>] __vfs_write+0x18/0x40
[ 77.998032] [<ffffffff811bfdee>] vfs_write+0xae/0x190
[ 78.003747] [<ffffffff811c1016>] SyS_write+0x46/0xb0
[ 78.009234] [<ffffffff81a4c31b>] entry_SYSCALL_64_fastpath+0x13/0x8f
[ 78.014809] ---[ end trace 0c36dd73b7408eb2 ]---
This happens when the 8250 serial controller is hotplugged as follows:
echo 1 > /sys/bus/pci/devices/0000:00:1a.0/remove
This trace happens due to the serial port still holding a reference when
the dma device is unregistered.
The dma unregister routine will check if there is still a reference exist,
if so it will give the WARNING(here serial port still was not unregister).
To fix this, We need to unregister the serial port first, then do DMA
device unregister to make sure there is no reference when to DMA routine.
Signed-off-by: Liwei Song <liwei.song@windriver.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Since we have nice macro IRQ_RETVAL() we would use it to convert a flag of
handled interrupt from int to irqreturn_t.
The rationale of doing this is:
a) hence we implicitly mark hsu_dma_do_irq() as an auxiliary function that
can't be used as interrupt handler directly, and
b) to be in align with serial driver which is using serial8250_handle_irq()
that returns plain int by design.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Since the commit c1a67b48f6 ("serial: 8250_pci: replace switch-case by
formula for Intel MID"), the 8250 driver crashes in the byt_set_termios()
function with a divide error. This is caused by the fact that a baud rate of 0
(B0) is not handled properly. Fix it by falling back to B9600 in this case.
Reported-by: "Mendez Salinas, Fernando" <fernando.mendez.salinas@intel.com>
Fixes: c1a67b48f6 ("serial: 8250_pci: replace switch-case by formula for Intel MID")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In DNV, when RX DMA is used and number of bytes received is less than
transfer size, only RX DMA timeout interrupt is sent. When this happens,
read the RX buffer.
Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To allow other code to safely read DMA Channel Status Register (where
the register attribute for Channel Error, Descriptor Time Out &
Descriptor Done fields are read-clear), export hsu_dma_get_status().
hsu_dma_irq() is renamed to hsu_dma_do_irq() and requires Status
Register value to be passed in.
Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
On Intel Penwell and Tangier the HSU block (3 HSU ports) has a global register
set which is currently not used by the driver. On Tangier it has it's own PCI
device and thus available for enumeration. Since it's not a real HSU port we
just skip it and therefore put a comment in the code why we do so.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The BIT() macro, that is definded in bitops.h, is used in the driver. Include
necessary header for that.
While here, reorder included headers alphabetically.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
There is a special register that shows interrupt status by source. In
particular case the source can be a combination of DMA Tx, DMA Rx, and UART.
Read the register and call the handlers only for sources that request an
interrupt.
Fixes: 6ede6dcd87 ("serial: 8250_mid: add support for DMA engine handling from UART MMIO")
Cc: stable@vger.kernel.org
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Unlike Intel Medfield and Tangier platforms DNV uses PCI BAR0 for IO compatible
resources and BAR1 for MMIO. We need latter in a way to support DMA. Introduce
an additional field in the internal structure and pass PCI BAR based on device
ID.
Reported-by: "Lai, Poey Seng" <poey.seng.lai@intel.com>
Fixes: 6ede6dcd87 ("serial: 8250_mid: add support for DMA engine handling from UART MMIO")
Cc: stable@vger.kernel.org
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The platforms that have this UART, but that don't have
separate PCI device for the DMA Engine, need to create the
HSU DMA Engine device separately.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Intel MID UART quirks require already quite a bit of code
in 8250_pci.c. On new Intel platforms where it is used, the
integrated DMA engine no longer has its own PCI device, but
is instead configured from the UART's MMIO. That means we
will have to add even more code for handling just MID UARTs.
Instead of adding that to 8250_pci.c, splitting the support
of Intel MID UART into its own driver. Handling of the
integrated DMA engine becomes much simpler this way. Own
driver will also remove the need for things like specific
set_termios hooks for every board using this UART, and
simplify the handling of it in general.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
