Replace construct that matches generic_handle_irq(irq_find_mapping())
to a single call to generic_handle_domain_irq().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
For the size-based communities, always use gpp_num_padown_regs,
which is now provided explicitly via INTEL_COMMUNITY_SIZE() macro.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_*() common macro instead custom SPT_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom TGL_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom MTL_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_SIZE() common macro instead custom LBG_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom LKF_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom JSL_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom ICL_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_SIZE() common macro instead custom GLK_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom EBG_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom EHL_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom DNV_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom CDF_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom CNL_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_SIZE() common macro instead custom BXT_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use INTEL_COMMUNITY_GPPS() common macro instead custom ADL_COMMUNITY().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Now it becomes visible that we can deduplicate SoC specific
*_COMMUNITY() macros across the Intel pin control drivers.
For that, introduce a common INTEL_COMMUNITY_GPPS() and
INTEL_COMMUNITY_SIZE() macros in the pinctrl-intel.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Core changes:
- Minor but nice and important documentation clean-ups.
New drivers:
- New subdriver for the Qualcomm SDM670 SoC.
- New subdriver for the Intel Moorefield SoC.
- New trivial support for the NXP Freescale i.MXRT1170 SoC.
Other changes and improvements
- A major clean-up of the Qualcomm pin control device tree bindings
by Krzysztof.
- A major header clean-up by Andy.
- Some immutable irqchip clean-up for the Actions Semiconductor
and Nuvoton drivers.
- GPIO helpers for The Cypress cy8c95x0 driver.
- Bias handling in the Mediatek MT7986 driver.
- Remove the unused pins-are-numbered concept that never flew.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmOXJjQACgkQQRCzN7AZ
XXOMaxAAuAv30XWa9sq5cMZKOlY3CLudZmxF5V7PSpFwAXiBPcPZu9ajxlaGJaAf
+KOgJhNKYhTb4mBxsQR3X749qFFlxnbEXo9u7ka2bb5bCEkP6ZooqKSGclzAufrp
azf1pmJYd2PoaZzwhpuosiWAzLNTeZBQPapU/d9KFIkNhvvY8dFG8YWrjV6YSMTr
6sPWj7/FCqxAzplrQRUXapS+k5JyihyY4aHcFgJwijN6qmSRCxc49SA4VQvkZQZ3
AP6NV1sX9JvbfgOm09Uk5doBnX4vyfeEshOq/c+XZVyr+ECzlGQARkgOXpPhPA8S
28bY6aDaiu5HzOBauM4bp0Z4W7m7YWKWo1cDZNPVEAMF/oATOj/h3YFhLAy66RtV
8BqEEXKvVwqGu0/utwlB1I+yLXvS0DN9C+TZ2y2aLfkgRHUonRrS1OKa0SSvvQp3
3eXmwTJgqf01bcK7kkdDr6+1H6lRmol27Gir6We5jdOCu0LqQcSIYhCr0RzSirWm
CHIZQTfo7J4S7pOrz7lhsFciqEQeQfsKXmSorLHrVNcGamIZZEdRhEqVxufqRU4B
0hWoNqxjIDcqyZFFUe211OwNWNOUwMdvw5bCVkmhW5e7AylTrOi1ie1b/SlmDxRl
k7NSVnIXdZmog0fYsSZy6qJM0FfTKXF7smnuZcBvgx61/MoCRDw=
=PhTP
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"The two large chunks is the header clean-up from Andy and the Qualcomm
DT bindings clean-up from Krzysztof. Each which could give rise to
conflicts, but I haven't seen any.
The YAML conversions happening around the device tree is the biggest
item in the series and is the result of Rob Herrings ambition to
autovalidate these trees against strict schemas and it is paying off
in lots of bugs found and ever prettier device trees. Sooner or later
the transition will be complete, Krzysztof is fixing up all of the
Qualcomm stuff, which is pretty voluminous.
Core changes:
- minor but nice and important documentation clean-ups
New drivers:
- subdriver for the Qualcomm SDM670 SoC
- subdriver for the Intel Moorefield SoC
- trivial support for the NXP Freescale i.MXRT1170 SoC
Other changes and improvements
- major clean-up of the Qualcomm pin control device tree bindings by
Krzysztof
- major header clean-up by Andy
- some immutable irqchip clean-up for the Actions Semiconductor and
Nuvoton drivers
- GPIO helpers for The Cypress cy8c95x0 driver
- bias handling in the Mediatek MT7986 driver
- remove the unused pins-are-numbered concept that never flew"
* tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits)
pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions()
dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered
dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered
pinctrl: stm32: Remove check for pins-are-numbered
pinctrl: mediatek: common: Remove check for pins-are-numbered
pinctrl: qcom: remove duplicate included header files
pinctrl: sunxi: d1: Add CAN bus pinmuxes
pinctrl: loongson2: Fix some const correctness
pinctrl: pinconf-generic: add missing of_node_put()
pinctrl: intel: Enumerate PWM device when community has a capability
pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
pwm: lpss: Allow other drivers to enable PWM LPSS
pwm: lpss: Include headers we are the direct user of
pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
pwm: Add a stub for devm_pwmchip_add()
pinctrl: k210: call of_node_put()
pinctrl: starfive: Use existing variable gpio
dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching
pinconf-generic: fix style issues in pin_config_param doc
pinctrl: pinctrl-loongson2: fix Kconfig dependency
...
The thunderbay_add_functions() will free memory of thunderbay_funcs
when everything is ok, but thunderbay_funcs will not be freed when
thunderbay_add_functions() fails, then there will be a memory leak,
so we need to add kfree() when thunderbay_add_functions() fails to
fix it.
In addition, doing some cleaner works, moving kfree(funcs) from
thunderbay_add_functions() to thunderbay_build_functions().
Fixes: 12422af819 ("pinctrl: Add Intel Thunder Bay pinctrl driver")
Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com>
Reviewed-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20221129120126.1567338-1-cuigaosheng1@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove the check for the unnecessary pins-are-numbered Devicetree property.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20221129023401.278780-2-bero@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The firmware on some systems may configure GPIO pins to be
an interrupt source in so called "direct IRQ" mode. In such
cases the GPIO controller driver has no idea if those pins
are being used or not. At the same time, there is a known bug
in the firmwares that don't restore the pin settings correctly
after suspend, i.e. by an unknown reason the Rx value becomes
inverted.
Hence, let's save and restore the pins that are configured
as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
Cc: stable@vger.kernel.org
Reported-and-tested-by: Dale Smith <dalepsmith@gmail.com>
Reported-and-tested-by: John Harris <jmharris@gmail.com>
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=214749
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221124222926.72326-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Enable PWM feature on Intel pin control IPs
The following is an automated git shortlog grouped by driver:
intel:
- Enumerate PWM device when community has a capability
pwm:
- lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
- lpss: Allow other drivers to enable PWM LPSS
- lpss: Include headers we are the direct user of
- lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
- Add a stub for devm_pwmchip_add()
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmN9Fn8ACgkQb7wzTHR8
rCh+7RAAqQjDQi6wGEXnjWTKA0OGCoi5uqrpuCa1g1Mr+57ym9BmMHCuK3U5UWkK
cXdXq15FulfIM75v8XeKGzWjG+N9AKjrgAqnV9RU+CwQeB7ROM5vgm3+JrJOEs/n
96rtvC1wD46MvKQ9gqv57GiyI3gKQuUKM5AnofPE/tcQAINx6W+82/xO3tWzH+LY
ZTSywCEzXuMLsOBlg4GfUHS0YuN8g7go2VZ7n+D38+jR090/xwdCfLXT0VMc9i+D
lFI/1CwLGqHAVw+loUTKEZ1cQ9bOOEa618/kkQ501n24LZ+3PzdJpvA7wvR/0sjM
e6tooa6Lb7V00oxxADVY7+a4VEmBgy1n9ExJFgrC03iNal7ALY2oZvloWpyl0iYf
cAqqNiKLsuU+J1i/mMqXxlMcrZyb/5BUBzAPgrDIhu2sVtuVCXIoTPNfjkK6TaGx
4gRA3NzSoNkF554BCPdVSm2BsGos30yVRSN3hn4S9w+hzo3l4DmZzXBvDsxT3BhB
wSbXOQ1Fx65kwQRZWVyxj4+i7XTzWzc6ZOxuRN7JKclYyfN5jptqDfngczToNU67
rTZuSLP99lVrKIjTrhd3Fpq+c1VhfMndNAcT2kKJ89uMIvpUK8AcxYFR28JAqxjj
sdoUOo46o+4R9o+7vR3G1QJsWID5ZYyRBWIOxqRdXIKf9joP91Y=
=ewrB
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v6.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-2
* Enable PWM feature on Intel pin control IPs
The following is an automated git shortlog grouped by driver:
intel:
- Enumerate PWM device when community has a capability
pwm:
- lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
- lpss: Allow other drivers to enable PWM LPSS
- lpss: Include headers we are the direct user of
- lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
- Add a stub for devm_pwmchip_add()
The D1 pin controller contains muxes for two CAN buses. While the CAN
bus controllers are only documented for the T113 SoC, the pin controller
is the same across all SoC variants.
Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221126191636.6673-1-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The kernel robot using sparse is complaining like this:
drivers/pinctrl/pinctrl-loongson2.c:212:21: sparse:
sparse: incorrect type in argument 1 (different address spaces) @@
expected void const volatile [noderef] __iomem *addr @@
got void *[noderef] __iomem reg @@
(...)
I think the problem is simply that the register base is defined
as void * __iomem instead of void __iomem * and this is because
of the way const correctness works with pointer infix order.
Fix it up. I think.
Reported-by: kernel test robot <lkp@intel.com>
Cc: zhanghongchen <zhanghongchen@loongson.cn>
Cc: Yinbo Zhu <zhuyinbo@loongson.cn>
Fixes: f73f88acbc ("pinctrl: pinctrl-loongson2: add pinctrl driver support")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
of_node_put() needs to be called when jumping out of the loop, since
for_each_available_child_of_node() will increase the refcount of node.
Fixes: c7289500e2 ("pinctrl: pinconf-generic: scan also referenced phandle node")
Signed-off-by: ZhangPeng <zhangpeng362@huawei.com>
Link: https://lore.kernel.org/r/20221125070156.3535855-1-zhangpeng362@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some of the Communities may have PWM capability. In such cases,
enumerate the PWM device via respective driver. A user is still
responsible for setting correct pin muxing for the line that
needs to output the signal.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Since for_each_available_child_of_node() will increase the refcount of
node, we need to call of_node_put() manually when breaking out of the
iteration.
Fixes: d4c34d09ab ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver")
Signed-off-by: ZhangPeng <zhangpeng362@huawei.com>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Link: https://lore.kernel.org/r/20221122075853.2496680-1-zhangpeng362@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is a possibility of dividing by zero due to the pcs->bits_per_pin
if pcs->fmask() also has a value of zero and called fls
from asm-generic/bitops/builtin-fls.h or arch/x86/include/asm/bitops.h.
The function pcs_probe() has the branch that assigned to fmask 0 before
pcs_allocate_pin_table() was called
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 4e7e8017a8 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Signed-off-by: Maxim Korotkov <korotkov.maxim.s@gmail.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20221117123034.27383-1-korotkov.maxim.s@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If CONFIG_PINCTRL_LOONGSON2=y and CONFIG_OF is not set,
gcc complained about undefined reference:
drivers/pinctrl/pinctrl-loongson2.o: In function `pinconf_generic_dt_node_to_map_all':
pinctrl-loongson2.c:(.text+0x1c4): undefined reference to
`pinconf_generic_dt_node_to_map'
To fix this error, add depends on OF to
config PINCTRL_LOONGSON2.
Fixes: f73f88acbc ("pinctrl: pinctrl-loongson2: add pinctrl driver support")
Signed-off-by: Ren Zhijie <renzhijie2@huawei.com>
Link: https://lore.kernel.org/r/20221121132608.230645-1-renzhijie2@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Use dynamic GPIO base on combined pincctrl/gpio controllers on
SH/R-Mobile SoCs,
- Miscellaneous improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCY3ddhAAKCRCKwlD9ZEnx
cN+KAP9q20FIsSb7wounDiFqtxvzQlxlRZqgrAuYRvB7gIDLIgEA83kVuhkI0+Ap
hoTVhQb/waZWKZye7+AaeiWbFCvUDgU=
=VLhE
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinctrl-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.2
- Use dynamic GPIO base on combined pincctrl/gpio controllers on
SH/R-Mobile SoCs,
- Miscellaneous improvements.
* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there
The following is an automated git shortlog grouped by driver:
alderlake:
- Deduplicate COMMUNITY macro code
cannonlake:
- Deduplicate COMMUNITY macro code
device property:
- Introduce fwnode_device_is_compatible() helper
icelake:
- Deduplicate COMMUNITY macro code
intel:
- Add Intel Moorefield pin controller support
- Use temporary variable for struct device
- Use str_enable_disable() helper
merrifield:
- Use temporary variable for struct device
qcom:
- lpass-lpi: Add missed bitfield.h
soc:
- fsl: qe: Switch to use fwnode instead of of_node
sunrisepoint:
- Deduplicate COMMUNITY macro code
tigerlake:
- Deduplicate COMMUNITY macro code
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmN2GBEACgkQb7wzTHR8
rCjfwRAAnG9/iBsiB9jDEbh6ZxNVC+2IAZ4KbaDl3KWhiA8WIbuwV1V2O2YGHXtJ
W8tcHbvvfvr5FOYzxolfx0jiaQX5O5FEt1JKx0GZnqIU6TK6H3SQf7GzYP3DcAQC
RdTy+naHWyJkOz4QI7vFeRIB5AtJJfd8BtyYmBgPiXDlGDBNZes5RP8Stb4aeWjO
QFkyH/wOpkEajPuRQ+muhP40mXAqJWctw7XA0TGMOvnto7RMAmJkv/5RYXBqpGGz
+0mHuFHXrLKUfPTieRrS1HhkYi2Uva6CIqEdhTLxZf2tmL6Qswv7tCUDnjj3ScAJ
b4wQxin82fDitFd+pTmmj1vgpDWKa7rDFKpcIxBu5IsnCLOXm6XTVWroq2pGMhuy
OQLPMXdwj5mnmtSQKx7oxuvrZ4lfGpIJ1p3b3LP9iOE1gIQ3pncKZTDntpDT8hsW
P/gxRTKTNMCNCO17DPPov48wiVzxzBRYp/6H+HQEN+HRBAJNaWNxeY0vuy9o7Jwt
CYHPtUAeBUoj6lNES1QRoacW56dOcvxI5upnoFmNyIQdbp1Vr1izefdpiph/PEG9
4RwlNA/Bl3o34L3KvQZxW7q/b5QSZTA1VPIjroVVZ540B1/s+6p8dXOXLaKic87x
BUmmDIvO//lnAfEW1DQvnKajvYThhi98xttFHxUDfDRQVsE1Hrw=
=4klv
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-1
* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there
The following is an automated git shortlog grouped by driver:
alderlake:
- Deduplicate COMMUNITY macro code
cannonlake:
- Deduplicate COMMUNITY macro code
device property:
- Introduce fwnode_device_is_compatible() helper
icelake:
- Deduplicate COMMUNITY macro code
intel:
- Add Intel Moorefield pin controller support
- Use temporary variable for struct device
- Use str_enable_disable() helper
merrifield:
- Use temporary variable for struct device
qcom:
- lpass-lpi: Add missed bitfield.h
soc:
- fsl: qe: Switch to use fwnode instead of of_node
sunrisepoint:
- Deduplicate COMMUNITY macro code
tigerlake:
- Deduplicate COMMUNITY macro code
Since commit 502df79b86 ("gpiolib: Warn on drivers still using
static gpiobase allocation") in gpio/for-next, one or more warnings are
printed during boot on systems where the pin controller also provides
GPIO functionality:
gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
Fix this for ARM-based SH/R-Mobile SoCs by:
1. Taking into account a non-zero GPIO base in the various GPIO chip
callbacks,
2. Switching to dynamic allocation of the GPIO base when support for
legacy function GPIOs is not enabled.
On SuperH SoCs using legacy function GPIOs, the GPIO bases of the GPIO
controller and the GPIO function controller must not be changed, as all
board files rely on the fixed GPIO_* and GPIO_FN_* definitions provided
by the various <cpu/sh*.h> header files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/df2cf30ac4c3cbee726799f32b727c1ebe62819c.1668000684.git.geert+renesas@glider.be
The Loongson-2 SoC has a few pins that can be used as GPIOs or take
multiple other functions. Add a driver for the pinmuxing.
There is currently no support for GPIO pin pull-up and pull-down.
Signed-off-by: zhanghongchen <zhanghongchen@loongson.cn>
Co-developed-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Link: https://lore.kernel.org/r/20221114024942.8111-1-zhuyinbo@loongson.cn
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The kernel test robot complains that in certain combinations
when building the Mediatek drivers as modules we lack some
debounce table symbols, so export them.
Reported-by: kernel test robot <lkp@intel.com>
Fixes: e1ff91f9d2 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration")
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The External Interrupt Controller (EINTC) on all of the supported
MediaTek SoCs does support input debouncing, but not all of them
index the debounce time values (DBNC_SETTING registers) the same way.
Before this change, in some cases, as an example, requesting a debounce
time of 16 milliseconds would mistakenly set the relative DBNC_SETTING
register to 0x2, resulting in a way shorter debounce time of 500uS.
To fix the aforementioned issue, define three different debounce_time
arrays, reflecting the correct register index for each value and for
each register index variant, and make sure that each SoC pinctrl
driver uses the right one.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
First of all, while for_each_maps() is private to pin control subsystem
it's still better to have it put into a namespace.
Besides that, users are not relying on iterator variable, so hide it
inside for-loop.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221111120048.42968-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux
and GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Here is the BUG report by KASAN about null pointer dereference:
BUG: KASAN: null-ptr-deref in strcmp+0x2e/0x50
Read of size 1 at addr 0000000000000000 by task python3/2640
Call Trace:
strcmp
__of_find_property
of_find_property
pinctrl_dt_to_map
kasprintf() would return NULL pointer when kmalloc() fail to allocate.
So directly return ENOMEM, if kasprintf() return NULL pointer.
Fixes: 57291ce295 ("pinctrl: core device tree mapping table parsing support")
Signed-off-by: Zeng Heng <zengheng4@huawei.com>
Link: https://lore.kernel.org/r/20221110082056.2014898-1-zengheng4@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pad names for the i.MXRT1050 were incorrect. Fix them.
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Link: https://lore.kernel.org/r/20221107071511.2764628-7-Mr.Bossman075@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit fb34a9ae38 ("pinctrl: mediatek: support rsel feature")
add SoC specify 'pull_type' attribute for bias configuration.
This patch add pull_type attribute to pinctrl-mt7986.c, and make
bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit fb34a9ae38 ("pinctrl: mediatek: support rsel feature")
introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo
and mtk_pinconf_bias_get_combo, and make the functions able to support
almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c.
This patch enables pinctrl_moore to support these functions.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Correct the bias-pull-up, bias-pull-down and bias-disable register
offset of mt7986 pin-42 to pin-49, in the original driver, the
relative offset value was erroneously decremented by 1.
Fixes: 360de67280 ("pinctrl: mediatek: add support for MT7986 SoC")
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106080114.7426-5-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0
selects the GPIO function and 1 selects the special function, in these
two fields, 0 selects the special function and 1 selects the GPIO
function.
Adjust the code to handle this quirk.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20221105185911.1547847-3-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In preparation for the next patch, which makes the logic around
setting/resetting bits in MFSEL a little more complicated, move that
code to a new function
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20221105185911.1547847-2-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In pinctrl-paris we're calling the .bias_set_combo() callback when we
are asked to set the pin bias to either pull up/down or pull disable.
On newer platforms, this callback is mtk_pinconf_bias_set_combo(),
located in pinctrl-mtk-common-v2.c: this will check the "pull type"
assigned to the requested pin and in case said pin's pull type is
MTK_PULL_PU_PD_RSEL_TYPE, this function will set RSEL first, PUPD
last, which is fine.
The issue comes when we're requesting PIN_CONFIG_BIAS_DISABLE, as
this does *not* require setting RSEL but only PU_PD: in this case,
the arg is MTK_DISABLE (zero), which is not a supported RSEL, due
to which function mtk_pinconf_bias_set_rsel() returns a failure;
because of that, mtk_pinconf_bias_set_pu_pd() is never called,
hence the pin bias is never set to DISABLE.
To fix this issue, add a check to mtk_pinconf_bias_set_rsel(): if
we are entering that function with no pullup requested and at the
same time the arg is MTK_DISABLE, this means that we're trying to
disable pin bias, hence it's safe to return cleanly without ever
setting any RSEL register.
This makes mtk_pinconf_bias_set_combo() happy, going on with setting
the PU_PD registers, which is the only action to actually take to
disable bias on a pin/pingroup.
Fixes: fb34a9ae38 ("pinctrl: mediatek: support rsel feature")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221104105605.33720-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning for irqchips that are not marked with
IRQCHIP_IMMUTABLE.
Convert the pinctrl-wpcm450 driver to an immutable irqchip.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20221031222833.201322-1-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver adds pinctrl support for Intel Moorefield. The IP block
which is called Family-Level Interface Shim is a separate entity in SoC.
The GPIO driver, which supports this pinctrl interface, will be
submitted separately.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
UFS reset pin offsets are wrongly configured for SC8280XP,
correcting the same for both UFS instances here.
Signed-off-by: Anjana Hari <quic_ahari@quicinc.com>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # QDrive3
Link: https://lore.kernel.org/r/20221103181051.26912-1-quic_bjorande@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
add the logic to configure the pad wakeup function via
the pin_config_set handler.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20221027130859.1444412-5-shenwei.wang@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly.
Use the mt8365_set_clr_mode() callback to fix the issue.
Co-developed-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Link: https://lore.kernel.org/r/20221021084708.1109986-3-bchihi@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly.
Add mt8365_set_clr_mode() callback for such SoCs, so that instead of
using the SET/CLR register, use the main R/W register to
read/update/write the modes.
Co-developed-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Link: https://lore.kernel.org/r/20221021084708.1109986-2-bchihi@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The mux routes are incomplete for the PX30. This was discovered because
we had a HW design using cif-clkoutm1 with the correct pinmux in the
Device Tree but the clock would still not work.
There are actually two muxing required: the pin muxing (performed by the
usual Device Tree pinctrl nodes) and the "function" muxing (m0 vs m1;
performed by the mux routing inside the driver). The pin muxing was
correct but the function muxing was not.
This adds the missing pins and their configuration for the mux routes
that are already specified in the driver.
Note that there are some "conflicts": it is possible *in Device Tree* to
(attempt to) mux the pins for e.g. clkoutm1 and clkinm0 at the same time
but this is actually not possible in hardware (because both share the
same bit for the function muxing). Since it is an impossible hardware
design, it is not deemed necessary to prevent the user from attempting
to "misconfigure" the pins/functions.
Fixes: 87065ca9b8 ("pinctrl: rockchip: Add pinctrl support for PX30")
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20221017-upstream-px30-cif-clkoutm1-v1-0-4ea1389237f7@theobroma-systems.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use temporary variable for struct device to make code neater.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Use temporary variable for struct device to make code neater.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Previously the cleanup change dropped the bitfield.h from the
pinctrl-lpass-lpi.h, since it's not used there, but forgot to
re-instantiate it in the C-file, where users are located.
Fix this by adding missed bitfield.h to the C-file.
Fixes: aa9430f8a6 ("pinctrl: qcom: Add missing header(s)")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Use str_enable_disable() helper instead of open coding the same.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Define a common COMMUNITY macro and supply a variant to it.
This removes some verbosity in macros.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Define a common COMMUNITY macro and supply a variant to it.
This removes some verbosity in macros.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Define a common COMMUNITY macro and supply a variant to it.
This removes some verbosity in macros.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Define a common COMMUNITY macro and supply a variant to it.
This removes some verbosity in macros.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Define a common COMMUNITY macro and supply a variant to it.
This removes some verbosity in macros.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* Add missing and remove unused headers in the pin control and GPIO drivers
* Revise the pin control and GPIO headers
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmNX5WAACgkQb7wzTHR8
rChXxw//YFAxU6PSp0tdmgN8U31YpgwfurSENF3B/oDXGumNfmf+e80/W/xjY4GR
lQXYv17CqJFVQKPtgFSZoHF2YvwLeLI0GtKsfQYbcIOqBsnfHULtSGay25axAzmC
2RwTAc9KYgrJuZiSKJjMGqa6HaQRRkw4oxLuFcG60ZuDvbGM/rQXEgoNs297r/IJ
2ra8TJpc9eOgiBzPqy5ahIFP3yWbitk2uYjOduIu+1ngD4knvcPypqfEmMvA2r4J
84Tni7ZzqqtdvQVdIGvhHyDmlgsCaCULQmGz9O/d5k5zmCpR8+UiXO8lto5UGq5T
xY3kyUomFcumVB7VIPjhjIYNHvUIdOB/N0UfFOL0EieULIVRcfqrVSBJZD93Cg+s
YolpMgUDfs99mjyAWhoMi2HgzesKfBYWlUMCgNsK/X0J3u4P/XUA22xdp70A8D5q
E4IYllUGjDxRKfA30XqkFzis+NWaHF0gj5+piIe3RY5OqRfPGnj1H5VgNu5QjFES
kGC3g2+Wu8vfqXl/IEqNntkbnjUDzl+wL7jBNJbtep4440m91tFCmjj5wl8vHHS6
B6/rfx3d/I8aO3kroZz8Pg1KEgjUl0cmTsL+XgOCePaWOKCDmTQeS7h3UhbPRVyd
udig2At3TfO+0w00jYabH2n+VIaIo4gdbQUc9q4NICn/9vuIZ9c=
=gj0F
-----END PGP SIGNATURE-----
Merge tag 'intel-pinctrl-v6.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.1-2
* Add missing and remove unused headers in the pin control and GPIO drivers
* Revise the pin control and GPIO headers
There is a few things done:
- include only the headers we are direct user of
- when pointer is in use, provide a forward declaration
- add missing headers
- group generic headers and subsystem headers
- sort each group alphabetically
While at it, fix some awkward indentations.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
