Various cleanups and enhancements are made to core Tegra code towards the
aim of including Tegra in a multi-platform ARM kernel:
RTC, timer, and TWD are configured via device tree.
SPARSE_IRQ is enabled.
Tegra's debug_ll options are simplified, and the macros brought into
line with other multi-platform implementations, and moved to the new
common location.
Two headers still need to be eliminated in order to include Tegra in a
multi-platform kernel/ <mach/{clk,powergate}.h>. A new common API needs
to be invented to replace parts of clk.h. powergate.h might be replaced
by regulators; this needs more investigation.
This pull request is based on tegra-for-3.8-dt, followed by a merge of
arm-soc's devel/debug_ll_init branch.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQppQBAAoJEMzrak5tbycxoz0P/REooomHVeI5CNyKMxp0rzQv
dSGfnWD2nuRJ3k36VOdGpa+BYW/xjYuYdIAKNrfAEnfeQRbYp1VGIfyjgMEcx7Yi
TzNmangYj+9f60u1MQq2YQytFFtgfcG1utTIuvKKhuJ/pZEjCkYKBQjNOLFuetaI
oCxNDklcnCn5zxUGsQwpxxMf+A1Ja6tPHkqdN2p+0OQpUpr0i2mCMMrSPEHY0RgV
zRBhsIwwe9eTAOPkZmr6SnCVIAs2rANVnBfZGJC/k9bT7cckhmL/EcGZLBIvRe8L
gD4HtZsltNwbCh/cV4qIvx/nUaW1No/iqvQERtgAGWQtCUp/Jgmy3roV4zzWBiOR
/N88kBaO5fw7crVFDMLTlHVKc2IKWTzSnpEUIllLw/G8ySjW5tjXP57gaxb712BU
KYmcl6KFZ8Uu8OfyDYR6dRPtk+ayqAhSqBql+NveOWLk+nYFFyoob62FPTFq64eu
MwM1BKlFKxLmMUeBTpSJXG/rtVkE+kgocZrB6GEofhIn7gjELqsaWutOJ6LYQ4wY
i4N0NcBA3/oFu7N9T7yY+mKJCwRovyrpqW3Lp62xvns8+Y2ziUNxY4e0NvopzIOi
GYz+ktI3CT1cZv9zkdEI+TOnRrWze8N7Xzt9ii8SD456to5wcaRCjmpATnNIKTTi
uLmNaB6M9+mTjIXR8MDb
=qXVf
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.8-single-zimage' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatform
From Stephen Warren:
ARM: tegra: single-zImage preparation work
Various cleanups and enhancements are made to core Tegra code towards the
aim of including Tegra in a multi-platform ARM kernel:
RTC, timer, and TWD are configured via device tree.
SPARSE_IRQ is enabled.
Tegra's debug_ll options are simplified, and the macros brought into
line with other multi-platform implementations, and moved to the new
common location.
Two headers still need to be eliminated in order to include Tegra in a
multi-platform kernel/ <mach/{clk,powergate}.h>. A new common API needs
to be invented to replace parts of clk.h. powergate.h might be replaced
by regulators; this needs more investigation.
This pull request is based on tegra-for-3.8-dt, followed by a merge of
arm-soc's devel/debug_ll_init branch.
* tag 'tegra-for-3.8-single-zimage' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (58 commits)
ARM: tegra: move debug-macro.S to include/debug
ARM: tegra: don't include iomap.h from debug-macro.S
ARM: tegra: decouple uncompress.h and debug-macro.S
ARM: tegra: simplify DEBUG_LL UART selection options
ARM: tegra: select SPARSE_IRQ
ARM: tegra: enhance timer.c to get IO address from device tree
ARM: tegra: enhance timer.c to get IRQ info from device tree
ARM: timer: fix checkpatch warnings
ARM: tegra: add TWD to device tree
ARM: tegra: define DT bindings for and instantiate RTC
ARM: tegra: define DT bindings for and instantiate timer
ARM: tegra: whistler: enable HDMI port
ARM: tegra: tec: Enable HDMI output
ARM: tegra: plutux: Enable HDMI output
ARM: tegra: tamonten: Add host1x support
ARM: tegra: trimslice: enable HDMI port
ARM: tegra: harmony: enable HDMI port
ARM: tegra: Add Tegra30 host1x support
ARM: tegra: Add Tegra20 host1x support
ARM: tegra: trimslice: enable SPI flash
...
Move Tegra's debug-macro.S over to the common debug macro directory.
Move Tegra's debug UART selection menu into ARM's Kconfig.debug, so that
all related options are selected in the same place.
Tegra's uncompress.h is left in mach-tegra/include/mach; it will be
removed whenever Tegra is converted to multi-platform.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
In order to move Tegra's debug-macro.S to a common location for single
zImage, it must not rely on any machine-specific header files such as
<mach/iomap.h>. Duplicate the few physical address definitions that
debug-macro.S relies upon directly into the file.
To avoid tegra_io_desc[] requiring shared knowledge of the UART
mapping's virtual address, use a virtual address outside the ranges
in tegra_io_desc[]. Call debug_ll_io_init() to propagate the mapping
beyond the early pages tables.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prior to this change, Tegra's debug-macro.S relied on uncompress.h having
determined which UART to use, and whether it was safe to use the UART
(i.e. is it not in reset, and is clocked). This determination was
communicated from uncompress.h to debug-macro.S using a few bytes of
Tegra's IRAM (an on-SoC RAM). This had the disadvantage that uncompress.h
was a required part of the kernel boot process; booting a non-compressed
kernel would not allow earlyprintk to operate.
This change duplicates the UART selection and validation logic into
debug-macro.S so that the reliance on uncompress.h is removed.
This also helps out with single-zImage work, since there is currently no
support for using any uncompress.h with single-zImage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Delete CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH; it's not useful any more:
* No upstream bootloader currently or will ever support this option.
* CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA is a much more direct alternative.
Merge the fixed and automatic UART selection menus into a single choice
for simplicity; now you either pick AUTO_ODMDATA or a single fixed UART,
rather than potentially having an AUTO option override whatever fixed
option was chosen.
Remove TEGRA_DEBUG_UART_NONE; if you don't want a Tegra DEBUG_LL UART,
simply don't turn on DEBUG_LL. NONE used to be the default option, so
pick AUTO_ODMDATA as the new default.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
SPARSE_IRQ is required for single zImage support.
With this enabled, we can delete <mach/irqs.h>. This requires removing
one unnecessary include of that file, and hard-coding the PCIe IRQ into
the PCIe driver. This is a hack that will be dealt with as part of
converting the PCIe driver into a true DT-supporting driver.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Modify Tegra's timer code to parse the IO address from device tree,
hence removing the dependency on <mach/iomap.h>. This will allow the
driver to be moved to drivers/clocksource/.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Modify Tegra's timer code to parse the Tegra timer IRQ from device tree,
and to instantiate the TWD from device tree, rather than relying on hard-
coded values from <mach/irqs.h>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This will allow timer.c to use twd_local_timer_of_register(), and
hence not need to hard-code the TWD address or IRQ.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Tegra RTC maintains seconds and milliseconds counters, and five alarm
registers. The alarms and other interrupts may wake the system from
low-power state.
Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Tegra timer provides a number of 29-bit timer channels, a single
32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules.
The first two channels may also trigger a legacy watchdog reset.
Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable host1x, and the HDMI output. Whistler also has a DSI-based LCD,
and a VGA output. tegradrm doesn't support either of those output types
yet.
Based on work by Thierry Reding for TrimSlice.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable the HDMI output found on Tamonten Evaluation Carrier boards.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable the HDMI output found on Plutux boards.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Hook up the required regulators, I2C DDC adapter and hotplug detect GPIO
to the Tamonten HDMI output. Carrier boards still need to explicitly
enable the output to use it.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable host1x, and the HDMI output. Harmony also has a DVI port with an
HDMI form-factor connector, driven by Tegra's LVDS output. This isn't
enabled yet, due to potential issues with having multiple outputs enabled.
Correct DDC I2C frequency to 100KHz.
Add dummy/fixed regulators to satisfy the HDMI driver.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
[swarren: add commit description, remove enable of DVI port]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable host1x, and the HDMI output. Harmony also has an optional LCD,
and a VGA output. The former isn't enabled due to potential issues with
having multiple outputs enabled. The latter isn't enabled since the
driver doesn't support VGA yet anyway.
Correct DDC I2C frequency to 100KHz.
Based on work by Thierry Reding for TrimSlice.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the host1x node along with its children to the Tegra30 DTSI. Board-
specific DTS files are expected to enable the available outputs and
complement the device tree with data specific to the hardware.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the host1x node along with its children to the Tegra20 DTSI. Board-
specific DTS files are expected to enable the available outputs and
complement the device tree with data specific to the hardware.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Nvidia's Tegra20 have the SPI (SFLASH) controller to
interface with spi flash device which is used for system
boot. Add DT entry for this controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: move sflash node to keep file sorted]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Harmony board has an ON Semiconductors NCT1008 temperature sensor
connected to the DVC bus. It can be used to monitor the ambient (local)
and on-die (remote) temperatures.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Tamonten SOM has an ON Semiconductor NCT1008 connected to the DVC
bus which is used to measure the ambient (local) temperature as well as
the on-die (remote) temperature.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Harmony board has an Analog Devices ADT7461 temperature sensor
connected to the DVC bus. It can be used to monitor the ambient (local)
and on-die (remote) temperatures.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
These properties are already set by the tegra20-tamonten.dtsi, so they
don't need to be repeated.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit allows the I2C2 controller on Tegra20 to be routed either to
the DDC or the PTA pin group at runtime. On Tamonten this allows the I2C
bus to be used for the DDC of the HDMI connector or to access I2C chips
on the carrier board.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable SLINK4 and connected device in Tegra30 based
platform Cardhu.
Setting maximum spi frequency to 25MHz.
SPI serial flash is connected on CS1 of SLINK4 on
cardhu platform.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: swapped reg/compatible order to be consistent]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add slink controller details in the dts file of
Tegra20 and Tegra30.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra 2's I2C2 controller can be routed to either the PTA
or DDC pin group on Ventana. So:
- Remove the HDMI function definition of pta pingroup
- Define child i2c adapters(ddc & pta) for I2C2 controller
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Configure pinmux as required for WiFi.
Enable the SDHCI1 controller for a02 and a04 board, which is connected to the
WiFi module.
For now, always enable the regulator that provides power to the Wifi module.
Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Configure pinmux as required for WiFi.
Enable the SDHCI1 controller, which is connectted to the WiFi module.
Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable the SDHCI1 controller. This is connected to the WiFi module.
Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Setup the clock parents for the two display controllers and HDMI.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the OF_DEV_AUXDATA table entries required to associate the proper
names with host1x and its children. In turn, this allows the devices to
find the required clocks.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Extend the pll_d frequency table with a few entries to support common
HDMI and LVDS display modes and setup the clock parents for the two
display controllers and HDMI.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the OF_DEV_AUXDATA table entries required to associate the proper
names with host1x and its children. In turn, this allows the devices to
find the required clocks.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds speedo-based process identification support for Tegra30.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
[swarren s/Tegra3/Tegra30/ in log print,
s/T30/Tegra30/ in commit description]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Detect CPU and core process ID by checking speedo corner tables.
This can provide a more accurate process ID.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
[swarren s/Tegra2/Tegra20/ in log print]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Change the spare fuse base from a definition to a variable.
It provides flexibilty to read spare fuse on different chip.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch implements ARM linux patch 6395/1 for Tegra. See commit
1a8e41c "ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache
controller) AuxCtlr register" for details.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
[swarren: added commit subject for referenced patch]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add OF_DEV_AUXDATA for sflash controller driver for Tegra20
board dt files.
Set the parent clock of sflash controller to PLLP and configure
clock to 20MHz.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable the data prefetch on L2. The bit28 in aux ctrl register.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
- Move all remaining headers out of arch/arm/plat-nomadik/include/plat
out to e.g. include/linux/platform_data
- Delete arch/arm/plat-nomadik
- Convert Nomadik and Ux500 to SPARSE_IRQ
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJQl4K6AAoJEEEQszewGV1zww0P/3YnFr91bhuwHsqhz3+W31Mi
RFXk74d7G7vyNZ8817zl0YcR22tByaIldnoj0sasqttqOChE0WbJBl86aDpoeKYo
dbZL3d8ZndE0mXomyV6nd0d5H7Q2/NBlQwCTEr4KvGlcSHIQ4MEW8aZx64m63ReP
YytAPNU36GrUBVPgtDNj8QwCTW84HEvwTte/W5t8iUPt40aeWL4BrYg19sIFtz9r
FhaXUkZBZSfsXg7ZDtkAd2mMpqJusIX0UQi5q0nyhClnz5+PGKHlN1/rMo56diQC
ZpIo1Dp4RhUj2MYVtvNrMNZE5dZxdrPbpswd/ExEQdzFxinUiopzz4VoMLjwbHME
c324I23kke/bDrOSQQvwUqRQ0p1xm2NFipPzs7LkqggxnLXBhDKkQoih6GeEmo4/
6Dq7XFN7DX6PwaambLEsvwolm52mvxN5N9R8bc3VBt9Z07Xt+nM994E55PcwHsD1
KaO+8R3efhUCTFq/r/on+QiEz6++kFZqLDeFlbsrPsUZDn0kZ0VPsKpEXKFwEJWk
bTk+vDo5OefSZ1d421Rpu73L6WkzhPQC9sIGSdDrw8uEOlgEQggVnI8VkATkz2Em
gn2aC1tCwtyhmTbzNhL8VLB4h1q7lvRX2mR8Z9Q9F0bL9IbyWGJ+hsuDjNZstjk4
FFXyRSClx3stmuSuPcGT
=LEWy
-----END PGP SIGNATURE-----
Merge tag 'kill-plat-sparse-irq' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next/multiplatform
From Linus Walleij:
This patchset will:
- Move all remaining headers out of arch/arm/plat-nomadik/include/plat
out to e.g. include/linux/platform_data
- Delete arch/arm/plat-nomadik
- Convert Nomadik and Ux500 to SPARSE_IRQ
* tag 'kill-plat-sparse-irq' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
ARM: plat-nomadik: convert platforms to SPARSE_IRQ
mfd/db8500-prcmu: use the irq_domain_add_simple()
mfd/ab8500-core: use irq_domain_add_simple()
ARM: plat-nomadik: move MTU, kill plat-nomadik
ARM: plat-nomadik: move DMA40 header to <linux/platform_data>
ARM: plat-nomadik: use DIV_ROUND_CLOSEST()
ARM: plat-nomadik: pass IRQ to timer driver
clk/ux500: explicitly include register header
pinctrl/nomadik: merge old pincfg header
pinctrl/nomadik: move the platform data header
ARM: plat-nomadik: move NMK_GPIO_PER_CHIP into gpio-nomadik.h
ARM: plat-nomadik: Introduce new DB8540 GPIO registers
Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30
board dt files.
Set the parent clock of slink controller to PLLP and configure
clock to 100MHz.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
