Commit Graph

1204 Commits

Author SHA1 Message Date
Chew, Kean Ho
42bd00706c pinctrl-baytrail: add function mux checking in gpio pin request
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup pin, I/O interfaces for LPSS, etc.

Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Darren Hart <dvhart@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-11 11:22:54 +01:00
Stephen Warren
a76cbd7eba pinctrl: tegra: fix some typos and inconsistencies
drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it.

pinctrl-tegra124.c had quite a few typos. Fix those.

pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys
and the function lists in tegra124_groups[]. Fix those.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-11 11:16:28 +01:00
Geert Uytterhoeven
e6fae2d03d pinctrl: sh-pfc: r8a7791: Add alternative MSIOF pin groups
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:53:49 +08:00
Geert Uytterhoeven
7033168da5 pinctrl: sh-pfc: r8a7790: Add alternative MSIOF pin groups
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:15:30 +08:00
Linus Walleij
a9ea2ed45a Merge branch 'pinctrl-mvebu' into devel 2014-03-03 13:40:22 +08:00
Jason Cooper
7cab36e5ee Sign for-mvebu/pinctrl-3xx
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Merge tag 'tags/for-mvebu-pinctrl-3xx' into mvebu/pinctrl

Sign for-mvebu/pinctrl-3xx
2014-03-01 07:03:52 +00:00
Sebastian Hesselbarth
6da67cab4b pinctrl: mvebu: dove: use global register regmap
Now that we have a regmap for global registers, get rid of the last
remaining hardcoded physical addresses. While at it, also remove
DOVE_ prefix from those macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:18 +01:00
Sebastian Hesselbarth
18e6f28e9c pinctrl: mvebu: dove: use remapped pmu_mpp registers
Now that we have ioremapped pmu_mpp registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:16 +01:00
Sebastian Hesselbarth
2c4b229baf pinctrl: mvebu: dove: use remapped mpp4 register
Now that we have an ioremapped mpp4 register, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:14 +01:00
Sebastian Hesselbarth
00202b013e pinctrl: mvebu: dove: use remapped mpp base registers
Now that we have ioremapped mpp base registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:12 +01:00
Sebastian Hesselbarth
e91f7916ea pinctrl: mvebu: dove: request syscon regmap for global registers
Dove pinctrl uses some global config registers to control pins.
This patch requests a syscon regmap for those registers. As this
changes DT to driver requirements, fallback to a self-registered
regmap with hardcoded resources, if the corresponding syscon DT
node is missing. Also, WARN about old DT binding usage to encourage
users to update their DTBs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:09 +01:00
Sebastian Hesselbarth
4d73fc7728 pinctrl: mvebu: dove: request additional resources
Dove pinctrl also requires additional registers to control all pins.
This patch requests resources for mpp4 and pmu-mpp register ranges.
As this changes DT to driver requirements, fallback to hardcoded
resources, if the corresponding DT regs have not been set.
Also, WARN about old DT binding usage to encourage users to update
their DTBs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:08 +01:00
Thomas Petazzoni
ca6d9a084b pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385
The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:51:05 +01:00
Thomas Petazzoni
ce3ed59dcd pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375
The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2014-02-25 18:51:01 +01:00
Sebastian Hesselbarth
78c2c3d3da pinctrl: mvebu: dove: reuse mpp_{set,get} in pmu callbacks
Dove has pins that can be switched between normal and pmu functions.
Rework pmu_mpp callbacks to reuse default mpp ctrl helpers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:38:41 +01:00
Sebastian Hesselbarth
c2f082fe97 pinctrl: mvebu: dove: consolidate auto-numbered pmu mpp ranges
Passing a NULL name for pin ranges will auto-generate standard names
for each pin. With common pinctrl driver now checking NULL name correctly,
consolidate mpp pins 0-15.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:38:37 +01:00
Thomas Petazzoni
cffa7a6b10 pinctrl: mvebu: remove MPP_REG_CTRL macro
Now that each per-SoC pinctrl driver must implement its own get/set
functions, there is no point in keeping the MPP_REG_CTRL macro, whose
purpose was to let the core pinctrl mvebu driver use default get/set
functions. While at it also update the comment about mvebu_mpp_ctrl.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:38:31 +01:00
Sebastian Hesselbarth
faaa8325ad pinctrl: mvebu: remove common get/set functions
With every SoC always providing its own get/set callbacks, we can now
remove the generic ones, remove the obsolete base address, and always
use the provided callbacks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:38:24 +01:00
Sebastian Hesselbarth
1217b790ae pinctrl: mvebu: move resource allocation to SoC specific drivers
The way that mvebu pinctrl is designed, requesting mpp registers
in common pinctrl driver does not allow SoC specific drivers to
access this resource.

Move resource allocation in each SoC pinctrl driver and enable
already provided mpp_{set,get} callbacks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:37:53 +01:00
Sebastian Hesselbarth
ad2a4f2b80 pinctrl: mvebu: armada-xp: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:35:41 +01:00
Sebastian Hesselbarth
877f01fc4d pinctrl: mvebu: armada-370: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:35:35 +01:00
Sebastian Hesselbarth
3a25f9f2f7 pinctrl: mvebu: kirkwood: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
2014-02-25 18:35:30 +01:00
Sebastian Hesselbarth
17bdec6770 pinctrl: mvebu: dove: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later. While at it, also make use of globally defined
MPP macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:35:24 +01:00
Sebastian Hesselbarth
f5b85e42d4 pinctrl: mvebu: add common mpp reg helper to mvebu pinctrl include
This adds some defines and helper functions for the common mpp reg
layout to mvebu pinctrl include.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
2014-02-25 18:35:16 +01:00
Sebastian Hesselbarth
2035d39da1 pinctrl: mvebu: remove passing mvebu_mpp_ctrl to callbacks
The only valuable information a special callback can derive from
mvebu_mpp_ctrl passed to it, is the pin id. Instead of passing
the struct, pass the pid directly.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:51 +01:00
Sebastian Hesselbarth
e310b74544 pinctrl: mvebu: identify generic controls by name
We treat unnamed controls as generic mvebu mpp register controls but
we identify them by not being special controls. Flip the logic and
use the name pointer as identification instead. While at it, add some
comments explaining the not so obvious treatment.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:45 +01:00
Sebastian Hesselbarth
dc2a90004e pinctrl: mvebu: remove obsolete per-control name buffer allocation
With the introduction of a global name buffer, we can now remove
the allocation and preparation of per-control name buffers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:41 +01:00
Sebastian Hesselbarth
8d898fd596 pinctrl: mvebu: count unnamed controls and allocate name buffer
pinctrl-mvebu allows SoCs to pass unnamed controls that will get an
auto-generated name of "mpp<PIN#>". Currently, we are allocating name
buffers on a per-control basis while looping over passed controls.
This counts the total number of unnamed controls and allocates a
global name buffer instead. The new buffer is then used while assigning
controls to pinctrl groups later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:34 +01:00
Wolfram Sang
6787141361 pinctrl: pfc: r8a7791: add mux data for IIC(B) cores
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:15 +01:00
Richard Genoud
8af584b868 pinctrl: at91: implement get_direction
This is needed for gpiod_get_direction().
Otherwise, it returns -EINVAL.

Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:15 +01:00
Martin Fuzzey
7c001e556e pinctrl: imx: Fix pin name in debug message.
The wrong index counter was being used, causing the debug message
to show an incorrect pin name.

Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:14 +01:00
Hans de Goede
885d662618 pinctrl-sunxi: Fix sun5i-a13 port F multiplexing
The correct value for selecting the mmc0 function on port F pins is 2 not 4,
as per the data-sheet:
http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:14 +01:00
Sonic Zhang
e3653749aa pinctrl: pinctrl-adi: combine multiple groups of one function together
The data pins of some peripheral are different if connecting to different
devices in one pinmux function. In the PPI case, data pins can be used
in 8, 16 and 24 pin groups individually. Add these groups into one ppi
function.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:13 +01:00
Barry Song
019c12f474 pinctrl: sirf: update copyright years to 2014
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:13 +01:00
Ulf Hansson
c003eed7a0 pinctrl: nomadik: Convert to modern pm_ops
Use the SIMPLE_DEV_PM_OPS macro and convert to the modern pm ops.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:12 +01:00
Ulf Hansson
131d85bc3a pinctrl: nomadik: Silence compiler warn for !CONFIG_PM
The static suspend/resume functions were not being used while
!CONFIG_PM. Fix it and convert to CONFIG_PM_SLEEP.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:12 +01:00
Geert Uytterhoeven
202909cdf1 pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:11 +01:00
Ivan T. Ivanov
dc1791188b pinctrl-msm: Add SPI8 pin definitions
Add pin, group and function definitions for SPI#8
controller.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:11 +01:00
Mark Brown
5d88dceac7 pinctrl: Quiet logging about missing DT nodes when not using DT
On systems which were not booted using DT it is entirely unsurprising that
device nodes don't have any DT information and this is going to happen for
every single device in the system. Make pinctrl be less chatty about this
situation by only logging in the case where we have DT.

Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-24 10:44:54 +01:00
Magnus Damm
97e00faaf1 pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUS
Create a new group for the USB0 OVC/VBUS pin by itself. This
allows us to monitor PWEN as GPIO on the Lager board.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11 09:35:19 +01:00
Young-Gun Jang
9a8b607972 pinctrl: exynos: add exynos5260 SoC specific data
Adds pinctrl support for all platforms based on EXYNOS5260 SoC.

Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11 09:35:19 +01:00
Bjorn Andersson
ed118a5fd9 pinctrl-msm: Support output-{high,low} configuration
Add support for configuring pins as output with value as from the
pinconf-generic interface.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11 09:35:18 +01:00
Rongjun Ying
58ffe7a025 pinctrl: sirf: add pin group for USP0 for atlas6
USP0 has multiple functions, and has RX and TX frame sync signals,
for some scenarios like audio PCM, we don't need both of them.
so here we add two possibilities for USP0 only holding one of TX
and RX frame sync.

commit 8385af02ba only added this group for prima2, and missed
atlas6. This patch fixes it.

Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Chao Xie
4bd7547756 pinctrl: single: add low power mode support
For some silicons, the pin configuration register can control
the output of the pin when the pad including the pin enter
low power mode.
For example, the pin can be "Drive 1", "Drive 0", "Float" when
the pad including the pin enter low power mode.
It is very useful when you want to control the power leakeage
when the SOC enter low power mode, and can save more power for
the low power mode.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Sonic Zhang
b81e57e6ac pinctrl-adi2: fix coding style issue
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Sonic Zhang
b4eef7b225 pinctrl-adi2: change irq_base from usigned int to int
Negative irq_base means this gpio port doens't support interrupts.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Sonic Zhang
1e6f8e3c92 pinctrl: Move pint PM storage structure out of blackfin architecture.
It is better to keep this structure in the pinctrl-adi2 driver.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Jean-Jacques Hiblot
94e692071a pinctrl: at91: use gpiolib API to mark a GPIO used as an IRQ
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Geert Uytterhoeven
2d0c386f13 pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-02-10 10:13:07 +01:00
Srinivas Kandagatla
155795b9d1 pinctrl: st: Add software edge trigger interrupt support
ST pin controller does not have hardware support for detecting edge
triggered interrupts, It only has level triggering support.
This patch attempts to fake up edge triggers from hw level trigger
support in software. With this facility now the gpios can be easily used
for keypads, otherwise it would be difficult for drivers like keypads to
work with level trigger interrupts.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:07 +01:00