The fsafe value in the pingroup data tables is only used to implement
tegra_pinctrl_disable(). The only reason this function is called is when
dynamically switching between pinmux states, i.e. when disabling the old
state before programming the new state. It's simpler to have the new
target state define the expected value of each pin (and all current DTs
do that). This also gives more flexibility, since it allows individual
boards explicit control over the "inactive" mux function for each pin,
rather than requiring it to be an SoC-specific value. Assuming this, we
can get rid of the fsafe value from the driver completely, thus saving
some more space in the driver tables.
While re-writing the content of tegra124_pingroups[], fix the indentation
to use a TAB instead of spaces.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel
options has the relevant HW register fields in the same register as the
mux function selection. Similarly, the drvtype option is always in the
drive register, if it is supported at all. Hence, we don't need to have
struct *_reg fields in the pin group table to define which register and
bank to use for those options. Delete this to save space in the driver's
data tables.
However, many of those options are not supported on all SoCs, or not
supported on some pingroups. We need a way to detect when they are
supported. Previously, this was indicated by setting the struct *_reg
field to -1. With the struct *_reg fields removed, we use the struct
*_bit fields for this purpose instead. The struct *_bit fields need to
be expanded from 5 to 6 bits in order to store a value outside the valid
HW bit range of 0..31.
Even without removing the struct *_reg fields, we still need to add code
to validate the struct *_bit fields, since some struct *_bit fields were
already being set to -1, without an option-specific struct *_reg field to
"guard" them. In other words, before this change, the pinmux driver might
allow some unsupported options to be written to HW.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix Tegra30/114/124 pinmux drivers consistency issues.
* Sort all lists of the same object type (e.g. #defines for pins, and
the array that defines their names) in the same order.
* Whitespace fixes.
* Consistency in layout between the 3 drivers.
These driver files were also auto-generated, which should allow us to
make e.g. the U-Boot drivers completely consistent with the kernel in
the future:-)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The per-SoC data structures for Tegra pinctrl stored some information
in a redundant way. Specifically, the list of groups that each function
could be muxed onto was stored once explicitly, and also as part of the
definition of each group. Eliminate this redundancy, and calculate each
function's list of valid groups at pinctrl probe time. This removes
thousands of lines of code from the pinctrl driver and ~16K from the
vmlinux binary size, and adds only about 500uS to the boot process (on
Tegra30; newer SoCs will likely be faster still).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Tegra20/30 pinctrl drivers currently initializes at arch_initcall,
whereas Tegra114/124 pinctrl drivers initialize at module_init time.
Convert Tegra20/30 to work the same way as the other drivers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.
rcv-sel: Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH
RCVR_SEL=0: Normal VIL/VIH
drv_type: Ouptput drive type:
33-50 ohm driver: 0x1
66-100ohm driver: 0x0
Add support of these parameters to be configure from DTS file.
Tegra20 and Tegra30 does not support this configuration and hence initialize their
pinmux structure with reg = -1.
Originally written by Pritesh Raithatha.
Changes by ldewangan:
- remove drvtype_width as it is always 2.
- Better describe the change.
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
markings need to be removed.
This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.
Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.
Cc: Bill Pemberton <wfp5p@virginia.edu>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Barry Song <baohua.song@csr.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CONFIG_HOTPLUG is going away as an option so __devinitdata is no
longer needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer
needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Rather than having a single tegra-pinctrl driver that determines whether
it's running on Tegra20 or Tegra30, instead have separate drivers for
each that call into utility functions to implement the majority of the
driver. This change is based on review feedback of the SPEAr pinctrl
driver, which had originally copied to Tegra driver structure.
This requires that the two drivers have unique names. Update a couple
spots in arch/arm/mach-tegra for the name change.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This adds a driver for the Tegra pinmux, and required parameterization
data for Tegra20 and Tegra30.
The driver is initially added with driver name and device tree compatible
value that won't cause this driver to be used. A later change will switch
the pinctrl driver to use the correct values, switch the old pinmux
driver to be disabled, and update all code that uses the old pinmux APIs
to use the new pinctrl APIs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
[squashed "fix case of Tegra30's foo_groups[] arrays"]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
