If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/83540eb3ae76a0d28bbe03d69d685a6d549b456b.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/ed5020e5b008b28c33a90c9c1670cef2393d3b7e.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/f30264b137b1282ffda34d336e8060bb13d60b98.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/335014f2b44cdf24ed1e37cb7c88f6c5de896cc2.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/f87e22bc09a471d2cf15ad05dfd6432f57739aed.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/7da7ea760abc5f85cad6e9b0d3e59eebd93f50d3.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/765c2f27d85fcee4eb137023dc0a8f864eee9e36.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/666127469482f9ca177805ff52aeb7bccb26e4c9.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/b95defa3db834789a4207df5d6b0216c8b610524.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If config pci_ops.read() methods return failure, the PCI_OP_READ() and
PCI_USER_READ_CONFIG() wrappers use PCI_SET_ERROR_RESPONSE() to set the
data value, so there's no need to set it in the pci_ops.read() methods
themselves.
Drop the unnecessary data value fabrication when pci_ops.read() fails.
Link: https://lore.kernel.org/r/22f471b638276422926c49f3d42ac41bc7b28b3d.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
BMIPS_GENERIC denotes support for the MIPS-based Broadcom STB platforms
which this driver can support.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Merge tag 'pci-v5.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Conserve IRQs by setting up portdrv IRQs only when there are users
(Jan Kiszka)
- Rework and simplify _OSC negotiation for control of PCIe features
(Joerg Roedel)
- Remove struct pci_dev.driver pointer since it's redundant with the
struct device.driver pointer (Uwe Kleine-König)
Resource management:
- Coalesce contiguous host bridge apertures from _CRS to accommodate
BARs that cover more than one aperture (Kai-Heng Feng)
Sysfs:
- Check CAP_SYS_ADMIN before parsing user input (Krzysztof
Wilczyński)
- Return -EINVAL consistently from "store" functions (Krzysztof
Wilczyński)
- Use sysfs_emit() in endpoint "show" functions to avoid buffer
overruns (Kunihiko Hayashi)
PCIe native device hotplug:
- Ignore Link Down/Up caused by resets during error recovery so
endpoint drivers can remain bound to the device (Lukas Wunner)
Virtualization:
- Avoid bus resets on Atheros QCA6174, where they hang the device
(Ingmar Klein)
- Work around Pericom PI7C9X2G switch packet drop erratum by using
store and forward mode instead of cut-through (Nathan Rossi)
- Avoid trying to enable AtomicOps on VFs; the PF setting applies to
all VFs (Selvin Xavier)
MSI:
- Document that /sys/bus/pci/devices/.../irq contains the legacy INTx
interrupt or the IRQ of the first MSI (not MSI-X) vector (Barry
Song)
VPD:
- Add pci_read_vpd_any() and pci_write_vpd_any() to access anywhere
in the possible VPD space; use these to simplify the cxgb3 driver
(Heiner Kallweit)
Peer-to-peer DMA:
- Add (not subtract) the bus offset when calculating DMA address
(Wang Lu)
ASPM:
- Re-enable LTR at Downstream Ports so they don't report Unsupported
Requests when reset or hot-added devices send LTR messages
(Mingchuang Qiao)
Apple PCIe controller driver:
- Add driver for Apple M1 PCIe controller (Alyssa Rosenzweig, Marc
Zyngier)
Cadence PCIe controller driver:
- Return success when probe succeeds instead of falling into error
path (Li Chen)
HiSilicon Kirin PCIe controller driver:
- Reorganize PHY logic and add support for external PHY drivers
(Mauro Carvalho Chehab)
- Support PERST# GPIOs for HiKey970 external PEX 8606 bridge (Mauro
Carvalho Chehab)
- Add Kirin 970 support (Mauro Carvalho Chehab)
- Make driver removable (Mauro Carvalho Chehab)
Intel VMD host bridge driver:
- If IOMMU supports interrupt remapping, leave VMD MSI-X remapping
enabled (Adrian Huang)
- Number each controller so we can tell them apart in
/proc/interrupts (Chunguang Xu)
- Avoid building on UML because VMD depends on x86 bare metal APIs
(Johannes Berg)
Marvell Aardvark PCIe controller driver:
- Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár)
- Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár)
- Downgrade PIO Response Status messages to debug level (Marek Behún)
- Preserve CRS SV (Config Request Retry Software Visibility) bit in
emulated Root Control register (Pali Rohár)
- Fix issue in configuring reference clock (Pali Rohár)
- Don't clear status bits for masked interrupts (Pali Rohár)
- Don't mask unused interrupts (Pali Rohár)
- Avoid code repetition in advk_pcie_rd_conf() (Marek Behún)
- Retry config accesses on CRS response (Pali Rohár)
- Simplify emulated Root Capabilities initialization (Pali Rohár)
- Fix several link training issues (Pali Rohár)
- Fix link-up checking via LTSSM (Pali Rohár)
- Fix reporting of Data Link Layer Link Active (Pali Rohár)
- Fix emulation of W1C bits (Marek Behún)
- Fix MSI domain .alloc() method to return zero on success (Marek
Behún)
- Read entire 16-bit MSI vector in MSI handler, not just low 8 bits
(Marek Behún)
- Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits
at startup; PCI core will set those as necessary (Pali Rohár)
- When operating as a Root Port, set class code to "PCI Bridge"
instead of the default "Mass Storage Controller" (Pali Rohár)
- Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't
implement this per spec (Pali Rohár)
- Add emulation of option ROM BAR since aardvark doesn't implement
this per spec (Pali Rohár)
MediaTek MT7621 PCIe controller driver:
- Add MediaTek MT7621 PCIe host controller driver and DT binding
(Sergio Paracuellos)
Qualcomm PCIe controller driver:
- Add SC8180x compatible string (Bjorn Andersson)
- Add endpoint controller driver and DT binding (Manivannan
Sadhasivam)
- Restructure to use of_device_get_match_data() (Prasad Malisetty)
- Add SC7280-specific pcie_1_pipe_clk_src handling (Prasad Malisetty)
Renesas R-Car PCIe controller driver:
- Remove unnecessary includes (Geert Uytterhoeven)
Rockchip DesignWare PCIe controller driver:
- Add DT binding (Simon Xue)
Socionext UniPhier Pro5 controller driver:
- Serialize INTx masking/unmasking (Kunihiko Hayashi)
Synopsys DesignWare PCIe controller driver:
- Run dwc .host_init() method before registering MSI interrupt
handler so we can deal with pending interrupts left by bootloader
(Bjorn Andersson)
- Clean up Kconfig dependencies (Andy Shevchenko)
- Export symbols to allow more modular drivers (Luca Ceresoli)
TI DRA7xx PCIe controller driver:
- Allow host and endpoint drivers to be modules (Luca Ceresoli)
- Enable external clock if present (Luca Ceresoli)
TI J721E PCIe driver:
- Disable PHY when probe fails after initializing it (Christophe
JAILLET)
MicroSemi Switchtec management driver:
- Return error to application when command execution fails because an
out-of-band reset has cleared the device BARs, Memory Space Enable,
etc (Kelvin Cao)
- Fix MRPC error status handling issue (Kelvin Cao)
- Mask out other bits when reading of management VEP instance ID
(Kelvin Cao)
- Return EOPNOTSUPP instead of ENOTSUPP from sysfs show functions
(Kelvin Cao)
- Add check of event support (Logan Gunthorpe)
Miscellaneous:
- Remove unused pci_pool wrappers, which have been replaced by
dma_pool (Cai Huoqing)
- Use 'unsigned int' instead of bare 'unsigned' (Krzysztof
Wilczyński)
- Use kstrtobool() directly, sans strtobool() wrapper (Krzysztof
Wilczyński)
- Fix some sscanf(), sprintf() format mismatches (Krzysztof
Wilczyński)
- Update PCI subsystem information in MAINTAINERS (Krzysztof
Wilczyński)
- Correct some misspellings (Krzysztof Wilczyński)"
* tag 'pci-v5.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (137 commits)
PCI: Add ACS quirk for Pericom PI7C9X2G switches
PCI: apple: Configure RID to SID mapper on device addition
iommu/dart: Exclude MSI doorbell from PCIe device IOVA range
PCI: apple: Implement MSI support
PCI: apple: Add INTx and per-port interrupt support
PCI: kirin: Allow removing the driver
PCI: kirin: De-init the dwc driver
PCI: kirin: Disable clkreq during poweroff sequence
PCI: kirin: Move the power-off code to a common routine
PCI: kirin: Add power_off support for Kirin 960 PHY
PCI: kirin: Allow building it as a module
PCI: kirin: Add MODULE_* macros
PCI: kirin: Add Kirin 970 compatible
PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge
PCI: apple: Set up reference clocks when probing
PCI: apple: Add initial hardware bring-up
PCI: of: Allow matching of an interrupt-map local to a PCI device
of/irq: Allow matching of an interrupt-map local to an interrupt controller
irqdomain: Make of_phandle_args_to_fwspec() generally available
PCI: Do not enable AtomicOps on VFs
...
- Use PCI_VENDOR_ID_AMCC macro instead of defining a custom macro in
pci-xgene.c (Pali Rohár)
* remotes/lorenzo/pci/xgene:
PCI: xgene: Use PCI_VENDOR_ID_AMCC macro
- Assign a number to each VMD controller to distinguish them in
/proc/interrupts (Chunguang Xu)
- Don't disable VMD MSI-X remapping if IOMMU remapping is enabled (Adrian
Huang)
- Add Kconfig dependency on !UML for allyesconfig build issue (Johannes
Berg)
* remotes/lorenzo/pci/vmd:
PCI: vmd: depend on !UML
PCI: vmd: Do not disable MSI-X remapping if interrupt remapping is enabled by IOMMU
PCI: vmd: Assign a number to each VMD controller
- Reorganize to separate out PHY logic (Mauro Carvalho Chehab)
- Add support for external PHY in addition to the internal PHY (Mauro
Carvalho Chehab)
- Use regmap so both kirin driver and PHY can access APB registers (Mauro
Carvalho Chehab)
- Add support for per-lane PERST# GPIOs on HiKey970 external PEX 8606 PCI
bridge (Mauro Carvalho Chehab)
- Add "hisilicon,kirin970-pcie" compatible string (Mauro Carvalho Chehab)
- Add MODULE_* macros (Mauro Carvalho Chehab)
- Allow building as a module (Mauro Carvalho Chehab)
- Add power_off support for Kirin 960 PHY (Mauro Carvalho Chehab)
- Disable clkreq during poweroff sequence (Mauro Carvalho Chehab)
- De-init the dwc driver during remove (Mauro Carvalho Chehab)
- Allow removal of kirin driver (Mauro Carvalho Chehab)
* pci/host/kirin:
PCI: kirin: Allow removing the driver
PCI: kirin: De-init the dwc driver
PCI: kirin: Disable clkreq during poweroff sequence
PCI: kirin: Move the power-off code to a common routine
PCI: kirin: Add power_off support for Kirin 960 PHY
PCI: kirin: Allow building it as a module
PCI: kirin: Add MODULE_* macros
PCI: kirin: Add Kirin 970 compatible
PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge
PCI: kirin: Use regmap for APB registers
PCI: kirin: Add support for a PHY layer
PCI: kirin: Reorganize the PHY logic inside the driver
- Export dw_pcie_ep_reset_bar(), dw_pcie_link_up() so more drivers can be
modular (Luca Ceresoli)
- Allow dra7xx host and endpoint drivers to be modules (Luca Ceresoli)
- Enable dra7xx optional external clock if present (Luca Ceresoli)
- Clean up Kconfig dependencies for PCIE_DW_HOST- and PCIE_DW_EP-based
drivers (Andy Shevchenko)
- Remove visconti redundant dev_err() after platform_get_irq_byname()
failure (Krzysztof Wilczyński)
- Run dwc .host_init() method before registering MSI interrupt handler so
we have a chance to deal with pending interrupts left by bootloader
(Bjorn Andersson)
- Serialize uniphier INTx masking/unmasking (Kunihiko Hayashi)
* pci/host/dwc:
PCI: uniphier: Serialize INTx masking/unmasking and fix the bit operation
PCI: dwc: Perform host_init() before registering msi
PCI: visconti: Remove surplus dev_err() when using platform_get_irq_byname()
PCI: dwc: Clean up Kconfig dependencies (PCIE_DW_EP)
PCI: dwc: Clean up Kconfig dependencies (PCIE_DW_HOST)
PCI: dra7xx: Get an optional clock
PCI: dra7xx: Remove unused include
PCI: dra7xx: Make it a kernel module
PCI: dwc: Export more symbols to allow modular drivers
- Make of_phandle_args_to_fwspec() generally available (Marc Zyngier)
- Allow matching of interrupt-maps local to interrupt controller or PCI
device (Marc Zyngier)
- Add Apple SoC (e.g., M1) PCIe host controller driver, which enables
access to USB type-A, Ethernet, Wi-Fi, Bluetooth devices; these require
additional drivers of their own (Alyssa Rosenzweig)
- Add apple INTx, per-port, and MSI interrupt support (Marc Zyngier)
- Configure apple Requester-ID-to-Stream-ID mapper for IOMMU (DART) support
(Marc Zyngier)
* pci/host/apple:
PCI: apple: Configure RID to SID mapper on device addition
iommu/dart: Exclude MSI doorbell from PCIe device IOVA range
PCI: apple: Implement MSI support
PCI: apple: Add INTx and per-port interrupt support
PCI: apple: Set up reference clocks when probing
PCI: apple: Add initial hardware bring-up
PCI: of: Allow matching of an interrupt-map local to a PCI device
of/irq: Allow matching of an interrupt-map local to an interrupt controller
irqdomain: Make of_phandle_args_to_fwspec() generally available
- Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár)
- Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár)
- Downgrade PIO Response Status messages to debug level (Marek Behún)
- Preserve CRS SV (Config Request Retry Software Visibility) bit in
emulated Root Control register (Pali Rohár)
- Fix issue in configuring reference clock (Pali Rohár)
- Don't clear status bits for masked interrupts (Pali Rohár)
- Don't mask unused interrupts (Pali Rohár)
- Avoid code repetition in advk_pcie_rd_conf() (Marek Behún)
- Retry config accesses on CRS response (Pali Rohár)
- Simplify emulated Root Capabilities initialization (Pali Rohár)
- Fix several link training issues (Pali Rohár)
- Fix link-up checking via LTSSM (Pali Rohár)
- Fix reporting of Data Link Layer Link Active (Pali Rohár)
- Fix emulation of W1C bits (Marek Behún)
- Fix MSI domain .alloc() method to return zero on success (Marek Behún)
- Read entire 16-bit MSI vector in MSI handler, not just low 8 bits (Marek
Behún)
- Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits at
startup; PCI core will set those as necessary (Pali Rohár)
- When operating as a Root Port, set class code to "PCI Bridge" instead of
the default "Mass Storage Controller" (Pali Rohár)
- Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't
implement this per spec (Pali Rohár)
- Add emulation of option ROM BAR since aardvark doesn't implement this per
spec (Pali Rohár)
* remotes/lorenzo/pci/aardvark:
PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge
PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge
PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge
PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG
PCI: aardvark: Fix return value of MSI domain .alloc() method
PCI: pci-bridge-emul: Fix emulation of W1C bits
PCI: aardvark: Fix reporting Data Link Layer Link Active
PCI: aardvark: Fix checking for link up via LTSSM state
PCI: aardvark: Fix link training
PCI: aardvark: Simplify initialization of rootcap on virtual bridge
PCI: aardvark: Implement re-issuing config requests on CRS response
PCI: aardvark: Deduplicate code in advk_pcie_rd_conf()
PCI: aardvark: Do not unmask unused interrupts
PCI: aardvark: Do not clear status bits of masked interrupts
PCI: aardvark: Fix configuring Reference clock
PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridge
PCI: aardvark: Don't spam about PIO Response Status
PCI: aardvark: Fix PCIe Max Payload Size setting
PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros
The Apple PCIe controller doesn't directly feed the endpoint's Requester ID
to the IOMMU (DART), but instead maps RIDs onto Stream IDs (SIDs). The DART
and the PCIe controller must thus agree on the SIDs that are used for
translation (by using the 'iommu-map' property).
For this purpose, parse the 'iommu-map' property each time a device gets
added, and use the resulting translation to configure the PCIe RID-to-SID
mapper. Similarly, remove the translation if/when the device gets removed.
This is all driven from a bus notifier which gets registered at probe time.
Hopefully this is the only PCI controller driver in the whole system.
[bhelgaas: squash indentation from Zhaoyu Liu <zackary.liu.pro@gmail.com>:
https://lore.kernel.org/r/20211031135544.GA1616@pc]
Link: https://lore.kernel.org/r/20210929163847.2807812-10-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
The MSI doorbell on Apple HW can be any address in the low 4GB range.
However, the MSI write is matched by the PCIe block before hitting the
iommu. It must thus be excluded from the IOVA range that is assigned to any
PCIe device.
Link: https://lore.kernel.org/r/20210929163847.2807812-9-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Probe for the 'msi-ranges' property, and implement the MSI support in the
form of the usual two-level hierarchy.
Note that contrary to the wired interrupts, MSIs are shared among all the
ports.
Link: https://lore.kernel.org/r/20210929163847.2807812-8-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Add support for the per-port interrupt controller that deals with both INTx
signalling and management interrupts.
This allows the Link-up/Link-down interrupts to be wired, allowing the
bring-up to be synchronised (and provide debug information). The framework
can further be used to handle the rest of the per port events if and when
necessary.
Likewise, INTx signalling is implemented so that end-points can actually be
used.
Link: https://lore.kernel.org/r/20210929163847.2807812-7-maz@kernel.org
Link: https://lore.kernel.org/r/20211004150552.3844830-1-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Now that everything is in place at the poweroff sequence, this driver can
use module_platform_driver(), which allows it to be removed.
Link: https://lore.kernel.org/r/53b40494252444a9b830827922c4e3a301b8f863.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
The logic under .remove ops is missing a call to dw_pcie_host_deinit(). Add
it, in order to allow the DWC core to be properly cleaned up.
Link: https://lore.kernel.org/r/838621e1c84ebaac153ccd9c36ea5e1254c61ead.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
The logic at kirin_pcie_gpio_request() enables some clkreq GPIO lines.
Disable them during power-off.
Link: https://lore.kernel.org/r/f403e590843de1a581cade2d534d34715706f54e.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Instead of having two copies of the same logic, place the power-off logic
in a separate function.
No functional changes.
Link: https://lore.kernel.org/r/64f6e8da3e5fff38b6c8fcb208ace46efe6555bb.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
There's nothing preventing this driver from being loaded as a module.
Change its config from bool to tristate.
Link: https://lore.kernel.org/r/b5e7cfe9df09b492750bd6db0f0c911eaae8c2d4.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Apple's PCIe controller requires clocks to be configured in order to
bring up the hardware. Add the register pokes required to do so.
Adapted from Corellium's driver via Mark Kettenis's U-Boot patches.
Co-developed-by: Stan Skowronek <stan@corellium.com>
Link: https://lore.kernel.org/r/20210929163847.2807812-6-maz@kernel.org
Signed-off-by: Stan Skowronek <stan@corellium.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Add a minimal driver to bring up the PCIe bus on Apple system-on-chips,
particularly the Apple M1. This driver exposes the internal bus used for
the USB type-A ports, Ethernet, Wi-Fi, and Bluetooth. Bringing up the
radios requires additional drivers beyond what's necessary for PCIe itself.
Co-developed-by: Stan Skowronek <stan@corellium.com>
Link: https://lore.kernel.org/r/20210929163847.2807812-5-maz@kernel.org
Signed-off-by: Stan Skowronek <stan@corellium.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
We already include <linux/device.h> and <linux/msi.h>, which
include <asm/device.h> and <asm/msi.h>.
Drop the redundant includes of <asm/device.h> and <asm/msi.h>.
[bhelgaas: squash in fix from Wan Jiabing <wanjiabing@vivo.com>:
https://lore.kernel.org/r/20211104063720.29375-1-wanjiabing@vivo.com]
Link: https://lore.kernel.org/r/20211013003145.1107148-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Derrick <jonathan.derrick@linux.dev>
If an error occurs after a successful cdns_pcie_init_phy() call, it must be
undone by a cdns_pcie_disable_phy() call, as already done above and below.
Update the goto to branch at the correct place of the error handling path.
Link: https://lore.kernel.org/r/db477b0cb444891a17c4bb424467667dc30d0bab.1624794264.git.christophe.jaillet@wanadoo.fr
Fixes: 49e0efdce7 ("PCI: j721e: Add support to provide refclk to PCIe connector")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
The PHY layer need to access APB registers too, for Kirin 970. So place
them into a named regmap.
Link: https://lore.kernel.org/r/daf0e4bda5a69a5ac8484e70f09351a959805c8c.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
The pcie-kirin driver contains both PHY and generic PCI driver.
The best would be, instead, to support a PCI PHY driver, making the driver
more generic.
However, it is too late to remove the Kirin 960 PHY, as a change like that
would make the DT schema incompatible with past versions.
So, add support for an external PHY driver without removing the existing
Kirin 960 PHY from it.
Link: https://lore.kernel.org/r/f38361df2e9d0dc5a38ff942b631f7fef64cdc12.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
The pcie-kirin PCIe driver contains internally a PHY interface for
Kirin 960.
As the next patches will add support for using an external PHY driver,
reorganize the driver in a way that the PHY part will be self-contained.
This could be moved to a separate PHY driver, but a change like that would
mean a non-backward-compatible DT schema change.
Link: https://lore.kernel.org/r/ad2f4aa6bbb71d5c9af0139704672f75f12644fc.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Aardvark supports PCIe Hot Reset via PCIE_CORE_CTRL1_REG.
Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL
register on emulated bridge.
With this, the function pci_reset_secondary_bus() starts working and can
reset connected PCIe card. Custom userspace script [1] which uses setpci
can trigger PCIe Hot Reset and reset the card manually.
[1] https://alexforencich.com/wiki/en/pcie/hot-reset-linux
Link: https://lore.kernel.org/r/20211028185659.20329-7-kabel@kernel.org
Fixes: 8a3ebd8de3 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Aardvark controller has something like config space of a Root Port
available at offset 0x0 of internal registers - these registers are used
for implementation of the emulated bridge.
The default value of Class Code of this bridge corresponds to a RAID Mass
storage controller, though. (This is probably intended for when the
controller is used as Endpoint.)
Change the Class Code to correspond to a PCI Bridge.
Add comment explaining this change.
Link: https://lore.kernel.org/r/20211028185659.20329-6-kabel@kernel.org
Fixes: 8a3ebd8de3 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
From very vague, ambiguous and incomplete information from Marvell we
deduced that the 32-bit Aardvark register at address 0x4
(PCIE_CORE_CMD_STATUS_REG), which is not documented for Root Complex mode
in the Functional Specification (only for Endpoint mode), controls two
16-bit PCIe registers: Command Register and Status Registers of PCIe Root
Port.
This means that bit 2 controls bus mastering and forwarding of memory and
I/O requests in the upstream direction. According to PCI specifications
bits [0:2] of Command Register, this should be by default disabled on
reset. So explicitly disable these bits at early setup of the Aardvark
driver.
Remove code which unconditionally enables all 3 bits and let kernel code
(via pci_set_master() function) to handle bus mastering of Root PCIe
Bridge via emulated PCI_COMMAND on emulated bridge.
Link: https://lore.kernel.org/r/20211028185659.20329-5-kabel@kernel.org
Fixes: 8a3ebd8de3 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org # b2a56469d5 ("PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access")
The PCIE_MSI_PAYLOAD_REG contains 16-bit MSI number, not only lower
8 bits. Fix reading content of this register and add a comment
describing the access to this register.
Link: https://lore.kernel.org/r/20211028185659.20329-4-kabel@kernel.org
Fixes: 8c39d71036 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
