Commit Graph

5 Commits

Author SHA1 Message Date
Lucas Stach
2f64a55443 gpu: ipu-v3: pre: add tiled prefetch support
This configures the TPR unit, using the DRM format modifier. For now only
the single buffer modifiers are supported, as split buffer needs more
configuration for the required cropping.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
[p.zabel@pengutronix.de: rebased after ERR009624 workaround]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-12-19 12:49:11 +01:00
Lucas Stach
7294408973 gpu: ipu-v3: prg: switch to runtime PM
Instead of open-coding the clk enable/disable in all of the callers
move this to the RPM suspend/resume functions.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-12-19 12:49:11 +01:00
Lucas Stach
263c3b8044 gpu: ipu-v3: prg: wait for double buffers to be filled on channel startup
Wait for both double buffer to be filled when first starting a channel.
This makes channel startup a lot more reliable, probably because it allows
the internal state machine to settle before the requests from the IPU are
coming in.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
[p.zabel@pengutronix.de: rebased before switch to runtime PM]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-10-11 12:04:23 +02:00
Lucas Stach
16e9ab820a gpu: ipu-v3: prg: remove counter load enable
The counter load enable bit has no effect when the shadow register
set is activated. As we always operate the PRG with shadow enabled
it is safe to remove this.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-08 08:57:13 +02:00
Lucas Stach
ea9c260514 gpu: ipu-v3: add driver for Prefetch Resolve Gasket
This adds support for the i.MX6 QUadPlus PRG unit. It glues together the
IPU and the PRE units.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
v4: add missing ipu_soc->prg_priv
2017-03-16 10:14:02 +01:00