- add missing (and currently unused) pad groups
- assign muxed GPIO pads for X1 to gpio2 node
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds muxing and configuration of the irq output of the temp
sensor on TQMa93xx that is connected to a GPIO line on MBa93xxLA
While at it, add comment for RTC_EVENT for pcf85063 since the IRQ line
of both devices on SoM are routed to CPU GPIO on MBa93xxLA.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LPSPI6 features a NAFE13388 analog frontend.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
- disable PU/PD if already done with external resistors
- do not configure Schmitt Trigger for outputs
- do not configure DSE / FSEL for inputs
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With PMIC node in place, add the correct regulators for eMMC.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With driver support in place add the PMIC node and remove the
fixed-regulators for rails provided by PMIC.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Update the DT to match newest Data Modul i.MX8M Mini eDM SBC rev.A01
board which implements PHY changes. Keep some of the rev.900 PHY node
in the DT so that a DTO can be used to support rev.900 boards easily.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The ISP supports both CSI and parallel interfaces, where port 0
corresponds to the former and port 1 corresponds to the latter. Since
the i.MX8MP's ISPs are connected by the parallel interface to the CSI
receiver, set them both to port 1.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add fixed regulator VCC_5V_SW based on the phyBOARD-Pollux schematics
to reflect the connectivity on the phyBOARD-Pollux-i.MX8MP.
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add SD-Card property for the bus IO power from the PMIC.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add fixed regulator VDD_IO (3.3v) based on the SoM schematics to reflect
the connectivity on the phyCORE-i.MX8MP.
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The DT nodes for the MIPI CSI-2 receivers (MIPI_CSI) configure the
CAM1_PIX and CAM2_PIX clocks to 266 MHz through the assigned-clock-rates
property, and report that frequency in the clock-frequency property. The
i.MX8MP reference manual and datasheet list 266 MHz as a nominal
frequency when using both CSI-2 receivers, so all looks normal.
In reality, the clock is actually set to 250 MHz, as the selected
parent, IMX8MP_SYS_PLL2_1000M, has a 1/4 output that is selected as the
closest frequency to 266 MHz. This doesn't break operation of the
device, but is clearly misleading.
Clarify the clock configuration by selecting the IMX8MP_SYS_PLL2_250M
parent, dropping the redundant assigned-clock-rates, and setting
clock-frequency to 250 MHz. This doesn't cause any functional change.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds support for the Kontron Electronics OSM-S i.MX93 SoM
and the matching baseboard BL i.MX93.
The SoM hardware complies to the Open Standard Module (OSM) 1.1
specification, size S (https://sget.org/standards/osm).
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Taishan Pi RK3566, ODROID-M1S,NanoPC-T6 LTS, Cool Pi CM5 GenBook
Big number of improvements for NanoPC-T6,QNAP-TS433 and FastRhino R66S
With recent dtc changes making it into linux-next the Wolfvision Visualizer
overlay finally compiles without warnings. And smaller number of
improvements on a number of Radxa boards.
Interesting new additions on a soc-level are the hardware RNG on rk3568,
an additional sdmmc-controller (not supported before) on rk3328 and
v4l video codecs for the rk3588 (decoding of h.264 amongst others).
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmbU4y4QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgXGsCACrCrqd90s6oE5y2dhmgyPdBHUmohhkE/m/
lq30aHjYROYlpNkFTVDezL9qaX74LkZ4vBMpd//189b2vp+vQOEOYN5Sjs2vrilY
f7Z1Wq38Czude4+AkOLMpnG/PExdtFO2AIjo4Zcg5i7NvC5eFd/59IyE4SoRzfEQ
f2AZ5iUPHrYjLgpUCoFBf9ydR4u2nZIrTEeVIij+1lGYfF9fHpoERpFBlIeUUzBB
C4e7AkAbty+O+OrXYM9v4vvWZMQzinAxCEBgt6I7bkj/JGIHOilPtk//7ejRIAlM
vRd6JwpRHyFAca9UBe+hmCf4o6q0PBgBnk3Pzu7v/2urf7hb9Egr
=66Iu
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbW5zQACgkQYKtH/8kJ
UidcfA/+ON1rt9j7KwdvKOuGr20cBBoEPWaK0IocYzeLwrMwRQzlsOtftIdNB4tT
ANxZ6sxL3MEpj8g+WyittHC0yar4g/09sYq3I00y9PHHWeDp2w2aht3DqrstKBpu
l3cY1YtR1bZCrnNGhEBwJABIT3svhd/EBLfB+fNHFyxfVpufq0Bs0lIcIX0SjG10
TZxCGMFPrpg1X7XCZ/GIicPe+b1Yw5RFMKHorxLgK5GFTBozAV66S6oi2czVuQFQ
BtnOG1tjTGU7Udzfrr3a19wjIBwqigmovEh+/uUBp/VG27SQ7VBBymjUIeDkoAE5
oIBtC91EewTTbQ7wsjAY8CF+0E+O6T0wTQAgU3SDXf6LVXKA0MkxbqJ9tRrooETs
CNfHJ31VoyI4a2LqVaY7KyAUgAU3GglD+21beA0h7psnqWGKLeUM9rNCaNH1NWpV
KNHZSg5rLtVuLY6/kCCGbDj/HrrQ9FTtFHbLYGiXPZSvi2pbEsDUHwcYOPp10l0z
MAAsOrU+pFg5zoe53iZVF5fL2vMoSF9kvAlbqQfJUWwneft9fbwbLWl+b0/Jn0Un
xxSvix2Ip4f8pVE1nCmRlqHWp9nQDt7hj+K4AIu4vLoY/TT1JyIADqDk6IodMrjY
lKt/ckcOTeh5pSLuzxaI5RYYjAKBGhCxsSYGXpHZx0nz7TPD2jI=
=nwGo
-----END PGP SIGNATURE-----
Merge tag 'v6.12-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: Firefly PX30 Core SoM with JD4 baseboard, NanoPi 2S Plus,
Taishan Pi RK3566, ODROID-M1S,NanoPC-T6 LTS, Cool Pi CM5 GenBook
Big number of improvements for NanoPC-T6,QNAP-TS433 and FastRhino R66S
With recent dtc changes making it into linux-next the Wolfvision Visualizer
overlay finally compiles without warnings. And smaller number of
improvements on a number of Radxa boards.
Interesting new additions on a soc-level are the hardware RNG on rk3568,
an additional sdmmc-controller (not supported before) on rk3328 and
v4l video codecs for the rk3588 (decoding of h.264 amongst others).
* tag 'v6.12-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (62 commits)
arm64: dts: rockchip: drop unsupported regulator-property from NanoPC-T6
arm64: dts: rockchip: drop unsupported regulator property from NanoPC-T6
arm64: dts: rockchip: use correct fcs,suspend-voltage-selector on NanoPC-T6
arm64: dts: rockchip: add Mask Rom key on NanoPC-T6
arm64: dts: rockchip: enable USB-C on NanoPC-T6
arm64: dts: rockchip: enable GPU on NanoPC-T6
arm64: dts: rockchip: add IR-receiver to NanoPC-T6
arm64: dts: rockchip: add SPI flash on NanoPC-T6
arm64: dts: rockchip: add NanoPC-T6 LTS
arm64: dts: rockchip: move NanoPC-T6 parts to DTS
arm64: dts: rockchip: prepare NanoPC-T6 for LTS board
dt-bindings: arm: rockchip: Add NanoPC-T6 LTS
arm64: dts: rockchip: disable display subsystem only for Radxa E25
arm64: dts: rockchip: enable PCIe on M.2 E key for Radxa ROCK 5A
arm64: dts: rockchip: remove unnecessary properties for Radxa ROCK 5A
arm64: dts: rockchip: add dts for LCKFB Taishan Pi RK3566
dt-bindings: arm: rockchip: Add LCKFB Taishan Pi RK3566
dt-bindings: vendor-prefixes: Add Shenzhen JLC Technology Group LCKFB
arm64: dts: rockchip: Add Hardkernel ODROID-M1S
dt-bindings: arm: rockchip: Add Hardkernel ODROID-M1S
...
Link: https://lore.kernel.org/r/6322098.17fYzF0512@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a slew of cleanups and consolidation changes for several
Orin boards and also fix some minor issues and enable more features on
the Jetson TX1.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmbR0fIACgkQ3SOs138+
s6HAWw//cB9J6sjY289VRdfS9rMiI7wzVhe6F/FzUljSfTX5cMou2J/SeJQruYyK
f058WzlWlseR91TIf11AFDNDPbMzAHyReU4aE0PD2fiyQE1jor8AhlmISXwvpqMZ
pxFmKkDrO0YTODam5xFPDFjyt/lIe1UpcIIXfx/19/dTinLoiXmLuaIPM5xkMh5G
DsRlN1Zfh99QwJQXCtPa/Y0IWYWngqr8i98k+xB5TTFSUaM1L61PJL3zYqaSSI4v
1XFCbZ/XhOL1vbg23sY0mXSl62SKAvrRP1hlij2o5YHoB8rT/qVvoXuTwEkrhOoV
qeRRsmt6F1pZLto+feRelauxQDy5EVkQTxJbeABoud5EhaBXCqgr44/bD8PxynX0
Ye7NWNrr32YPytgmiMDlxAMW5jZm+oL+G+bCG5TIeTFW08+Jvxm2A+2cnhZMoqey
3Un3wjHByXfkdGov28p9XSkeCk1y3VUPyjt18A3CR5JqE7lMlvyrCxuvpNJ/BsqN
FGeHlmRffRx1Z7Kv6kJ2qp4dwqAAMg1lMlkNaYzv9fH1mZS4nzzOenSRofLgg9S4
ZXBqcoiRvfWM8oBUME08MQw4f/AYgS6qxhGONxmC1tCnYBEUIanDWxfVr9bJrQwP
dvRdQbCeOVSXF9kP3PkCEUngPApW7l6iC5uAQBNGDogGtHYfaAg=
=9eOb
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbW5kcACgkQYKtH/8kJ
Uif7ERAA4PtYrX7BxGAWOJVdiNKv43WDaDNq8t2S0nwQbfa6TWap6hiCSxevK9da
yescLLRLxTPPQZ2xbBTYBuV6I1NlI/JqcSTmQfrBGzpps2xj1dGG4wkNSOMx1MIW
kAcYRQPWOMkmNwr+lyPM4LNVGe3Xis/5oLXVOMOtaQNvDxxnJeZTlLevqpHljLku
ZKHGW88CS+wVHqhU6ozDPD6TPOT3zEy5+1wQ44gxYEpMY49GAgup35rqbhKvXP7h
PIl2fuESW9mgENG5jpfxK5trqprlAf0tdFlu6PbyOnsCcNxXpSQ9C3OsOg4iAdS3
c1qhksIC1F4pwxqiHDyN9ucDlzPJY95RpGf59MlAcBwLZU/2w75a4TDTgw2y72yy
67RYXnkOph++N8259tkF+EN2+CZuyXBVwUMBFJLGwtYGl+JhKYkyfLuq5QRTCoEU
6fFStTWUI5NcBqjpSc+mF5aftDCTx41IZTz1PGBW7vAdMnQ0AsGdRZKWR2ezNw/j
yVjqEkj+DKiBUkC0qx4g6blE71tRm9wB3ub64vwzt7uoB4QlXXwO28q5UaGW71ao
fn4x4rwa/uND4/HXiRcLjAyv07hRJXhmtMQrkKeRERMBhMeyJmgwNEq8WgVmJAMe
Cb37obFW3c0BXFS80IJWqfkEIRKoDDescfqNsCNtgejF839/m2c=
=MPzU
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.12-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.12-rc1
This contains a slew of cleanups and consolidation changes for several
Orin boards and also fix some minor issues and enable more features on
the Jetson TX1.
* tag 'tegra-for-6.12-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add thermal nodes to AGX Orin SKU8
arm64: tegra: Move BPMP nodes to AGX Orin module
arm64: tegra: Move padctl supply nodes to AGX Orin module
arm64: tegra: Move AGX Orin nodes to correct location
arm64: tegra: Combine IGX Orin board files
arm64: tegra: Combine AGX Orin board files
arm64: tegra: Add common nodes to AGX Orin module
arm64: tegra: Wire up WiFi on Jetson TX1 module
arm64: tegra: Wire up Bluetooth on Jetson TX1 module
arm64: tegra: Wire up power sensors on Jetson TX1 DevKit
arm64: tegra: Add p3767 PCIe C4 EP details
arm64: tegra: Add Tegra234 PCIe C4 EP definition
arm64: tegra: Add wp-gpio for P2597's external card slot
arm64: tegra: Fix gpio for P2597 vmmc regulator
arm64: tegra: Correct location of power-sensors for IGX Orin
arm64: tegra: enable same UARTs for Orin NX/Nano
arm64: tegra: Add DMA properties for Tegra234 UARTA
Link: https://lore.kernel.org/r/20240830141004.3195210-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Just a single update adding stdout-path to the fast models(FVP and
Foundation) which eliminates the need to specify any platform-specific
kernel command line parameters to get working earlycon or console.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmbRpBAACgkQAEG6vDF+
4phWzA//TjMkMtmaAkR2sntQmAeBTOkiLEpX6siJDsxGhkdKYTvQAOwwmgJC3fQJ
lf1Xqw7bh+3YymW9QjUpvs6MAT4Z+y/lmmxaMO4SOnD1zcTKX76ouDXwMw6rEyba
XiqeGLwd2fEf2dQnLOsUsNXOnuY4uPx3usECgYeb4MYFihdMxEr4WGM+8jzm+WPn
eNRDL0h/piAOehQzBzCnr+USvJNS+aHmLraMdGSwF7AZVdCP9HlveGPizY7EtSFu
unlsHy71t0pdGuOSbLGruS0FGzVOmTw7kf7mvvLzNPZsgITbT6NTUtakiL4tnwBg
aXiDRLWiSIKylPfSftafCgGYUhImGCs7r4SeyB2+DkGQ04GNNtlRa5YQubs9sQrI
KIxezSVnrPu02ycB24t8dfALid6UuCnVVpRbt2OEe8S4Ry9gbbWqd7HibJ5QcDON
4Y1QcuuZoSvny8mvVIlgbyK2zuF0PWf/vWitJFGyWGVFiDhyDjFVC4/Il4Gs/iQi
j+QjcOgSSh7IgEXGS4RFQrJUkZW+UEud0slFzgMxB3W/NK11U02ia7rUTERKsvt7
v2Um0OuvzCs+NurxcojjEy4TDzcFQaCOn7TEINkW/jTX0s1wi89lNPLRNUy9AarV
WesNvUjMdCnxereKZnHQlkPVu5e00Oa0M2irJZJPsQ7STfxlkQY=
=7rHm
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbW5YYACgkQYKtH/8kJ
UifOwhAAv1JbhiJRRBDB9hZnJCkasb9vsRKzqiy2Eme2rXhLrmMIUugrXc/We4wH
rOi8u6abVMRVpcUgjLJNiof4EsIvy7gZKNPpL6YpI2VaR2JcyURxaE4FWxdMASgo
z4ivxcGukvyWWxAUiDBDHOVuictIx9yjjDzddvQcPwq/GzuUPHS38SBHpcWPRLJy
hWUmqYl0B1HtjD41CNGD2edrunbE8M1yo+3kfGw1zAvMbVsqpklPLB9N0JCX4waG
HymCyHRgrFqfns3YM1oWXWfGzjVyWLLF+QdygwC/Jl7GveJ/KfN4IgkAj1mx2F4Q
MhFfThMEIZB44tlLThusKy9zf0tLHUaflVW3B1QahBrY/qEtogWQEXZrQV4bUvxK
LqEhKKciPdsNpm8NMSWhfBiMJ7uVLpGem4TmMAwn06in7UF//bToHuUYAPd5q1bQ
Mp/1ceQZLuPuviR99ivgUrgqLrb2bDGstPCGj/CeRkoJRzO7JdysNlE+IoWXTGiA
TPPk5fG+4BtsspuTRko0DIf7Rb2DC0Y/Byy7gMmHALquiowX0u3B3gaeWjmhM2F0
/C6Wh06Zn0yHbSE7YMzhxoihLv6xaMSO/vMuBqa9BB3mXA9H0fY82rxvXq4XDe+f
fz3taUYTc2ayGe6Fu3SdOCmPbJbViVef8gG9uCN69wtwB0SCD+M=
=+Og8
-----END PGP SIGNATURE-----
Merge tag 'juno-update-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/FVP update for v6.12
Just a single update adding stdout-path to the fast models(FVP and
Foundation) which eliminates the need to specify any platform-specific
kernel command line parameters to get working earlycon or console.
* tag 'juno-update-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: fvp: Set stdout-path to serial0 in the chosen node
Link: https://lore.kernel.org/r/20240830135837.2383557-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable support for AK4619 codecs and Renesas R-Car Ethernet-TSN
controllers in the ARM64 defconfig,
- Enable slab hardening and kmalloc buckets in the Renesas ARM
defconfig.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZsbubAAKCRCKwlD9ZEnx
cOaHAQCizOEU5damvBCBzcAaKbSGKc+psBUJogJ/ic19I5B4NAD/aOihRr4iCJZe
MckRf7P2BebH75TbwTstZMscRkkGAAU=
=Wr7F
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbW4wAACgkQYKtH/8kJ
UifX7xAAvO9EuI8hfOtLUmlXEUFYAZaqLSqNwg4i7s6U7qjn2Zt5dexTHOI90U1K
nZve4C2tp1/1llhWDxipna6FgXXYzdBM9LHPpGyzweQufeXYXCIDG7ECg13/5iCE
ibtvj1FFi9ZVFcneMUhyJo6b5epYw8ZJ50XjaCscH3Wo5FuLaJSZ9CnTUegO8Eff
NXJ43DA7bWh3dZdeuintC4wurooh4DAdDkwAAeWzxu8LDwGxREN0Q0JTod10cEME
pkVHctH0L3RtXrRaX/PTE7so2Cg4gjCR6qJv1FdCnE4NHi3Fs4humaddEc2iL4VQ
aOPIxHRcsJWJlZKG5afTaDUhDq0LuwvoaBmDLT8dlyYSp1k1QF9wRK6vvSEUe71Q
c26IUi5mZk1OWPQ/qvD43jtnkat9ZefDHkFaEvfCKQovBwzNkSBI6TApd+MImcQR
gZ3zb/z412An0yqOPU/q6oyAzMUvXIbzELXyIu+7p8dgk4veE/eq072EYAnS7J/5
fHF250ZXyZqxktUF2FdzLvHkLjux9eeIuruf+9nayHynF73PHpcw9rrWGQM2SaMG
vA/VNpf3Itx1+Ov/T6qo5lRf/2Y67c7gNrPdMt1PLNRiFHY5SmUeTIfe46rtFucE
usi4i2GnlpSliT0Xu44X9p8VxPJ6trSUGIfRApywgLxUhfZMA80=
=VxDt
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-defconfig-for-v6.12-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig
Renesas ARM defconfig updates for v6.12
- Enable support for AK4619 codecs and Renesas R-Car Ethernet-TSN
controllers in the ARM64 defconfig,
- Enable slab hardening and kmalloc buckets in the Renesas ARM
defconfig.
* tag 'renesas-arm-defconfig-for-v6.12-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable R-Car Ethernet-TSN support
ARM: shmobile: defconfig: Enable slab hardening and kmalloc buckets
arm64: defconfig: Enable AK4619 codec support
Link: https://lore.kernel.org/r/cover.1724316480.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The usage of the R-Car V4M CSISP bindings where merged before the
bindings where approved. At that time the family fallback compatible
where not part of the bindings, add them.
Fixes: 2bb78d9fb7 ("arm64: dts: renesas: r8a779h0: Add video capture nodes")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20240826144352.3026980-7-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
To make it easier to support new R-Car Gen4 SoCs add a family fallback
compatible similar to what was done for VIN on R-Car Gen4.
There is no functional change, but the addition of the family fallback
in the bindings produces warnings for R-Car V3U for DTS checks if they
are not added.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240826144352.3026980-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
To make it easier to support new R-Car Gen4 SoCs add a family fallback
compatible similar to what was done for VIN on R-Car Gen4.
There is no functional change, but the addition of the family fallback
in the bindings produces warnings for R-Car V4H for DTS checks if they
are not added.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240826144352.3026980-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The usage of the R-Car V4M VIN bindings where merged before the bindings
where approved. At that time the family fallback compatible was not
part of the bindings, add it.
Fixes: 2bb78d9fb7 ("arm64: dts: renesas: r8a779h0: Add video capture nodes")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20240704161620.1425409-7-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
To make it easier to support new R-Car Gen4 SoCs a family fallback
compatible similar to what is used for R-Car Gen2 has been added to the
VIN bindings. Add this fallback to the R-Car V3U DTSI.
There is no functional change, but the addition of the family fallback
in the bindings produces warnings for R-Car V3U for DTS checks if they
are not added.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20240704161620.1425409-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
To make it easier to support new R-Car Gen4 SoCs a family fallback
compatible similar to what is used for R-Car Gen2 has been added to the
VIN bindings. Add this fallback to the R-Car V4H DTSI.
There is no functional change, but the addition of the family fallback
in the bindings produces warnings for R-Car V4H for DTS checks if they
are not added.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20240704161620.1425409-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fix warning when use W=1 to build dtb, as following error:
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi:65.7-76.4: Warning
(unit_address_vs_reg): /sram: node has a reg or ranges property,
but no unit name
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi:168.34-413.6: Warning
(unit_address_vs_reg): /soc/bus@fe000000/pinctrl@4000: node has a
unit name, but no reg or ranges property
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi:168.34-413.6: Warning
(simple_bus_reg): /soc/bus@fe000000/pinctrl@4000: missing or empty
reg/ranges property
arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts:205.9-245.4:
Warning (avoid_unnecessary_addr_size): /soc/bus@fe000000/spi@56000
/nand@0: unnecessary #address-cells/#size-cells without "ranges",
"dma-ranges" or child "reg" property
Fixes: d4bd8f3023 ("arm64: dts: amlogic: add C3 AW419 board")
Fixes: 520b792e83 ("arm64: dts: amlogic: add some device nodes for C3")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/r/202409010005.A7tSzgEn-lkp@intel.com/
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240902-fix_warning-v1-1-037029c584fc@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The K3 J722S-EVM platform is based on the J722S SoC which has one
single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN
voltage domain, and two C71x DSP subsystems in MAIN voltage domain.
The Inter-Processor communication between the A53 cores and these R5F
and DSP remote cores is achieved through shared memory and Mailboxes.
Thus, add the memory carveouts and enable the mailbox clusters required
for communication.
Also, The remoteproc firmware like of R5F and DSPs in the MAIN voltage
domain use timers. Therefore, change the status of the timer nodes to
"reserved" to avoid any clash during booting of remotecores. Usage is
described as below:
+===================+=============+
| Remoteproc Node | Timer Node |
+===================+=============+
| main_r5fss0_core0 | main_timer0 |
+-------------------+-------------+
| c7x_0 | main_timer1 |
+-------------------+-------------+
| c7x_1 | main_timer2 |
+-------------------+-------------+
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20240830161742.925145-3-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each
of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems
in MAIN voltage domain. Add the DT nodes to support Inter-Processor
Communication.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
[ refactoring changes to k3-j722s-main.dtsi ]
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240830161742.925145-2-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Commit 73f1f26e2e ("arm64: dts: ti: k3-am68-sk-som: Add support
for OSPI flash") introduced the flash node with discontinuous
partitions. Updating the partition offset to be continuous from
the previous partition to maintain linearity.
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Link: https://lore.kernel.org/r/20240828060830.555733-1-p-mantena@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
BeagleBoard.org BeagleY-AI is an easy to use, affordable open source
hardware single board computer based on the Texas Instruments AM67A,
which features a quad-core 64-bit Arm CPU subsystem, 2 general-purpose
digital-signal-processors (DSP) and matrix-multiply-accelerators (MMA),
GPU, vision and deep learning accelerators, and multiple Arm Cortex-R5
cores for low-power, low-latency GPIO control.
https://beagley-ai.org/https://openbeagle.org/beagley-ai/beagley-ai
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Jared McArthur <j-mcarthur@ti.com>
Link: https://lore.kernel.org/r/20240829213929.48540-2-robertcnelson@gmail.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Each Ethernet PHY on IOT2050 platforms drives 3 LEDs whose triggers
can be configured to signal link properties such as connection status
or speed.
Declare the LEDs, exposing their trigger controls to userspace.
Signed-off-by: Diogo Ivo <diogo.ivo@siemens.com>
Link: https://lore.kernel.org/r/20240829-ivo-iot2050_leds-v1-1-792a512b2178@siemens.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add Error Signaling Module (ESM) instances in MCU and MAIN domains,
set ESM interrupt sources for rti as per TRM [0] 9.4 Interrupt
Sources.
There are no ESM0_ESM_INT* events routed to MCU ESM, so it is not
possible to reset the CPU using watchdog and ESM0 configuration.
However add ESM instances for device completion.
Add comments to describe what interrupt sources are routed to ESM
modules.
[0] http://www.ti.com/lit/pdf/spruid7
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-7-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add Error Signaling Module (ESM) instances in MCU and MAIN domains,
set ESM interrupt sources for rti as per TRM [0] 10.4 Interrupt
Sources.
Add comments to describe what interrupt sources are routed to ESM
modules.
[0] https://www.ti.com/lit/pdf/spruj16
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-2-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add comments to describe what interrupt sources are routed to ESM
modules.
There is no functional change.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-5-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Fix interrupt sources for rti routed to the ESM0 as per [0], in 10.4
Interrupt Sources
Add comments to describe what interrupt sources are routed to ESM
modules.
[0] https://www.ti.com/lit/pdf/spruj83
Fixes: b5080c7c1f ("arm64: dts: ti: k3-am62p: Add nodes for more IPs")
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-3-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Remove 'reserved' status for MCU ESM node. Watchdog reset is
propagated through ESM0 to MCU ESM to reset the CPU, so enable MCU ESM
to reset the CPU with watchdog timeout.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240815204833.452132-4-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Fix the gpio hog node name to p15-hog to match up with gpio-hog
convention. This fixes dtbs_check warning:
p15: $nodename:0: 'p15' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$'
Acked-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240830102822.3970269-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Rename the pin mux and gpio-hog node names to match up with binding
rules. This fixes dtbs_check warnings:
'gpmc0-pins-default' does not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', 'pinctrl-[0-9]+'
'gpio0-36' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$'
While at it, change the phandle name to be consistent with the pinctrl
naming.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20240830113137.3986091-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although
not used currently by the Linux FSS driver, these regions belong to
the FSS and should be included in the ranges mapping.
While here, a couple of these numbers had missing zeros which was
hidden by odd alignments, fix both these issues.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://lore.kernel.org/r/20240828172956.26630-5-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although
not used currently by the Linux FSS driver, these regions belong to
the FSS and should be included in the ranges mapping.
While here, a couple of these numbers had missing zeros which was
hidden by odd alignments, fix both these issues.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://lore.kernel.org/r/20240828172956.26630-4-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although
not used currently by the Linux FSS driver, these regions belong to
the FSS and should be included in the ranges mapping.
While here, a couple of these numbers had missing zeros which was
hidden by odd alignments, fix both these issues.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://lore.kernel.org/r/20240828172956.26630-3-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although
not used currently by the Linux FSS driver, these regions belong to
the FSS and should be included in the ranges mapping.
While here, a couple of these numbers had missing zeros which was
hidden by odd alignments, fix both these issues.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://lore.kernel.org/r/20240828172956.26630-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
USB on AM64 is the same peripheral as on J721E. It has a specific
compatible for potential integration details. Express this
relationship, matching what the dt-bindings indicate.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240726-s2r-cdns-v5-12-8664bfb032ac@bootlin.com
Signed-off-by: Nishanth Menon <nm@ti.com>
ADP5585 is found on i.MX93 11x11 EVK base board as a GPIO expander
and a PWM controller. Build ADP5585 GPIO and PWM drivers as modules.
While at it, build ADP5585 MFD driver as a module because the GPIO
and PWM drivers depend on it.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is a fairly large number of bug fixes for Qualcomm platforms,
most of them addressing issues with the devicetree files for the
newly added Snapdragon X1 based laptops to make them more reliable.
The Qualcomm driver changes address a few build-time issues as well
as runtime problems in the tzmem and scm firmware, the USB Type-C
driver, and the cmd-db and pmic_glink soc drivers.
The NXP i.MX usually gets a bunch of devicetree fixes that is proportional
to the number of supported machines. This includes both warning fixes
and correctness for the 64-bit i.MX9, i.MX8 and layerscape platforms,
as well as a single fix for a 32-bit i.MX6 based board.
The other changes are the usual minor changes, including an update to the
MAINTAINERS file, an omap3 dts file and a SoC driver for mpfs (risc-v).
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbSNOgACgkQYKtH/8kJ
UieuWg//eW9qg16Fw7ZeEDSrq7s7Mrr03zcF+Xqb1wpZZqDbUqgSWqaDDapd//bW
st7eR2rxm5yySBRbYFNa/jjB7YQA1GSlYtFn3cBEe/lFiuhOeP5yWwKTT05yeWDr
RzkPSDIt30YDsYV6+k5HpyzRNeuOd7QaVOz9XKqnEgzuRKC89OcSkHmXQUhvvbrg
f+5/uSFTZBAYjUpuH3ZRX9elRYsHSYlsmLI71HWRIBZrvNWwv3O4N0nySbCdhE0V
8hb3fCo/39rdjWjKuGHigsvxMLLmooFNvu/r/oZtqUjFDIjOkVzxI14K/yl2al7v
nmEHnwFqTsTIGP21CmRV4fzrS/80gld3ieLavC9kZaWqfV9yMjF1+jg40qsrUXcR
/Gfzq7XCrqx9CpFA62uytjkQZI5tk9Ip9FQHK80+OsDq8/zCJs77NIwR26VNT3O/
HIf9yTdC4bzZW1hUpTsIy+/piSWja5kkSKHn5Zcqby05hPUjWe/utiBKW3lTE9OI
EJ4swrHOenGea0AEeR2Rp5WOVfq26q12m4GYCi5YM+FGr64KHf5URQ1GoRTxorAx
YLa8xGm88CfIU3rnW90b2/5lYgqAyL3xEq9p1qt9HmZx/0SuoGbV1EekgfPd52yV
hrkn2gnNGS+A2ldqSRGZVJQSxKIpISORDj4y3sAI+JEQmm0UEM0=
=tK5m
-----END PGP SIGNATURE-----
Merge tag 'arm-fixes-6.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"There is a fairly large number of bug fixes for Qualcomm platforms,
most of them addressing issues with the devicetree files for the newly
added Snapdragon X1 based laptops to make them more reliable.
The Qualcomm driver changes address a few build-time issues as well as
runtime problems in the tzmem and scm firmware, the USB Type-C driver,
and the cmd-db and pmic_glink soc drivers.
The NXP i.MX usually gets a bunch of devicetree fixes that is
proportional to the number of supported machines. This includes both
warning fixes and correctness for the 64-bit i.MX9, i.MX8 and
layerscape platforms, as well as a single fix for a 32-bit i.MX6 based
board.
The other changes are the usual minor changes, including an update to
the MAINTAINERS file, an omap3 dts file and a SoC driver for mpfs
(risc-v)"
* tag 'arm-fixes-6.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (50 commits)
firmware: microchip: fix incorrect error report of programming:timeout on success
soc: qcom: pd-mapper: Fix singleton refcount
firmware: qcom: tzmem: disable sdm670 platform
soc: qcom: pmic_glink: Actually communicate when remote goes down
usb: typec: ucsi: Move unregister out of atomic section
soc: qcom: pmic_glink: Fix race during initialization
firmware: qcom: qseecom: remove unused functions
firmware: qcom: tzmem: fix virtual-to-physical address conversion
firmware: qcom: scm: Mark get_wq_ctx() as atomic call
arm64: dts: qcom: x1e80100: Fix Adreno SMMU global interrupt
arm64: dts: qcom: disable GPU on x1e80100 by default
arm64: dts: imx8mm-phygate: fix typo pinctrcl-0
arm64: dts: imx95: correct L3Cache cache-sets
arm64: dts: imx95: correct a55 power-domains
arm64: dts: freescale: imx93-tqma9352-mba93xxla: fix typo
arm64: dts: freescale: imx93-tqma9352: fix CMA alloc-ranges
ARM: dts: imx6dl-yapp43: Increase LED current to match the yapp4 HW design
arm64: dts: imx93: update default value for snps,clk-csr
arm64: dts: freescale: tqma9352: Fix watchdog reset
arm64: dts: imx8mp-beacon-kit: Fix Stereo Audio on WM8962
...
The actual PHY used by MDSS DP2 is the USB SS2 QMP one. So switch to it
instead. This is needed to get external DP support on boards like CRD
where the 3rd Type-C USB port (right-hand side) is connected to DP2.
Fixes: 1940c25eaa ("arm64: dts: qcom: x1e80100: Add display nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240829-x1e80100-dts-dp2-use-qmpphy-ss2-v1-1-9ba3dca61ccc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
All three USB SS combo QMP PHYs need to power off, deinit, then init and
power on again on every plug in event. This is done by forwarding the
orientation from the retimer/mux to the PHY. All is needed is the
orientation-switch property in each such PHY devicetree node. So add
them.
Fixes: 4af46b7bd6 ("arm64: dts: qcom: x1e80100: Add USB nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240829-x1e80100-combo-qmpphys-add-orientation-switch-v1-1-5c61ea1794da@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Confidential Computing environments such as pKVM and Arm's CCA
distinguish between shared (i.e. emulated) and private (i.e. assigned)
MMIO regions.
Introduce a hook into our implementation of ioremap_prot() so that MMIO
regions can be shared if necessary.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240830130150.8568-6-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Implementing the internal mem_encrypt API for arm64 depends entirely on
the Confidential Computing environment in which the kernel is running.
Introduce a simple dispatcher so that backend hooks can be registered
depending upon the environment in which the kernel finds itself.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240830130150.8568-4-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Implement a pKVM protected guest driver to probe the presence of pKVM
and determine the memory protection granule using the HYP_MEMINFO
hypercall.
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240830130150.8568-3-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
arm64 will soon require its own callback to initialise services
that are only available on this architecture. Introduce a hook
that can be overloaded by the architecture.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240830130150.8568-2-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
The ampere1a cpu is affected by erratum AC04_CPU_10 which is the same
bug as AC03_CPU_38. Add ampere1a to the AC03_CPU_38 workaround midr list.
Cc: <stable@vger.kernel.org>
Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
Acked-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827211701.2216719-1-scott@os.amperecomputing.com
Signed-off-by: Will Deacon <will@kernel.org>
Handling FEAT_ATS1A (which provides the AT S1E{1,2}A instructions)
is pretty easy, as it is just the usual AT without the permission
check.
This basically amounts to plumbing the instructions in the various
dispatch tables, and handling FEAT_ATS1A being disabled in the
ID registers.
Signed-off-by: Marc Zyngier <maz@kernel.org>
FEAT_PAN3 added a check for executable permissions to FEAT_PAN2.
Add the required SCTLR_ELx.EPAN and descriptor checks to handle
this correctly.
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
In order to plug the brokenness of our current AT implementation,
we need a SW walker that is going to... err.. walk the S1 tables
and tell us what it finds.
Of course, it builds on top of our S2 walker, and share similar
concepts. The beauty of it is that since it uses kvm_read_guest(),
it is able to bring back pages that have been otherwise evicted.
This is then plugged in the two AT S1 emulation functions as
a "slow path" fallback. I'm not sure it is that slow, but hey.
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
On the face of it, AT S12E{0,1}{R,W} is pretty simple. It is the
combination of AT S1E{0,1}{R,W}, followed by an extra S2 walk.
However, there is a great deal of complexity coming from combining
the S1 and S2 attributes to report something consistent in PAR_EL1.
This is an absolute mine field, and I have a splitting headache.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Similar to our AT S1E{0,1} emulation, we implement the AT S1E2
handling.
This emulation of course suffers from the same problems, but is
somehow simpler due to the lack of PAN2 and the fact that we are
guaranteed to execute it from the correct context.
Co-developed-by: Jintack Lim <jintack.lim@linaro.org>
Signed-off-by: Jintack Lim <jintack.lim@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Building on top of our primitive AT S1E{0,1}{R,W} emulation,
add minimal support for the FEAT_PAN2 instructions, momentary
context-switching PSTATE.PAN so that it takes effect in the
context of the guest.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Emulating AT instructions is one the tasks devolved to the host
hypervisor when NV is on.
Here, we take the basic approach of emulating AT S1E{0,1}{R,W}
using the AT instructions themselves. While this mostly work,
it doesn't *always* work:
- S1 page tables can be swapped out
- shadow S2 can be incomplete and not contain mappings for
the S1 page tables
We are not trying to handle these case here, and defer it to
a later patch. Suitable comments indicate where we are in dire
need of better handling.
Co-developed-by: Jintack Lim <jintack.lim@linaro.org>
Signed-off-by: Jintack Lim <jintack.lim@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
If our guest has been configured without PAN2, make sure that
AT S1E1{R,W}P will generate an UNDEF.
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
The upper_attr attribute has been badly named, as it most of the
time carries the full "last walked descriptor".
Rename it to "desc" and make ti contain the full 64bit descriptor.
This will be used by the S1 PTW.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Despite KVM not using the contiguous bit for anything related to
TLBs, the spec does require that the alignment defined by the
contiguous bit for the page size and the level is enforced.
Add the required checks to offset the point where PA and VA merge.
Fixes: 61e30b9eef ("KVM: arm64: nv: Implement nested Stage-2 page table walk logic")
Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Although we have helpers that encode the level of a given fault
type, the Address Size fault type is missing it.
While we're at it, fix the bracketting for ESR_ELx_FSC_ACCESS_L()
and ESR_ELx_FSC_PERM_L().
Signed-off-by: Marc Zyngier <maz@kernel.org>
Although we already have the primitives to set PSTATE.PAN with an
immediate, we don't have a way to read the current state nor set
it ot an arbitrary value (i.e. we can generally save/restore it).
Thankfully, all that is missing for this is the definition for
the PAN pseudo system register, here named SYS_PSTATE_PAN.
Signed-off-by: Marc Zyngier <maz@kernel.org>
As KVM is about to grow a full emulation for the AT instructions,
add the layout of the PAR_EL1 register in its non-D128 configuration.
Note that the constants are a bit ugly, as the register has two
layouts, based on the state of the F bit.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Although Linux doesn't make use of hierarchical permissions (TFFT!),
KVM needs to know where the various bits related to this feature
live in the TCR_ELx registers as well as in the page tables.
Add the missing bits.
Signed-off-by: Marc Zyngier <maz@kernel.org>
To allow using newer instructions that current assemblers don't know about,
replace the `at` instruction with the underlying SYS instruction.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Add Amlogic C3 C308L AW419 board. The corresponding binding
has been applied, therefore, this series does not need to
add a binding corresponding to the AW419 board.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240830-c3_add_node-v4-3-b56c0511e9dc@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Add some device nodes for SoC C3, including periphs clock controller
node, PLL clock controller node, SPICC node, regulator node, NAND
controller node, sdcard node, Ethernet MAC and PHY node.
The sdacrd depends on regulator and pinctrl(select), so some
property fields are placed at the board level. The nand chip
is placed on the board, So some property fields about SPIFC
and NAND controller node are placed at the board level.
THe Ethernet MAC support outchip PHY, so place this property
field(select PHY) at the board level.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240830-c3_add_node-v4-2-b56c0511e9dc@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
vcc3v3-sd-s0-regulator used enable-active-low. According the binding
of the fixed regulator, that is the assumed mode of operation if
enable-active-high is not specified. So this is property is not part
of the binding, therefore remove it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240829132100.1723127-4-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A remant from moving from the vendor kernel, the regulator is using
a fairchild fcs prefix instead of rockchip,* in the mainline kernel
according to its binding.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240829132100.1723127-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Build the Tegra194 PCIe Endpoint driver as a module by default for
ARM64.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
One of the key differences between p3701-0000 and p3701-0008 is the
temperature range. Add this info for p3701-0008.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
All SKUs of the p3701 module contain a temp sensor connected to the
BPMP I2C. Move the associated nodes from tegra234-p3701-0008.dtsi
to tegra234-p3701.dtsi. Add missing compatible.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some padctl supply nodes currently reside in board file, when they
should reside on module level. The nodes are part of module,
not board. Move these nodes to the correct AGX Orin
module file.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some of the nodes inside the AGX Orin module file are in the
wrong location. In particular, the SD card interface and
two of the PCIe regulators in the module file should instead
reside in the board file. These components are not part of the
module. They are part of the carrier board. Move these
nodes to the correct location.
Fixes: cd42b26a52 ("arm64: tegra: Add regulators required for PCIe")
Fixes: d71b893a11 ("arm64: tegra: Add Tegra234 SDMMC1 device tree node")
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Current IGX Orin structure has both a top-level module+board
file as well as a board file. Most of the data in the board-file
is closely related to the module itself. The benefit of this
extra file is outweighed by the additional complexity. Merge
the board file into the module+board file for simplicity.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The current AGX Orin structure has both a top-level module+board
file as well as a board file. Most of the data in the board-file
is closely related to the module itself. The benefit of this
extra file is outweighed by the additional complexity. Merge
the board file into the module+board file for simplicity.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AGX Orin module boards contain common nodes that can
be moved to the included module dtsi. This eliminates
redundancy within the files and reduces lines of code.
Data from tegra234-p3701-0000 and tegra234-p3701-0008 that
is common is now in tegra234-p3701.dtsi.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
P2180 modules have WiFi in form of BCM4354 chip, and kernel driver
supports this one, so enable it for all users. The necessary calibration
file can be obtained from Jetson Linux Archive. nvram.txt file is
located in "Driver Package (BSP)" in
nv_tegra/l4t_deb_packages/nvidia-l4t-firmware_<version>_arm64.deb
archive. The rest of necessary blobs can be obtained from official
Linux Firmware repository or (newer ones) from Infineon
ifx-linux-firmware repository (look in older releases).
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
P2180 modules have Bluetooth in form of BCM4354 chip, and kernel driver
supports this one, so enable it for all users. The necessary firmware
can be obtained from Jetson Linux Archive. bcm4354.hcd file is located
in "Driver Package (BSP)" in
nv_tegra/l4t_deb_packages/nvidia-l4t-firmware_<version>_arm64.deb
archive.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
One INA3221 sensor is located on P2180 module and the other two are on
P2597 base board.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add implementation details for Orin NX/Nano PCIe EP on C4.
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add PCIe C4 EP controller definition in device tree for Tegra234
devices.
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the definition for the wp-gpio of the P2597's external card slot,
enabling this functionality.
Tested on a P2597 board.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The current declaration is off-by-one and actually corresponds to the
wp-gpio of the external slot.
Tested on a P2597 board.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
FriendlyELEC NanoPC-T6 has optional SPI flash chip on-board.
It is populated with 32MB one on LTS version.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-5-edff247e8c02@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In the LTS (2310) version the miniPCIe slot got removed and USB 2.0
setup has changed. There are two external accessible ports and two ports
on the internal header.
There is an on-board USB hub which provides:
- one external connector (bottom one)
- two internal ports on pin header
- one port for m.2 E connector
The top USB 2.0 connector comes directly from the SoC.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-4-edff247e8c02@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
FriendlyELEC introduced a second version of NanoPC-T6 SBC.
Create common include file and make NanoPC-T6 use it. Following
patches will add LTS version.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-2-edff247e8c02@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RK3588 VO0 and VO1 GRFs are not identical (though quite similar in terms
of layout) and, therefore, incorrectly shared the compatible string.
Since the related binding document has been updated to use dedicated
strings, update the compatibles for vo{0,1}_grf DT nodes accordingly.
Additionally, for consistency, set the full region size (16KB) for
VO1_GRF.
Reported-by: Conor Dooley <conor@kernel.org>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240828-rk3588-vo-grf-compat-v2-2-4db2f791593f@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable the Display Unit and link with the HDMI add-on board connected
to the parallel connector on the RZ/G2UL SMARC EVK by using a Device
Tree overlay.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240826101648.176647-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Enable HDMI audio on the RZ/G2LC SMARC EVK. Set SW 1.5 on the SoM
module to the OFF position to turn on HDMI audio.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240826090803.56176-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On X1E the GPU node is disabled by default, to be enabled in the
individual devices once the developers install the required firmware.
The generic EDP panel driver used on the X1E CRD is replaced with the
Samsung ATNA45AF01 driver, in order to ensure backlight is brought back
up after being turned off.
The pin configuration for PCIe-related pins are corrected across all the
X1E targets. The PCIe controllers gain a minimum OPP vote, and PCIe
domain numbers are corrected.
WiFi calibration variant information is added to the Lenovo Yoga Slim
7x, to pick the right data from the firmware packages.
The incorrect Adreno SMMU global interrupt is corrected.
For IPQ5332, the IRQ triggers for the USB controller are corrected.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmbMnc4VHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FTmEQANIITSDMgMOy6NIqXiCeejSl0wKz
/aJhJK9iot+dYzcXZfswNxKDstYB3MJ0TIQMKw0uGZ7dyQS+InpD/+PAR1CX4dPz
yEpdWvvMDbnVp3IkkvtLjdBCS2Ri11j9ybheGuQWml8/lZs+YzzHObybygNAkKbj
3w6CiPU4lNSXw0bLkxxldC7Dl3UYAWPVtp3sye31ybS8WMLED1N0ANYVheCV/8YT
lFPVrFHW+nI+2iyvEg5lIHu+eprgk3a7u32XCm9RE68NTRxCsEkLlgc0r9mbhqMk
i/bKN96In/W4mt15SzOj+/wK1SGKCIgeZhYnkZe86NqvBfojvSvwfzbZhM8VveAM
aiUpJ9gRm/1QBZt3V84OkdX3w4+RZKpKfEmk9yMMEcHmrhv039lF8PJEEBYPbsIA
8WAaPQ3iauSz5tz4fhObHwAqSnBMvxV5/5HouRyHJfOBjh6Ui7zieVc0RtVhudsd
6d8P/UdDFOeK2LnOdgniPUVvWAMVM2XsFELmjUb9jRDpi3pd4t+Owvbozg6W2SaD
ChVDyAeGVSBlqHBsYX/OvwuXFx/GLj+zo49noFD2Ci/qoxGIy40au9miSwFzMa4K
BV/wl6Hi+urlvv89MPJi/CDptYc75tr8Dui9DbWMaYP4g3b02Zej0OP+oJqyx0ZT
BRHaDLySwJnAC/v5
=ymuZ
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbPiGEACgkQYKtH/8kJ
Uid/RxAA39/ZFMx6QEzhA0KAv4xEm73UDsPV8ozB+5asDeDuht1UHq4nwRSmFJaE
4gy+zMipHl8kMvnYBZv1S7rNJ1D27wKOkGBTJrIznB/UBLPxkFJZnjAy8kMWuu9l
/Z6X1Fqf8hkxTNet+70y8j2LCQbhyxBd77SvpHiLjHdxs+JH7Vtl7OHbk6+XXDzj
OxJu6Iy7CbS4mGqx5pYpOnnl0g9WE1gNEabmH1kSa+aW1nU2fjGVr9gCu1h4tb/D
vD1xb8laNs2FmP+HpcootlWWgD0wzU0u1WU5qBzen1B/qm0WyEp/xyUTvM4EiSeN
qb3obRx8EbASmcXUtUIfPR9Sz774Gx3J740V7J7ZikxvUnr2cImC955hZzP8U60b
+qiTmiFoqTXt5eb4H+w0aB28z4h5hizT9uV50u1K1awdZIP72IucPqfNkvu95MIR
0C/GZraDQl6j0XJocaXp4nSLk09Vo6uejXMCYGeHIm1CgEOwBiezrPy9BQ96an+E
9Efh+5NLm+qXicFqBdTkJ2q06Qkqv5i+rTXcVDdm2VQScn9/u/FdEktIV3C/20Hp
mpGG1BVoWcGNFeldF/65R7uRDzX0zXJnn3nXWTKM16d2YqhAd55i9cHjqMZOZqrc
Rg5DTbjRkwS7c+rBOSxmGOx9PpcUYuUeRKyGGCs6z2/2KYmB4ME=
=oFQA
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
Qualcomm Arm64 DeviceTree fixes for v6.11
On X1E the GPU node is disabled by default, to be enabled in the
individual devices once the developers install the required firmware.
The generic EDP panel driver used on the X1E CRD is replaced with the
Samsung ATNA45AF01 driver, in order to ensure backlight is brought back
up after being turned off.
The pin configuration for PCIe-related pins are corrected across all the
X1E targets. The PCIe controllers gain a minimum OPP vote, and PCIe
domain numbers are corrected.
WiFi calibration variant information is added to the Lenovo Yoga Slim
7x, to pick the right data from the firmware packages.
The incorrect Adreno SMMU global interrupt is corrected.
For IPQ5332, the IRQ triggers for the USB controller are corrected.
* tag 'qcom-arm64-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits)
arm64: dts: qcom: x1e80100: Fix Adreno SMMU global interrupt
arm64: dts: qcom: disable GPU on x1e80100 by default
arm64: dts: qcom: x1e80100-crd: Fix backlight
arm64: dts: qcom: x1e80100-yoga-slim7x: fix missing PCIe4 gpios
arm64: dts: qcom: x1e80100-yoga-slim7x: disable PCIe6a perst pull down
arm64: dts: qcom: x1e80100-yoga-slim7x: fix up PCIe6a pinctrl node
arm64: dts: qcom: x1e80100-yoga-slim7x: fix PCIe4 PHY supply
arm64: dts: qcom: x1e80100-vivobook-s15: fix missing PCIe4 gpios
arm64: dts: qcom: x1e80100-vivobook-s15: disable PCIe6a perst pull down
arm64: dts: qcom: x1e80100-vivobook-s15: fix up PCIe6a pinctrl node
arm64: dts: qcom: x1e80100-vivobook-s15: fix PCIe4 PHY supply
arm64: dts: qcom: x1e80100-qcp: fix missing PCIe4 gpios
arm64: dts: qcom: x1e80100-qcp: disable PCIe6a perst pull down
arm64: dts: qcom: x1e80100-qcp: fix up PCIe6a pinctrl node
arm64: dts: qcom: x1e80100-qcp: fix PCIe4 PHY supply
arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios
arm64: dts: qcom: x1e80100-crd: disable PCIe6a perst pull down
arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node
arm64: dts: qcom: x1e80100: add missing PCIe minimum OPP
arm64: dts: qcom: x1e80100: fix PCIe domain numbers
...
Link: https://lore.kernel.org/r/20240826152426.1648383-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the Samsung ATNA33XC20 display panel driver, as we switched from
the generic EDP panel for some of the X1E devices in v6.11.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmbMl8AVHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3F6EcP/36z5R0RyFBhf85g5P1WUlli/SPX
byA2XLNqHbhqhwu9Ao5x/QQw9e/hM7yOvMoPlzKdbR1On3o9VSYij22eKExg4KTK
omh35mQC5UX4wUeECRZdWBsPaGzK7t+LVkeDhGlrfHsnOYO/sL63WMxSf+pi/3GT
RuyfKLP5CiCmjqoE3zAwWUEFS+50UhEPt2sk4E8gEeA0XBLi44agaQHfDYC6COlX
A18qgMqZ7NSYsgp1ctTJ8kFklLfTd5c4H/rUkJpkttPti6o/NzeCKmRzwKb/1Ih+
/vrvypk/TFNHdnMqp7LNN7zKb9cAEf+LS4DHuyrwqL+PtdUuOfbJr3Fad6vn/fJi
e2e2bKZRG7ShgVocU13nGXUjPrjKPir+NUZPuWycCNr/IJ4HxVOaB+ZsO17wVeo2
FdxM6tPUIJ0RSi96RCRX+roY9tqPykrYZEdN4gS80eIjzyUwbAkYlb8K5wmSrgMQ
8lcEiyvIpE6ZcfQMdkwU59hIpLJUaA/FuGpZUH4aJPTxmWiHHgPoSc4d2x7eobvR
l08+H3IhPOvYML3cVmdFuPlHg0ePKG/FWCuOm24WYPgpTrc94siOdGRPsavv0iLj
lafdN6j8Xs5VqNj1KADlut2m9+5PVpZO4YJpVOOZlGyhoV/GKdXtC5FYlZjTUX8q
fq9uqaUIsFqN68xM
=Wl9S
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbPiFEACgkQYKtH/8kJ
UifDsw/9EU0lymxO5TbSvAGrJO9qM0W6ZSFttDrBwx22W+687NUz5UaMd5VOS2q+
kPkj8Jekxz9mk2NV2+g/MIRf0DHEjsYhOkX59w62ZBwIGw68DHc4BpE6ISlK83/Z
Z7wa0xEoiA7dagz4ik+hgkIcWg5TwdCK4SpuQdZ2LlsB22Ib7yQ7jcTFOxWcaJps
K22DyjF1usYeY1Uc35hViA4j189JhB7ZDa31I9nO6HgWfBB7UG8j04Wd+PcudgBR
WMCFGxRzTkO3/OvrfaEBF+NXHRYwQskqKeoMGb81DoIJauS45dCKUdVdtrNZ8Ogu
5h/sIWLiDYt+JUZDOSQpIS20FPZLVSrjMAbRi8QkDFrdySgkfGhPThPHzy4NzFv5
2mi1Onu93S5epNVeCHlxvAniw8SB1ugWvgH3aXKhgN/2WDdEAcB6l9V3LX2mhBlP
ekKGjpH4SkmYsEKFMVIYuPkE0LxXGOEMYMfJheLAk9p+x0DD1TdqubZ9xAiMVsSU
uwIPFTtuF9tIHwLVVXR70jfbSoVU1UCdbL/23lPnBFZuD6DDBs7h7Dyy+PU525Ml
7vX/IPGf+RCSdnAr+rm82YvPpojTWTjaU5F8awodreYjeJkuBw/zU88EtTjViEev
bTwQs4g+YcqzuHo+xX8XUDOv4gM2nvyIvUZlbra7jqMhglJE2kI=
=qe2j
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-defconfig-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
Qualcomm Arm64 defconfig fix for 6.11
Enable the Samsung ATNA33XC20 display panel driver, as we switched from
the generic EDP panel for some of the X1E devices in v6.11.
* tag 'qcom-arm64-defconfig-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Add CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20
Link: https://lore.kernel.org/r/20240826145736.1646729-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- One imx8mp-beacon-kit change from Adam Ford to fix the broken WM8962
audio support
- One pinctrl property typo fix for imx8mm-phygate
- One layerscape fix from Krzysztof Kozlowski to get thermal nodes
correct name length
- A couple of imx93-tqma9352 fixes from Markus Niebel, one on CMA
alloc-ranges and the other on SD-Card cd-gpios typo
- One change from Michal Vokáč to fix imx6dl-yapp43 LED current to match
the HW design
- A couple of imx95 fixes from Peng Fan, one to correct a55 power
domains and the other to correct L3Cache cache-sets
- One tqma9352 watchdog reset fix from Sascha Hauer
- One imx93 change from Shenwei Wang to fix the default value for STMMAC
EQOS snps,clk-csr
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAma7a9EUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM4FFAf/RVBrDLv5/Bj6IJl6gJSGw31l6mz/
gb3uCDbSF7JxNrGCbTz5IcDJmDJnDrg68m+UiNS3vwq0tXd3rN2MXy55bxE0XA7n
4drzyFuV0Cuqpr8snAgxzvX5F4w+vT1z9vk5fDxY5YAvxGbtYFMYnanE6w2Fs2g+
2nVxChCWlAqHEfO5E/hQKZzMtjU/ATKHZMqOG1ZFypoyBuO96GTDNMoYlZrfYiRh
7alnxUnvMNJ2UX0OC9SLb3CVAtt9lxGKT5KEps2LSeiRw1dQ8KdTpjreIkoh7mMh
MDHiHORgO5VAyOLPv/jUb23q9KzT3HSqpl/TMtG34pvHb7E9YODRZLwGCg==
=Tzc4
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbPiDEACgkQYKtH/8kJ
Uies+g/7BmPr1bujROQO0C9dmn/B9gCMsE+sajpltVUpVdFWlSbxHs2HTbyElsQc
Wxo1KsBxs3dtm71tp4NNMuiyrUjPaGgoEPNmEd8O5Jfu7fnpl+OwpxaqnyLKAmUA
iCHUuRLNQx8Ilz0LUxKkeovCOT2d+T4EzawRqLdNs4ioHsUuumiqbyBbR1XtzaCW
CyHKQLmthIZeZTPzpyEM7+D+zt/SrF0FnI+c4p0gixnl2hDmCtrxI9qwtuSuw+ca
5Bj85KTUSyR3drKgJ0peKmDxMamfyRaAKU1B5XzAD/IfUie/SsSi+M59NGS+3pVo
l1rA/iUcDwzEE2e1u/7/jTK4zwdFWjUvG4rhrgAypSsijMem2qiLGOWKnkVz2DOx
LjDcL4i1sapTAramGzbfrn6Ky+ZMQEOYskRAGTT4G9QP7meaqiQ7dn60/7oLPzK4
ktdYnrGqw9INfAUIfOlae7n89M89URU3T4rt7AbyE0oFOiTjUa4xAFkk+IDltcH0
9E+VY5XMixJhXVloKjdXo2xRDFZRusgB/gIJrBxql1++Sp1QyraAR/f4s9zyOhql
9C1zLi/QArfgKKJZbEYSldHxkkwedEfwVL6IGUcPEpgppXVzTp5e+EKh0Rp7QsIT
ME7Mb9+ipVtKhQLuX8OyBRc71zmt1UWUU28/6X+nUBoSioXg+IQ=
=gOQs
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 6.11:
- One imx8mp-beacon-kit change from Adam Ford to fix the broken WM8962
audio support
- One pinctrl property typo fix for imx8mm-phygate
- One layerscape fix from Krzysztof Kozlowski to get thermal nodes
correct name length
- A couple of imx93-tqma9352 fixes from Markus Niebel, one on CMA
alloc-ranges and the other on SD-Card cd-gpios typo
- One change from Michal Vokáč to fix imx6dl-yapp43 LED current to match
the HW design
- A couple of imx95 fixes from Peng Fan, one to correct a55 power
domains and the other to correct L3Cache cache-sets
- One tqma9352 watchdog reset fix from Sascha Hauer
- One imx93 change from Shenwei Wang to fix the default value for STMMAC
EQOS snps,clk-csr
* tag 'imx-fixes-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mm-phygate: fix typo pinctrcl-0
arm64: dts: imx95: correct L3Cache cache-sets
arm64: dts: imx95: correct a55 power-domains
arm64: dts: freescale: imx93-tqma9352-mba93xxla: fix typo
arm64: dts: freescale: imx93-tqma9352: fix CMA alloc-ranges
ARM: dts: imx6dl-yapp43: Increase LED current to match the yapp4 HW design
arm64: dts: imx93: update default value for snps,clk-csr
arm64: dts: freescale: tqma9352: Fix watchdog reset
arm64: dts: imx8mp-beacon-kit: Fix Stereo Audio on WM8962
arm64: dts: layerscape: fix thermal node names length
Link: https://lore.kernel.org/r/ZrtsTO1+jXhJ6GSM@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds node for E5010 JPEG Encoder which is a stateful JPEG Encoder
present in AM62A SoC [1], supporting baseline encoding of semiplanar based
YUV420 and YUV422 raw video formats to JPEG encoding, with resolutions
supported from 64x64 to 8kx8k.
E5010 JPEG Encoder IP is present in main domain, so this also adds address
range for core and mmu regions of E5010 IP in cbass_main node.
Link: https://www.ti.com/lit/pdf/spruj16 [1]
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20240826162250.380005-2-devarsht@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
CAN instances 0 and 1 in the mcu domain and 0 in the main domain are
brought on the evm through headers J5, J8 and J10 respectively. Thus,
add their respective transceiver's 0, 1 and 2 dt nodes as well as
add the required pinmux to add support for these CAN instances.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Judith Mendez <jm@ti.com>
Link: https://lore.kernel.org/r/20240827105644.575862-2-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
System firmware uses main_uart5 in J722S EVM for trace data.
Thus, describe it in device tree for completeness,
adding the pinmux and mark it as reserved.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20240827105644.575862-3-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
wkup_uart0 is a reserved node that is used by Device Manager firmware.
Only TX and RX pins are required for the firmware and enabling pinctrl
for CTS and RTS breaks the wakeup functionality of wkup_uart0. Drop the
conflicting muxes.
Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20240826-am62p-v1-1-b713b48628d1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain
use timers. Therefore, change the status of the timer nodes to
"reserved" to avoid any clash. Usage is described as below:
+===================+=============+
| Remoteproc node | Timer Node |
+===================+=============+
| main_r5fss0_core0 | main_timer2 |
+-------------------+-------------+
| main_r5fss0_core1 | main_timer3 |
+-------------------+-------------+
| main_r5fss1_core0 | main_timer4 |
+-------------------+-------------+
| main_r5fss1_core1 | main_timer5 |
+-------------------+-------------+
| c71_0 | main_timer0 |
+-------------------+-------------+
| c71_1 | main_timer1 |
+-------------------+-------------+
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826104821.1516344-6-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain
use timers. Therefore, change the status of the timer nodes to
"reserved" to avoid any clash. Usage is described as below:
+===================+=============+
| Remoteproc node | Timer Node |
+===================+=============+
| main_r5fss0_core0 | main_timer2 |
+-------------------+-------------+
| main_r5fss0_core1 | main_timer3 |
+-------------------+-------------+
| main_r5fss1_core0 | main_timer4 |
+-------------------+-------------+
| main_r5fss1_core1 | main_timer5 |
+-------------------+-------------+
| c71_0 | main_timer0 |
+-------------------+-------------+
| c71_1 | main_timer1 |
+-------------------+-------------+
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826104821.1516344-5-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain
use timers. Therefore, change the status of the timer nodes to
"reserved" to avoid any clash. Usage is described as below:
+===================+==============+
| Remoteproc node | Timer Node |
+===================+==============+
| main_r5fss0_core0 | main_timer12 |
+-------------------+--------------+
| main_r5fss0_core1 | main_timer13 |
+-------------------+--------------+
| main_r5fss1_core0 | main_timer14 |
+-------------------+--------------+
| main_r5fss1_core1 | main_timer15 |
+-------------------+--------------+
| c66_0 | main_timer0 |
+-------------------+--------------+
| c66_1 | main_timer1 |
+-------------------+--------------+
| c71_0 | main_timer2 |
+-------------------+--------------+
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826104821.1516344-4-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain
use timers. Therefore, change the status of the timer nodes to
"reserved" to avoid any clash. Usage is described as below:
+===================+==============+
| Remoteproc node | Timer Node |
+===================+==============+
| main_r5fss0_core0 | main_timer12 |
+-------------------+--------------+
| main_r5fss0_core1 | main_timer13 |
+-------------------+--------------+
| main_r5fss1_core0 | main_timer14 |
+-------------------+--------------+
| main_r5fss1_core1 | main_timer15 |
+-------------------+--------------+
| c66_0 | main_timer0 |
+-------------------+--------------+
| c66_1 | main_timer1 |
+-------------------+--------------+
| c71_0 | main_timer2 |
+-------------------+--------------+
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826104821.1516344-3-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The remoteproc firmware of R5F in the MAIN voltage domain use timers.
Therefore, change the status of the timer nodes to "reserved" to avoid
any clash. Usage is described as below:
+===================+==========================+
| Remoteproc node | Timer Node |
+===================+==========================+
| main_r5fss0_core0 | main_timer0, main_timer2 |
+-------------------+--------------------------+
| main_r5fss0_core1 | main_timer1 |
+-------------------+--------------------------+
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826104821.1516344-2-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
To allow firmware to pick up all DTs from here, move the overlays that
are normally applied during DT fixup to the kernel source as well. Hook
then into the build nevertheless to ensure that regular checks are
performed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/91f8b825467651ebd51a4051f153ab136eeb1849.1724830741.git.jan.kiszka@siemens.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The PG1 A variant of the iot2050 series has been identified which
partially lacks support for lock-step mode. This implies that all
iot2050 boards can't support this mode. As a result, lock-step mode has
been disabled across all iot2050 boards for consistency and to avoid
potential issues.
Signed-off-by: Li Hua Qian <huaqian.li@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/d1f5f84db7a1597cd29628a0b503e578367b7b40.1724830741.git.jan.kiszka@siemens.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The TI AM69 SK board has three R5F clusters in the MAIN domain, and all
of these are configured for LockStep mode at the moment. Switch all of
these R5F clusters to Split mode by default to maximize the number of
R5F cores.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826093024.1183540-8-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The TI J784S4 EVM board has three R5F clusters in the MAIN domain, and
all of these are configured for LockStep mode at the moment. Switch
all of these R5F clusters to Split mode by default to maximize the
number of R5F cores.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826093024.1183540-7-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The TI AM68 SK board has two R5F clusters in the MAIN domain, and both
of these are configured for LockStep mode at the moment. Switch both of
these R5F clusters to Split mode by default to maximize the number of
R5F cores.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826093024.1183540-6-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The TI J721S2 EVM board has two R5F clusters in the MAIN domain, and
both of these are configured for LockStep mode at the moment. Switch
both of these R5F clusters to Split mode by default to maximize the
number of R5F cores.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826093024.1183540-5-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The TI J721E SK board has two R5F clusters in the MAIN domain, and both
of these are configured for LockStep mode at the moment. Switch both of
these R5F clusters to Split mode by default to maximize the number of
R5F cores.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826093024.1183540-4-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The TI J721E EVM board has two R5F clusters in the MAIN domain, and
both of these are configured for LockStep mode at the moment. Switch
both of these R5F clusters to Split mode by default to maximize the
number of R5F cores.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826093024.1183540-3-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The TI J7200 EVM board has one R5F cluster in the MAIN domain, and it is
configured for LockStep mode at the moment. Switch the MAIN R5F cluster
to Split mode by default to maximize the number of R5F cores.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240826093024.1183540-2-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This enables E5010 JPEG Encoder which is a stateful JPEG Encoder present in
TI's AM62A SoC [1] and supporting baseline encoding of semiplanar based
YUV420 and YUV422 raw video formats to JPEG encoding, with resolutions
supported from 64x64 to 8kx8k resolution.
Link: https://www.ti.com/lit/pdf/spruj16 [1]
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20240826162250.380005-3-devarsht@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
External interfaces should be disabled at the SoC DTSI level, since
the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
and enable them in the board DTS. If the board DTS includes a SoM DTSI
that completes the node description, enable the Ethernet switch and
ports in SoM DTSI.
Reflect this change in SoM DTSIs by removing ethernet port disable.
Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Acked-by: Josua Mayer <josua@solid-run.com>
Link: https://lore.kernel.org/r/20240809135753.1186-1-logan.bristol@utexas.edu
Signed-off-by: Nishanth Menon <nm@ti.com>
assigned-clock sets DEV_RTIx_RTI_CLK(id:0) whereas clocks sets
DEV_RTIx_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT(id:1)[1]. This does not
look right, the timers in the driver assume a max frequency of 32kHz for
the heartbeat (HFOSC0 is 19.2MHz on j784s4-evm).
With this change, WDIOC_GETTIMELEFT return coherent time left
(DEFAULT_HEARTBEAT=60, reports 60s upon opening the cdev).
[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html#clocks-for-rti0-device
Fixes: caae599de8 ("arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances")
Suggested-by: Andrew Halaney <ahalaney@redhat.com>
Signed-off-by: Eric Chanudet <echanude@redhat.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20240805174330.2132717-2-echanude@redhat.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The DMA carveout for the C6x core 0 is at 0xa6000000 and core 1 is at
0xa7000000. These are reversed in DT. While both C6x can access either
region, so this is not normally a problem, but if we start restricting
the memory each core can access (such as with firewalls) the cores
accessing the regions for the wrong core will not work. Fix this here.
Fixes: fae14a1cb8 ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240801181232.55027-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The DMA carveout for the C6x core 0 is at 0xa6000000 and core 1 is at
0xa7000000. These are reversed in DT. While both C6x can access either
region, so this is not normally a problem, but if we start restricting
the memory each core can access (such as with firewalls) the cores
accessing the regions for the wrong core will not work. Fix this here.
Fixes: f46d16cf5b ("arm64: dts: ti: k3-j721e-sk: Add DDR carveout memory nodes")
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240801181232.55027-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The SoM board has reserved HDMI output, while the Radxa E25
is not connected. So disable the display subsystem only for
Radxa E25.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20240820120020.469375-1-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable pcie2x1l2 and related combphy/regulator routed to M.2 E key
connector on Radxa ROCK 5A.
Tested with Radxa Wireless Module A8:
$ lspci
0004:40:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01)
0004:41:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8852BE PCIe 802.11ax Wireless Network Controller
$ ip l
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: end0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
link/ether c2:58:fc:70:55:86 brd ff:ff:ff:ff:ff:ff
3: wlP4p65s0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 2c:05:47:65:5b:ed brd ff:ff:ff:ff:ff:ff
$ lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 001 Device 002: ID 1a40:0101 Terminus Technology Inc. Hub
Bus 001 Device 003: ID 0bda:b85b Realtek Semiconductor Corp. Bluetooth Radio
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 004 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 005 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 006 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 006 Device 002: ID 0789:0336 Logitec Corp. LMD USB Device
Bus 007 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 008 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
$ hciconfig
hci0: Type: Primary Bus: USB
BD Address: 2C:05:47:65:5B:EE ACL MTU: 1021:6 SCO MTU: 255:12
UP RUNNING
RX bytes:2698 acl:0 sco:0 events:329 errors:0
TX bytes:69393 acl:0 sco:0 commands:329 errors:0
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20240826080456.525-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There is no "on-board WLAN/BT chip" on Radxa ROCK 5A. remove related
properties.
Fixes: 1642bf66e2 ("arm64: dts: rockchip: add USB2 to rk3588s-rock5a")
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20240826075130.546-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Hardkernel ODROID-M1S is a single-board computer based on Rockchip
RK3566 SoC. It features e.g. 4/8 GB LPDDR4 RAM, 64 GB eMMC, SD-card,
GbE LAN, HDMI 2.0, M.2 NVMe and USB 2.0/3.0.
Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240827211825.1419820-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The vendor prefix for Hardkernel ODROID-M1 is incorrectly listed as
rockchip. Use the proper hardkernel vendor prefix for this board, while
at it also drop the redundant soc prefix.
Fixes: fd35832677 ("arm64: dts: rockchip: Add Hardkernel ODROID-M1 board")
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240827211825.1419820-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds the necessary device tree changes to enable analog audio
output for the 3.5 mm TRS headphone jack on the Radxa ROCK 4C+ with
its RK809 audio codec.
Signed-off-by: Jonathan Liu <net147@gmail.com>
Link: https://lore.kernel.org/r/20240828074755.1320692-1-net147@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
but can be used as a cluster (i.e. sharing work between the cores).
These cores are called VEPU121 in the TRM. The TRM describes one more
VEPU121, but that is combined with a Hantro H1. That one will be handled
using the VPU binding instead.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240827181206.147617-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The interrupt pin of the PHY is connected to the GPIO expander, configure
it accordingly.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove unused property num-viewport to fix dtbs warnings.
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dtb: pcie@3400000: Unevaluated properties are not allowed ('num-viewport' was unexpected)
from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dtb: pcie@3400000: Unevaluated properties are not allowed ('num-viewport' was unexpected)
from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
Cc: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
We currently have two helpers (undef_access() and trap_undef()) that
do exactly the same thing: inject an UNDEF and return 'false' (as an
indication that PC should not be incremented).
We definitely could do with one less. Given that undef_access() is
used 80ish times, while trap_undef() is only used 30 times, the
latter loses the battle and is immediately sacrificed.
We also have a large number of instances where undef_access() is
open-coded. Let's also convert those.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-11-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
We don't expect to trap any GICv3 register for host handling,
apart from ICC_SRE_EL1 and the SGI registers. If they trap,
that's because the guest is playing with us despite being
told it doesn't have a GICv3.
If it does, UNDEF is what it will get.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-10-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
On platforms that require emulation of the CPU interface, we still
need to honor the traps requested by the guest (ICH_HCR_EL2 as well
as the FGTs for ICC_IGRPEN{0,1}_EL1.
Check for these bits early and lail out if any trap applies.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-9-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
The usual song and dance. Anything that is a trap, any register
it traps. Note that we don't handle the registers added by
FEAT_NMI for now.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-8-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
As we are about to describe the trap routing for ICH_HCR_EL2, add
the register to the vcpu state in its VNCR form, as well as reset
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-7-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
In order to be consistent, we shouldn't advertise a GICv3 when none
is actually usable by the guest.
Wipe the feature when these conditions apply, and allow the field
to be written from userspace.
This now allows us to rewrite the kvm_has_gicv3 helper() in terms
of kvm_has_feat(), given that it is always evaluated at runtime.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-6-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
We already have to perform a set of last-chance adjustments for
NV purposes. We will soon have to do the same for the GIC, so
introduce a helper for that exact purpose.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-5-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
On a VHE system, no GICv3 traps get configured when no irqchip is
present. This is not quite matching the "no GICv3" semantics that
we want to present.
Force such traps to be configured in this case.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-4-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
We so far only write the ICH_HCR_EL2 config in two situations:
- when we need to emulate the GICv3 CPU interface due to HW bugs
- when we do direct injection, as the virtual CPU interface needs
to be enabled
This is all good. But it also means that we don't do anything special
when we emulate a GICv2, or that there is no GIC at all.
What happens in this case when the guest uses the GICv3 system
registers? The *guest* gets a trap for a sysreg access (EC=0x18)
while we'd really like it to get an UNDEF.
Fixing this is a bit involved:
- we need to set all the required trap bits (TC, TALL0, TALL1, TDIR)
- for these traps to take effect, we need to (counter-intuitively)
set ICC_SRE_EL1.SRE to 1 so that the above traps take priority.
Note that doesn't fully work when GICv2 emulation is enabled, as
we cannot set ICC_SRE_EL1.SRE to 1 (it breaks Group0 delivery as
IRQ).
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-3-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Follow the pattern introduced with vcpu_set_hcr(), and introduce
vcpu_set_ich_hcr(), which configures the GICv3 traps at the same
point.
This will allow future changes to introduce trap configuration on
a per-VM basis.
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827152517.3909653-2-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
* kvm-arm64/tlbi-fixes-6.12:
: .
: A couple of TLB invalidation fixes, only affecting pKVM
: out of tree, courtesy of Will Deacon.
: .
KVM: arm64: Ensure TLBI uses correct VMID after changing context
KVM: arm64: Invalidate EL1&0 TLB entries for all VMIDs in nvhe hyp init
Signed-off-by: Marc Zyngier <maz@kernel.org>
The power-sensors are located on the carrier board and not the
module board and so update the IGX Orin device-tree files to fix this.
Fixes: 9152ed0930 ("arm64: tegra: Add power-sensors for Tegra234 boards")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch ensures that Orin NX and Orin Nano enable an identical
set of serial ports. UARTA/UARTE will be enabled by adding
respective nodes to the board dtsi file.
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Adding the missing dmas and dma-names properties which are required
for UARTA when using with the Tegra HSUART driver.
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The functions defined in arm64 for ACPI support are required
for RISC-V also. To avoid duplication, move these functions
to common location.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Will Deacon <will@kernel.org>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://patch.msgid.link/20240812005929.113499-2-sunilvl@ventanamicro.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
'struct kobj_type' is not modified. It is only used in kobject_init()
which takes a 'const struct kobj_type *ktype' parameter.
Constifying this structure moves some data to a read-only section,
so increase over all security.
On a x86_64, compiled with arm defconfig:
Before:
======
text data bss dec hex filename
5602 548 352 6502 1966 arch/arm64/kernel/cpuinfo.o
After:
======
text data bss dec hex filename
5650 500 352 6502 1966 arch/arm64/kernel/cpuinfo.o
Signed-off-by: Huang Xiaojia <huangxiaojia2@huawei.com>
Link: https://lore.kernel.org/r/20240826151250.3500302-1-huangxiaojia2@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
On arm64, this prctl controls access to CNTVCT_EL0, CNTVCTSS_EL0 and
CNTFRQ_EL0 via CNTKCTL_EL1.EL0VCTEN. Since this bit is also used to
implement various erratum workarounds, check whether the CPU needs
a workaround whenever we potentially need to change it.
This is needed for a correct implementation of non-instrumenting
record-replay debugging on arm64 (i.e. rr; https://rr-project.org/).
rr must trap and record any sources of non-determinism from the
userspace program's perspective so it can be replayed later. This
includes the results of syscalls as well as the results of access
to architected timers exposed directly to the program. This prctl
was originally added for x86 by commit 8fb402bccf ("generic, x86:
add prctl commands PR_GET_TSC and PR_SET_TSC"), and rr uses it to
trap RDTSC on x86 for the same reason.
We also considered exposing this as a PTRACE_EVENT. However, prctl
seems like a better choice for these reasons:
1) In general an in-process control seems more useful than an
out-of-process control, since anything that you would be able to
do with ptrace could also be done with prctl (tracer can inject a
call to the prctl and handle signal-delivery-stops), and it avoids
needing an additional process (which will complicate debugging
of the ptraced process since it cannot have more than one tracer,
and will be incompatible with ptrace_scope=3) in cases where that
is not otherwise necessary.
2) Consistency with x86_64. Note that on x86_64, RDTSC has been there
since the start, so it's the same situation as on arm64.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Link: https://linux-review.googlesource.com/id/I233a1867d1ccebe2933a347552e7eae862344421
Link: https://lore.kernel.org/r/20240824015415.488474-1-pcc@google.com
Signed-off-by: Will Deacon <will@kernel.org>
Everything is now in place for a guest to "enjoy" FP8 support.
Expose ID_AA64PFR2_EL1 to both userspace and guests, with the
explicit restriction of only being able to clear FPMR.
All other features (MTE* at the time of writing) are hidden
and not writable.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-9-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
If userspace has enabled FP8 support (by setting ID_AA64PFR2_EL1.FPMR
to 1), let's enable the feature by setting HCRX_EL2.EnFPM for the vcpu.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-8-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
ID_AA64FPFR0_EL1 contains all sort of bits that contain a description
of which FP8 subfeatures are implemented.
We don't really care about them, so let's just expose that register
and allow userspace to disable subfeatures at will.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-7-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
HCRX_EL2.EnFPM controls the trapping of FPMR (as well as the validity
of any FP8 instruction, but we don't really care about this last part).
Describe the trap bit so that the exception can be reinjected in a
NV guest.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-6-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Just like the rest of the FP/SIMD state, FPMR needs to be context
switched.
The only interesting thing here is that we need to treat the pKVM
part a bit differently, as the host FP state is never written back
to the vcpu thread, but instead stored locally and eagerly restored.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-5-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Just like SVCR, FPMR is currently stored at the wrong location.
Let's move it where it belongs.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-4-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
As we are about to check for the advertisement of FPMR support to
a guest in a number of places, add a predicate that will gate most
of the support code for FPMR.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-3-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
SVCR is just a system register, and has no purpose being outside
of the sysreg array. If anything, it only makes it more difficult
to eventually support SME one day. If ever.
Move it into the array with its little friends, and associate it
with a visibility predicate.
Although this is dead code, it at least paves the way for the
next set of FP-related extensions.
Reviewed-by: Mark Brown <broonie@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240820131802.3547589-2-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Add support for Surface Laptop 7 machines, based on X1E80100.
The feature status is mostly on par with other X Elite machines,
notably lacking:
- USB-A and probably USB-over-Surface-connector (pending NXP retimer
support)
- SD card reader (Realtek RTS5261 connected over PCIe)
- Touchscreen and touchpad support (hid-over-SPI [1])
- Audio (a quick look suggests the setup is very close to the one in
X1E CRD)
The two Surface Laptop 7 SKUs (13.8" and 15") only have very minor
differences, amounting close to none on the software side. Even the
MBN firmware files and ACPI tables are shared between the two machines.
With that in mind, support is added for both, although only the larger
one was physically tested. Display differences will be taken care of
through fused-in EDID and other matters should be solved within the
EC and boot firmware.
[1] https://www.microsoft.com/en-us/download/details.aspx?id=103325
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-5-c32ebae78789@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GENI SE2 within QUP0 is used as UART on some devices, describe it.
While at it, rewrite the adjacent UART21 pins node to make it more
easily modifiable.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-4-c32ebae78789@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable throttling down the CPU frequency when an alert temperature
threshold (lower than the critical threshold) is reached.
Signed-off-by: Alessandro Zini <alessandro.zini@siemens.com>
Link: https://lore.kernel.org/r/20240814214328.14155-1-alessandro.zini@siemens.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Commit ed07d82f9e ("arm64: dts: ti: k3-am62p-j722s: Move
SoC-specific node properties") introduced the main_gpio1 node
and included the ti,ngpio property, but did not include the
gpio-reserved-ranges property. As a result, the user could try
to access gpios that do not exist. Fix this by introducing the
gpio-reserved-ranges property.
The non-existent gpios are found in the am67x datasheet [1] in Table
5-27.
Depends on patch: dt-bindings: gpio: gpio-davinci: Add the
gpio-reserved-ranges property [2]
[1] https://www.ti.com/lit/ds/symlink/am67.pdf
[2] https://lore.kernel.org/all/20240809154638.394091-2-j-mcarthur@ti.com/
Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
Link: https://lore.kernel.org/r/20240809162828.1945821-3-j-mcarthur@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Commit 29075cc09f ("arm64: dts: ti: Introduce AM62P5 family of
SoCs") introduced the main_gpio1 node and included the ti,ngpio
property, but did not include the gpio-reserved-ranges property. As a
result, the user could try to access gpios that do not exist. Fix this
by introducing the gpio-reserved-ranges property.
The non-existent gpios are found in the am62p datasheet [1] in Table
5-24.
Depends on patch: dt-bindings: gpio: gpio-davinci: Add the
gpio-reserved-ranges property [2]
[1] https://www.ti.com/lit/ds/symlink/am62p.pdf
[2] https://lore.kernel.org/all/20240809154638.394091-2-j-mcarthur@ti.com/
Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
Link: https://lore.kernel.org/r/20240809162828.1945821-2-j-mcarthur@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
mmc1 is not functional and needs clock loopback so that it can
create sampling clock from this for high speed SDIO operations.
Thus, add clklb pin mux to get mmc1 working.
Fixes: a266c180b3 ("arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base board")
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20240809072231.2931206-1-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
