Commit Graph

35001 Commits

Author SHA1 Message Date
Chunming Zhou
36f8c1f903 drm/amdgpu: adapt vm size for multi vmpt
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:30 -04:00
Chunming Zhou
f7effef8d6 drm/amdgpu: limit block size to one page
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:29 -04:00
Chunming Zhou
a1adf8bef2 drm/amdgpu: abstract block size to one function
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:29 -04:00
Christian König
f566ceb165 drm/amdgpu: add alloc/free for multi level PDs V2
Allocate and free page directories on demand.

V2:
a. clear entries allocation
b. fix entries index calculation
c. need alloc sub level even parent bo was allocated

Signed-off-by: Christian König <christian.koenig@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (v2)
Acked-by: Alex Deucher <alexander.deucher@amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:28 -04:00
Christian König
4e2cb640c2 drm/amdgpu: handle multi level PD during PT updates
Not the best solution, but good enough for now.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:27 -04:00
Christian König
194d216113 drm/amdgpu: handle multi level PD updates V2
Update all levels of the page directory.

V2:
a. sub level pdes always are written to incorrect place.
b. sub levels need to update regardless of parent updates.

Signed-off-by: Christian König <christian.koenig@amd.com> (V1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (V1)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (V2)
Acked-by: Alex Deucher <alexander.deucher@amd.com> (V2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:27 -04:00
Christian König
d711e1398d drm/amdgpu: handle multi level PD in the LRU
Move all levels to the end after command submission.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:26 -04:00
Christian König
670fecc876 drm/amdgpu: handle multi level PD during validation
All page directory levels should be in place after this.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:25 -04:00
Christian König
72a7ec5cf6 drm/amdgpu: handle multi level PD size calculation (v2)
Allows us to get the size for all levels as well.

v2: agd: fix warning

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:25 -04:00
Christian König
67003a15b7 drm/amdgpu: generalize page table level
No functional change, but the base for multi level page tables.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:24 -04:00
Christian König
8437a097fe drm/amdgpu: add num_level to the VM manager
Needs to be filled with handling.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:23 -04:00
Christian König
49ac8a24ca drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well
This way we save passing it through the different functions.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:23 -04:00
Christian König
a24960f321 drm/amdgpu: rename page_directory_fence to last_dir_update
Decribes better what this is used for.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:22 -04:00
Rex Zhu
a7c7bc4c0c drm/amd/powerplay: reduce sample period time
for power readings.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:22 -04:00
Huang Rui
e2a4cd69a5 drm/amdgpu: add get_clockgating callback for mmhub v1
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:21 -04:00
Huang Rui
2eba890cb8 drm/amdgpu: add get_clockgating for sdma v4
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:20 -04:00
Huang Rui
f9abe35c30 drm/amdgpu: add get_clockgating callback for soc15 (v3)
v2: squash register typo fix from Ray
v3: fix spelling

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:20 -04:00
Huang Rui
e96487a6a7 drm/amdgpu: add get_clockgating callback for nbio v6.1
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:19 -04:00
Huang Rui
12ad27faa8 drm/amdgpu: add get_clockgating callback for gfx v9
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:18 -04:00
Alex Deucher
e322edc322 drm/amdgpu/gfx9: further KIQ parameter cleanup
The ring structure already has what we need.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:18 -04:00
Alex Deucher
d72f2f46e6 drm/amdgpu/gfx9: store the eop gpu addr in the ring structure
Avoids passing around additional parameters during setup.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:17 -04:00
Alex Deucher
33fb869883 drm/amdgpu/gfx9: reduce the functon params for mpq setup
Everything we need is in the ring structure.  No need to
pass all the bits explicitly.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:16 -04:00
Alex Deucher
f7618a6330 drm/amdgpu/gfx9: reserve kiq eop object before unmapping it
It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:16 -04:00
Alex Deucher
e1d53aa880 drm/amdgpu/gfx9: reserve mqd objects before mapping them
It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:15 -04:00
Alex Deucher
e935c2116e drm/amdgpu/gfx9: rename some functions
To better match where they are used.  Called from sw_init
and sw_fini.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:15 -04:00
Alex Deucher
b4fcf7f069 drm/amdgpu/gfx9: whitespace cleanup
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:14 -04:00
Harry Wentland
9e8e453a70 drm/amd/amdgpu: Fix some warnings in vce4
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:13 -04:00
Xiangliang Yu
bf4305fe72 drm/amdgpu/vce4: impl vce & mmsch sriov start
For MM sriov, need use MMSCH to init engine and the init procedures
are all saved in mm table.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:13 -04:00
Xiangliang Yu
d7a98193f7 drm/amdgpu: add mmsch structures
For MM SRIOV, need to prepare MM table send send it to MMSCH to
initial UVD & VCE engine. Create new header file for the structures.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:12 -04:00
Xiangliang Yu
e76347b0c2 drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
In order to not break SRIOV gfx development, will revert
this patch after vce proved working.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:11 -04:00
Xiangliang Yu
f5dee22824 drm/amdgpu/vce4: alloc mm table for MM sriov
Allocate MM table for sriov device.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:11 -04:00
Xiangliang Yu
ecb2b9c698 drm/amdgpu/virt: add structure for MM table
Add new structure for MM table for multi media scheduler of sriov.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:10 -04:00
Xiangliang Yu
468842a5e5 drm/amdgpu: disable uvd for sriov
disable uvd for sriov temporarily.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:10 -04:00
Xiangliang Yu
bae5b5191d drm/amdgpu/vce4: enable doorbell for SRIOV
VCE SRIOV need use doorbell and only works on VCN0 ring now

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:09 -04:00
Xiangliang Yu
d9af225942 drm/amdgpu: Don't touch PG&CG for SRIOV MM
For SRIOV, MM don't need to care about PG & CG, skip it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:08 -04:00
Monk Liu
e6b3ecb4db drm/amdgpu/vega10:fix DOORBELL64 scheme
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:08 -04:00
Alex Deucher
f8445307b6 drm/amdgpu:vega10: enable virtual display if set via module option
Enable virtual displays if the user has enabled them via the
kernel command line.  Useful in virtual or headless environments.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:07 -04:00
Xiangliang Yu
796b656840 drm/amdgpu/soc15: enable virtual dce for vf
VF need virtual dce, enable it if device is vf.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:06 -04:00
Xiangliang Yu
f1a34465c8 drm/amdgpu/soc15: init virt ops for vf
If gpu device is vf, set virt ops so that guest can talk with GPU
hypervisor.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:06 -04:00
Xiangliang Yu
c9c9de93a3 drm/amdgpu/virt: impl mailbox for ai
Implement mailbox protocol for AI so that guest vf can communicate
with GPU hypervisor.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:05 -04:00
Xiangliang Yu
ebe0a80979 drm/amdgpu/dce_virtual: bypass DPM for vf
If enable DPM for VF, always get lot of warn_slow_patch_null in
dmesg and vf doesn't support DPM.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:04 -04:00
Xiangliang Yu
c7a7266b7d drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
two reasons:
1. there is a spinlock around;
2. vm register is pf/vf copy, vf can access via mmio safely.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:04 -04:00
Xiangliang Yu
86d3798af0 drm/amdgpu/soc15: bypass PSP for VF
Bypass PSP block for VF device.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:03 -04:00
Monk Liu
0e11de1ef5 drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
Rework sdma init to support SR-IOV.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:03 -04:00
Monk Liu
cfee05bc90 drm/amdgpu:bypass RLC init for SRIOV
one issue unresolved for RLC:
rlc will go wrong completely if there is a soft_reset
before RLC ucode loading.

to workaround above issue, we can totally ignore RLC
in guest driver side due to there was already full
initialization on RLC side by GIM

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:02 -04:00
Xiangliang Yu
cca02cd3d4 drm/amdgpu/gfx9: impl gfx9 meta data emit
Insert ce meta prior to cntx_cntl and de follow it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:01 -04:00
Monk Liu
9a5e02b5cc drm/amdgpu:impl gfx9 cond_exec (v2)
it is needed for virtualization

v2: squash in wptr value fix

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:01 -04:00
Xiangliang Yu
464826d67a drm/amdgpu: init kiq and kcq for vega10
Init kiq via cpu mmio and init kcq through kiq.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:55:00 -04:00
Xiangliang Yu
97031e2541 drm/amdgpu/gfx9: fullfill kiq irq funcs (v2)
Fullfill KIQ irq funcs to support kiq interrupt.

v2: squash in adding interrupt src

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:59 -04:00
Xiangliang Yu
aa6faa44dd drm/amdgpu/gfx9: fullfill kiq funcs (v2)
Fullfill kiq funcs to support kiq ring.

v2: squash in 64bit ptr fix

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:59 -04:00
Xiangliang Yu
ac104e99cd drm/amdgpu: add kiq ring for gfx9
Allocate KIQ ring in sw_init for gfx9.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:58 -04:00
Xiangliang Yu
1b922423ce drm/amdgpu: impl sriov detection for vega10
Read vega10 hw register to detect if sriov is enabled, and call
it before IP blocks setting.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:57 -04:00
Monk Liu
3fc08b61df drm/amdgpu/gfx9: programing wptr_poll_addr register
Required for SR-IOV.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:57 -04:00
Junwei Zhang
ca2f1ccaf9 drm/amdgpu: add Vega10 Device IDs (v2)
v2: add AMD_EXP_HW_SUPPORT for now

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:56 -04:00
Ken Wang
460826e6a0 drm/amdgpu: Set the IP blocks for vega10
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:56 -04:00
Ken Wang
220ab9bd1c drm/amdgpu: soc15 enable (v3)
Add soc15 support and enable all the IPs for vega10.

v2: squash in xclk fix
v3: disable HDP MGCG

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:55 -04:00
Eric Huang
f83a999164 drm/amd/powerplay: add Vega10 powerplay support (v5)
Adds power management support for vega10.

v2: squash in fan control and led config fixes from Rex
v3: squash in dead code removal and socvid fixes from Rex
v4: squash in dpm force level fix from Rex
v5: squash in latest headless, gpu load fixes from Rex

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:54 -04:00
Eric Huang
d018772748 drm/amd/powerplay: add some display/powerplay interfaces
New interfaces needed to handle the new clock trees and
bandwidth requirements on vega10.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:54 -04:00
Eric Huang
a2dd023a77 drm/amd: add structures for display/powerplay interface
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:53 -04:00
Eric Huang
e29922795f drm/amd/powerplay: add some new structures for Vega10
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:52 -04:00
Rex Zhu
2a5071056e drm/amd/powerplay: add global PowerPlay mutex.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:52 -04:00
Eric Huang
0d2c7569e1 drm/amdgpu: add new atomfirmware based helpers for powerplay
New helpers for fetching info out of atomfirmware.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Ken.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:51 -04:00
Eric Huang
bcea239686 drm/amd/powerplay: add new Vega10's ppsmc header file
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:51 -04:00
Eric Huang
25e2196cc8 drm/amd/powerplay: add smu9 header files for Vega10
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:50 -04:00
Huang Rui
d1de1ed3df drm/amdgpu: add SMC firmware into global ucode list for psp loading
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:49 -04:00
Huang Rui
6a7ed07e27 drm/amdgpu: add psp firmware info into info query and debugfs
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:49 -04:00
Huang Rui
0e5ca0d1ac drm/amdgpu: add PSP driver for vega10 (v2)
PSP is responsible for firmware loading on SOC-15 asics.

v2: fix memory leak (Ken)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:48 -04:00
Leo Liu
c1dc356a11 drm/amdgpu: add initial vce 4.0 support for vega10
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:47 -04:00
Leo Liu
09bfb8912d drm/amdgpu: add initial uvd 7.0 support for vega10
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:47 -04:00
Ken Wang
282aae555e drm/amdgpu: add vega10 interrupt handler
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:46 -04:00
Ken Wang
b102357147 drm/amdgpu: implement GFX 9.0 support (v2)
Add support for gfx v9.0.

v2: update golden settings from Ken

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:45 -04:00
Ken Wang
2130f89ced drm/amdgpu: add SDMA v4.0 implementation (v2)
v2: fix Makefile

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:45 -04:00
Alex Xie
e60f8db5e4 drm/amdgpu: Add GMC 9.0 support (v2)
On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).

v2: drop sdma from Makefile, fix duplicate return statement.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:44 -04:00
Junwei Zhang
c1d83da980 drm/amdgpu: add NBIO 6.1 driver
This handles nbio 6.1 specific implementations which
are used by various other IPs.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:44 -04:00
Alex Xie
b0fd18b071 drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:43 -04:00
Alex Xie
15b31c59bc drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:42 -04:00
Alex Deucher
a0676f6083 drm/amdgpu: gart fixes for vega10
Flags need to be 0 to be considered invalid.

Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:42 -04:00
Huang Rui
eb6611135f drm/amdgpu: add psp firmware header info
Defines the header info for the psp firmware.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:41 -04:00
Huang Rui
2445b22751 drm/amdgpu: rework common ucode handling for vega10
Handle ucode differences in vega10.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:40 -04:00
Marek Olšák
9079ac7666 drm/amdgpu: don't validate TILE_SPLIT on GFX9
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:40 -04:00
Alex Deucher
bce23e00f3 drm/amdgpu: add NGG parameters
NGG (Next Generation Graphics) is a new feature in GFX9.0.  This
adds the relevant parameters.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:38 -04:00
Alex Deucher
ca02061c7a drm/amdgpu: add PTE defines for MTYPE
New on SOC-15 asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:37 -04:00
Christian König
cef105f7dc drm/amdgpu: add IV trace point
This allows us to grab IVs without spamming the log.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:37 -04:00
Alex Deucher
614dea315f drm/amdgpu: update IH IV ring entry for soc-15
Reflect the new format on soc-15 asics.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:36 -04:00
Alex Deucher
be34d3bfe3 drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
If the board is atomfirmware based.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:35 -04:00
Alex Xie
66e02bc343 drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:35 -04:00
Ken Wang
39807b939e drm/amdgpu: add 64bit doorbell assignments
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:34 -04:00
Andrey Grodzovsky
d0e95758e3 drm/amdgpu: gb_addr_config struct
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:33 -04:00
Huang Rui
e635ee0745 drm/amdgpu: use new flag to handle different firmware loading method
This patch introduces a new flag named "amdgpu_firmware_load_type" to
handle different firmware loading method. Since Vega10, there are
three ways to load firmware. It would be better to use a flag and a
fw_load_type kernel parameter to configure it.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:33 -04:00
ken
70170d146d drm/amdgpu: add clinetid definition for vega10
Signed-off-by: ken <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:32 -04:00
Ken Wang
d4196f011c drm/amdgpu: add vega10 chip name
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:32 -04:00
Ken Wang
8e3153ba3f drm/amdgpu: add common soc15 headers
These are used by various IP modules.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:31 -04:00
Alex Deucher
90df1d55a2 drm/amdgpu: add SDMA 4.0 packet header
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:30 -04:00
Alex Deucher
6a38ce8f19 drm/amdgpu: add gfx9 clearstate header
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:30 -04:00
Felix Kuehling
4b219123e9 drm/amd: Add MQD structs for GFX V9
This header defines the gfx v9 MEC structures.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:29 -04:00
Alex Deucher
f6c3947893 drm/amdgpu: add the VCE 4.0 register headers
These are the Video Compression Engine registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:28 -04:00
Alex Deucher
7008d577d6 drm/amdgpu: add the UVD 7.0 register headers
These are the Unifed Video Decoder registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:28 -04:00
Alex Deucher
893f25540e drm/amdgpu: add THM 9.0 register headers
These are the THerMal control registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:27 -04:00
Alex Deucher
63d311d9b4 drm/amdgpu: add SMUIO 9.0 register headers
These are the System Managment Unit IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:26 -04:00
Alex Deucher
456f97704f drm/amdgpu: add SDMA 4.0 register headers
These are the System DMA register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:26 -04:00
Alex Deucher
5a8288c0f9 drm/amdgpu: add OSSSYS 4.0 register headers
These are the OS Services register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:25 -04:00
Alex Deucher
198b746016 drm/amdgpu: add NBIO 6.1 register headers
These are the Bus IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:24 -04:00
Alex Deucher
61e04478b2 drm/amdgpu: add NBIF 6.1 register headers
These are the Bus InterFace registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:23 -04:00
Alex Deucher
3ec127a075 drm/amdgpu: add MP 9.0 register headers
MP is the system management controller on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:23 -04:00
Alex Deucher
68c7d13052 drm/amdgpu: add the MMHUB 1.0 register headers
Add the MultiMedia Hub registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:22 -04:00
Alex Deucher
bcfb47cdd7 drm/amdgpu: add the HDP 4.0 register headers
These are the Host Data Path registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:21 -04:00
Alex Deucher
5585476e44 drm/amdgpu: add the GC 9.0 register headers
Add the Graphics Core register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:21 -04:00
Alex Deucher
4adc5ab813 drm/amdgpu: Add the DCE 12.0 register headers
These are the register headers for the Display
and Composition Engine on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:20 -04:00
Alex Deucher
7fee1fd93b drm/amdgpu: Add ATHUB 1.0 register headers
ATHUB is part of the memory controller on soc15 asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:19 -04:00
Alex Deucher
733acf561e drm/amdgpu: add vega10_enum.h
This adds the register bitfield enums for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:19 -04:00
Alex Deucher
1fd1cc5640 drm/amdgpu: add soc15ip.h
This header defines the IP layout for soc15 based SoCs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:18 -04:00
Alex Deucher
a5bde2f964 drm/amdgpu: add basic support for atomfirmware.h (v3)
This adds basic support for asics that use atomfirmware.h
to define their vbios tables.

v2: rebase
v3: squash in num scratch reg fix

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:17 -04:00
Alex Deucher
43bf11bd92 drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
There will be a slightly different version for atomfirmware.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:17 -04:00
Alex Deucher
0cdd500560 amdgpu: detect if we are using atomfirmware or atombios for vbios (v2)
Supposedly atomfirmware rom header is 3.3 atombios is 1.1.

v2: rebased on newer kernel

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:16 -04:00
Alex Deucher
1fadf42ed5 drm/amdgpu: add the new atomfirmware interface header
soc15 asics have a new vbios interface.  These headers
define that interface.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:15 -04:00
Nicolai Hähnle
f34678187a drm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freed
We will add the fence to freed buffer objects in a later commit, to ensure
that the underlying memory can only be re-used after all references in
page tables have been cleared.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:15 -04:00
Eric Huang
923d26db85 drm/amd/powerplay: restore disabling power containment on Fiji (v2)
Power containment will degrade performance in some compute tests.
Restore disabling it as before code refining in powerplay.

v2: only in the compute profile

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:14 -04:00
Alex Deucher
a2140e00e0 drm/amdgpu/gfx8: further KIQ parameter cleanup
The ring structure already has what we need.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:13 -04:00
Alex Deucher
345346108b drm/amdgpu/gfx8: store the eop gpu addr in the ring structure
Avoids passing around additional parameters during setup.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:13 -04:00
Alex Deucher
015c23600a drm/amdgpu/gfx8: reduce the functon params for mpq setup
Everything we need is in the ring structure.  No need to
pass all the bits explicitly.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:12 -04:00
Alex Deucher
f2effd49e7 drm/amdgpu/gfx8: reserve kiq eop object before unmapping it
It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:12 -04:00
Alex Deucher
0104cf2536 drm/amdgpu/gfx8: fold loops in kiq_resume()
No need to loop through the compute queues twice.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:11 -04:00
Alex Deucher
2e263c824a drm/amdgpu/gfx8: test KIQ before compute rings
If KIQ isn't working, the compute rings won't work either.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:10 -04:00
Alex Deucher
6a6f380f07 drm/amdgpu/gfx8: reserve mqd objects before mapping them
It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:10 -04:00
Alex Deucher
0875a24296 drm/amdgpu/gfx8: rename some functions
To better match where they are used.  Called from sw_init
and sw_fini.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:09 -04:00
Alex Deucher
b0ac2a32ad drm/amdgpu/gfx8: whitespace cleanup
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:08 -04:00
Rex Zhu
0d52c6a13e drm/amdgpu: load mc firware in driver for Polaris.
load mc ucode in driver if VBIOS not loaded
a full version of MC ucode,

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: jimqu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:08 -04:00
Chunming Zhou
aacbbc8bc1 drm/amdgpu: fix duplicated code
it could come from branch merge.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:07 -04:00
Rex Zhu
739e9fffde drm/amdgpu: enable gfx/system/vce clockgating on Polars12.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:06 -04:00
Rex Zhu
1c622002b1 drm/amd/powerplay: add a new register define for APU in VI.
the ixcurrent_pg_status addr is different between APU and DGPU.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:06 -04:00
Eric Huang
170d6e94e5 drm/amdgpu: enable GFX/UVD/VCE PG for Bristol
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:05 -04:00
Tom St Denis
d1aff8ec49 drm/amd/amdgpu: Set VCE/UVD off during late init
Forces VCE/UVD off during late init to ensure they're powered off
correctly during boot.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:05 -04:00
Colin Ian King
f917c2ad92 drm/amdgpu: remove redundant outer loop and remove commented out code
The outer loop is redundant and can be removed as it is doing nothing
useful. Also remove some commented out code that is not being used.

Detected by CoverityScan, CID#1402073

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:04 -04:00
Chunming Zhou
153de9dff9 drm/amd/sched: revise priority number
big number is to high priority.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:03 -04:00
Alex Deucher
8eafd505db drm/amdgpu: bump version for PRT support
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:03 -04:00
Junwei Zhang
27f6d61036 drm/amdgpu: fix before and after mapping judgement for replace mapping
If the before mapping is 1 page size, so its start and last will be same.
Thus below condition will become false, then to free the before mapping.
   > if (before->it.start != before->it.last)
But in this case, we need the before mapping of 1 page size.
So does after mapping.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:02 -04:00
Christian König
80f95c579d drm/amdgpu: add a VM mapping replace operation v2
Add a new operation to replace mappings in a VM with a new one.

v2: Fix Jerry's comment, separate out clear operation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:01 -04:00
Christian König
dc54d3d174 drm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2
A new VM operation to remove all mappings in a range.

v2: limit unmapped area as noted by Jerry

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:01 -04:00
Christian König
663e4577a5 drm/amdgpu: separate page table allocation from mapping
This makes it easier to implement a replace operation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:54:00 -04:00
Christian König
4388fc2ab0 drm/amdgpu: make set_prt callback optional and fix error handling
PRT support is completely implemented now and we left it
turned on accidentially in the error path.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:59 -04:00
Alex Deucher
d319c2bcc6 drm/amdgpu/vi: add missing error handling when setting uvd dclk
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:59 -04:00
Alex Deucher
8085c69968 drm/amdgpu/vi: remove duplicate CG flags
GFX_MGLS was added twice.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:58 -04:00
Andrew F. Davis
93a4aec218 drm/amd/powerplay: remove unneeded conversions to bool
Found with scripts/coccinelle/misc/boolconv.cocci.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:58 -04:00
Andrew F. Davis
7e91366420 drm/amdgpu: remove unneeded conversions to bool
Found with scripts/coccinelle/misc/boolconv.cocci.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:57 -04:00
Andres Rodriguez
c98b5c9714 drm/amdgpu: add macro to retrieve timeline name v2
This helps de-duplicate a long expression and removes overly long lines.

v2: Rename macro and undef it

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:56 -04:00
Andres Rodriguez
ced2ef66dc drm/amdgpu: replace fence pointer with fence data in traces
Fence data is easier to read and allows us to correlate to identify
corresponding dma_fence ftrace events.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:56 -04:00
Andres Rodriguez
2359419fa5 drm/amdgpu: remove useless pointers from traces
Remove pointers which provide redundant information which is already
easier to deduce from other fields.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:55 -04:00
Andres Rodriguez
f6fd20304a drm/amdgpu: use sched_job id instead of pointer for tracing
Pointers get reallocated and they are hard to read for humans. Use ids
instead.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:54 -04:00
Andres Rodriguez
373eadfa6a drm/amdgpu: more ftrace formatting consistency fixes
Consistent formatting makes it easier to read the logs and apply simple
awk oneliners.

I missed some of these on my last patch.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:54 -04:00
Andres Rodriguez
93f8b36738 drm/amd/sched: add a unique job id to amd_sched_job
A unique id is useful for debugging and tracing. Intended to replace
pointers in ftrace output.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:53 -04:00
Roger.He
8fb6e528c3 drm/amdgpu: increase IH ring buffer size to avoid overflow
We originally limited the IH to 4k on tonga since it
uses bus addresses directly rather than GPU MC addresses,
so it needs contigous physical memory.  This brings it
inline with other asics.

Signed-off-by: Roger.He <Hongbo.He@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:53 -04:00
Alex Deucher
d2d51d8192 drm/amdgpu: don't init GDS pool if GDS size is 0 (v2)
SI cards don't expose GDS as a separate pool.  The CP manages
GDS and the UMDs use special CP packets to allocate GDS memory.

v2: drop extra whitespace change

bug: https://bugzilla.kernel.org/show_bug.cgi?id=194867

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:52 -04:00
Alex Deucher
11ba13e179 drm/amdgpu/gfx6: drop gds unrefs
Leftover from gfx7 code.  gfx6 never sets up the gds buffers
in the first place.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:51 -04:00
Rex Zhu
2667989927 drm/amdgpu: refine vce_3.0 code.
fix logic error in hw_fini and
set_clockgating_state functions.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:51 -04:00
Rex Zhu
03a5f1df5b drm/amdgpu: refine vce2.0 dpm sequence
start vce first then enable vce dpm.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:50 -04:00
Alex Deucher
c5e38e1194 drm/radeon: add new ATIF ACPI method
Used for fetching external GPU information.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:49 -04:00
Alex Deucher
8285052ef1 drm/amdgpu: add new ATIF ACPI method
Used for fetching external GPU information.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:49 -04:00
Leo Liu
166c8178fb drm/amdgpu: get cs support of AMDGPU_HW_IP_UVD_ENC
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:48 -04:00
Leo Liu
63defd3f67 drm/amdgpu: add AMDGPU_HW_IP_UVD_ENC to info query
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:47 -04:00
Leo Liu
50c3e23299 drm/amdgpu: add uvd enc ring type and functions
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:46 -04:00
Leo Liu
a28f0a164c drm/amdgpu: add uvd enc run queue
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:46 -04:00
Leo Liu
f7243053c2 drm/amdgpu: add uvd enc rings
And initialize them

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:45 -04:00
Leo Liu
5e5681788b drm/amdgpu: move amdgpu_vce structure to vce header
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:44 -04:00
Leo Liu
4df654d293 drm/amdgpu: move amdgpu_uvd structure to uvd header
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:44 -04:00
Leo Liu
135d4735d8 drm/amdgpu: add a ring func for end command
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:43 -04:00
Huang Rui
c773a632a9 drm/amdgpu: add DF MGCG flag
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:42 -04:00
Huang Rui
e929c98d2e drm/amdgpu: add DRM MGCG header
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:42 -04:00
Alex Deucher
bbf282d884 drm/amdgpu: add asic callback to get memsize register
Newer asics use different registers so abstract it.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:41 -04:00
Rex Zhu
c722865a19 drm/amdgpu: check function points valid before use. (v3)
v2: agd: integrate Christian's comments.
v3: print error message if call fails

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:41 -04:00
Alex Xie
5463545b92 drm/amdgpu: add a callback to set vm mapping flags
This lets each asic set whichever flags it supports.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:40 -04:00
Alex Xie
4b98e0c4ae drm/amdgpu: set GART PTE asic specific flags
Set asic specific gart pte flags in the gmc IP module for
each asic.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:39 -04:00
Huang Rui
daf42c314d drm/amdgpu: add a ucode size member into firmware info
This will be used for newer asics.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:39 -04:00
Chunming Zhou
6b777607c1 drm/amdgpu: expand pte flags to uint64_t
Necessary for new asics.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:38 -04:00
Alex Deucher
7ccf5aa8ba drm/amdgpu/ih: store the full context id
The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics.  Expand the
src_id field to handle this.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:37 -04:00
Alex Deucher
d766e6a393 drm/amdgpu: switch ih handling to two levels (v3)
Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:37 -04:00
Ken Wang
832be4041d drm/amdgpu: add 64bit doorbell functions (v2)
Newer asics need 64 bit doorbells.

v2: fix comment (Nils)

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:36 -04:00
Ken Wang
7014285ade drm/amdgpu: add 64bit wb functions
Newer asics need 64 bit writeback slots.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:35 -04:00
Ken Wang
536fbf946c drm/amdgpu: change wptr to 64 bits (v2)
Newer asics need 64 bit wptrs.  If the wptr is now
smaller than the rptr that doesn't indicate a wrap-around
anymore.

v2: integrate Christian's comments.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:35 -04:00
Junwei Zhang
8fe733289b drm/amdgpu: init aperture definitions (v2)
v2: agd: move apertures to mc structure

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:34 -04:00
Daniel Vetter
04e30c9c86 drm/amdgpu: Merge pre/postclose hooks
Again no apparent explanation for the split except hysterical raisins.
Merging them also makes it a bit more obviuos what's going on wrt the
runtime pm refdancing.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:33 -04:00
Daniel Vetter
78910246dd drm/radeon: Merge pre/postclose hooks
Again no apparent explanation for the split except hysterical raisins.
Merging them also makes it a bit more obviuos what's going on wrt the
runtime pm refdancing.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:33 -04:00
Andres Rodriguez
82c6bd46bf drm/amdgpu: trace fence details in amdgpu_sched_run_job
This information is intended to provide the required data to associate
amdgpu tracepoints with their corresponding dma_fence_* events.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:32 -04:00
Andres Rodriguez
f8d569011c drm/amdgpu: make trace format uniform csv name=value
Most of the traces have uniform format except for two of them. Having
all the traces match makes it simple to run awk on the ftrace output.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:31 -04:00
Xiangliang Yu
49abb980c5 drm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.h
Because different HWs have different definition for CE & DE meta
data, follow mqd design to move the structures to vi_structs.h.

And change the prefix from amdgpu to vi as the structures is only
for VI family.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:31 -04:00
Junshan Fang
7dae618174 drm/amd/amdgpu: add DID for Polaris10
Signed-off-by: Junshan Fang <Junshan.Fang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:30 -04:00
Alex Deucher
2fc5338494 drm/amdgpu: add polaris12 to virtual dce handling
Was missed when polaris12 support was added.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:30 -04:00
Christian König
81522f71b1 drm/amdgpu: remove unused sync testing
Not used in a while.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:29 -04:00
Eric Huang
35011d398e drm/amd/powerplay: simplify avfs control code in smu7
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:28 -04:00
Eric Huang
f9c993ceb1 drm/amd/powerplay: add function avfs control in smu7
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:28 -04:00
Eric Huang
dd4bdf3b35 drm/amd/powerplay: add voltage change support through pp_table
Disable avfs to make voltage change take effect.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:27 -04:00
Andy Shevchenko
a33c1a822c drm/radeon: remove useless and potentially wrong message
There is no need to repeat information that printed by PCI core at boot time.

Besides that printing was potentially wrong since resource_size_t might be
bigger than 32 bits and there is a dedicated specifier for such type, i.e.
%pap. Someone can fix it and use even better approach, i.e. %pR.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:26 -04:00
Rex Zhu
cf4270ec68 drm/amdgpu: print full bios version in dmesg.
v2: fix merge error.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:26 -04:00
Christian König
c5cb934ebd drm/amdgpu: disable HDP flushes on APUs
We completely bypass the HDP now.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:25 -04:00
Joe Perches
7ca85295d8 gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>
Use a more common logging style.

Miscellanea:

o Coalesce formats and realign arguments
o Neaten a few macros now using pr_<level>

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:24 -04:00
Joe Perches
eeca232490 drm: Use pr_cont where appropriate
Using 'printk("\n")' is not preferred anymore and
using printk to continue logging messages now produces
multiple line logging output unless the continuations
use KERN_CONT.

Convert these uses to appropriately use pr_cont or a
single printk where possible.

Miscellanea:

o Use a temporary const char * instead of multiple printks
o Remove trailing space from logging by using a leading space instead

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:24 -04:00
Alex Deucher
9dc5a91e4d drm/amdgpu: put gtt at 0 in the internal address space
There still seem to be some blocks that make accesses
in the lower part of the address space.  This works around
this.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:23 -04:00
Alex Deucher
dc3abc16a7 drm/amdgpu/vce2: fix vce bar programming
Program the VCE BAR and offsets properly.  The current code
was carried over from a limitation from older VCE versions.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:22 -04:00
Joe Perches
98a36749eb drivers/gpu: Convert remaining uses of pr_warning to pr_warn
To enable eventual removal of pr_warning

This makes pr_warn use consistent for drivers/gpu

Prior to this patch, there were 15 uses of pr_warning and
20 uses of pr_warn in drivers/gpu

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:22 -04:00
Geert Uytterhoeven
6137a0fec2 drm/amd: Spelling s/SDMA_WRTIE_SUB_OPCODE_TILED/SDMA_WRITE_SUB_OPCODE_TILED/
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: dri-devel@lists.freedesktop.orgamd-gfx@lists.freedesktop.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:21 -04:00
Lyude
92c177b794 drm/radeon/dp_auxch: Ratelimit aux transfer debug messages
Aux transfers always fail with non-zero status flags when there's
nothing connected on the port, so we don't usually need to see all of
the debugging information from it. Also, we try reprobing a -lot-, so
without ratelimiting most of the kernel log is filled up with messages
from radeon_dp_aux_transfer_native.

Signed-off-by: Lyude <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29 23:53:21 -04:00