The I2S controller can handle sample rates only up to 96000 and the CPU DAI
has already related constraint set so drop the impossible 176400, 192000
switch cases.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
In case of sample rates lower than 44100 currently there is too low MCLK
frequency set for the CODEC. Playback fails with following errors:
$ speaker-test -c2 -t sine -f 1500 -l2 -r 32000
Sine wave rate is 1500.0000Hz
Rate set to 32000Hz (requested 32000Hz)
Buffer size range from 128 to 131072
Period size range from 64 to 65536
Using max buffer size 131072
Periods = 4
Unable to set hw params for playback: Invalid argument
Setting of hwparams failed: Invalid argument
[ 497.883700] max98090 1-0010: Invalid master clock frequency
To fix this the I2S root clock's frequency is increased, depending
on sampling rate.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
The Odroid boards are manufactured by Hardkernel, not Samsung. New compatible
string entries are added, with "hardkernel," instead of "samsung," vendor
prefix. Support for the old compatible strings is going to be removed after
some time.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
As suggested in reviews the requirement of clocks in the 'sound' node
is dropped and instead a leaf clock is used to configure frequency
of the audio root clock PLL. This can work now after the clock tree
definitions have been updated to allow clock rate setting propagation
on the path from the I2S controller up to the EPLL.
This patch also lowers the CODEC master clock frequency so as
to not exceed the maximum allowed 60 MHz at maximum audio sampling
rates.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
To prevent incorrect setting of the EPLL the clock frequency
values are changed to exact values as possible to obtain on
the EPLL output with given PLL coefficients.
This patch is required after recent change of the EPLL rate
table by patch
"clk: samsung: exynos5420: The EPLL rate table corrections".
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This dedicated driver allows to support SoC specific clock
settings and helps to ensure proper number of channels gets
negotiated in multicodec system configurations.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
