Commit Graph

781689 Commits

Author SHA1 Message Date
Linus Walleij
1c5fb66afa pinctrl: Include <linux/gpio/driver.h> nothing else
These drivers are GPIO drivers, and the do not need to use the
legacy header in <linux/gpio.h>, go directly for
<linux/gpio/driver.h> instead.

Replace any use of GPIOF_* with 0/1, these flags are for
consumers, not drivers.

Get rid of a few gpio_to_irq() users that was littering
around the place, use local callbacks or avoid using it at
all.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-14 15:10:57 +02:00
Linus Walleij
e897b38665 pinctrl: at91-pio4: Get rid of legacy call
By just moving the atmel_gpio_to_irq() and calling the internal
function we can get rid of the driver calling back out into the
deprecated external consumer API.

Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-14 12:49:19 +02:00
Ludovic Desroches
0c3dfa1769 pinctrl: at91: don't use the same irqchip with multiple gpiochips
Sharing the same irqchip with multiple gpiochips is not a good
practice. For instance, when installing hooks, we change the state
of the irqchip. The initial state of the irqchip for the second
gpiochip to register is then disrupted.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-14 10:58:54 +02:00
Dan Carpenter
b97760ae8e pinctrl: at91-pio4: fix has_config check in atmel_pctl_dt_subnode_to_map()
Smatch complains about this condition:

	if (has_config && num_pins >= 1)

The "has_config" variable is either uninitialized or true.  The
"num_pins" variable is unsigned and we verified that it is non-zero on
the lines before so we know "num_pines >= 1" is true.  Really, we could
just check "num_configs" directly and remove the "has_config" variable.

Fixes: 776180848b ("pinctrl: introduce driver for Atmel PIO4 controller")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-13 14:17:09 +02:00
Stephen Boyd
89c68b102f pinctrl: qcom: spmi-mpp: Fix drive strength setting
It looks like we parse the drive strength setting here, but never
actually write it into the hardware to update it. Parse the setting and
then write it at the end of the pinconf setting function so that it
actually sticks in the hardware.

Fixes: 0e948042c4 ("pinctrl: qcom: spmi-mpp: Implement support for sink mode")
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-10 09:31:02 +02:00
YueHaibing
9ae4987ebb pinctrl: sirf: atlas7: remove set but not used variables 'conf, bank'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/pinctrl/sirf/pinctrl-atlas7.c: In function 'atlas7_pinmux_resume_noirq':
drivers/pinctrl/sirf/pinctrl-atlas7.c:5545:6: warning:
 variable 'bank' set but not used [-Wunused-but-set-variable]
  u32 bank;

drivers/pinctrl/sirf/pinctrl-atlas7.c:5543:28: warning:
 variable 'conf' set but not used [-Wunused-but-set-variable]
  struct atlas7_pad_config *conf;

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-05 12:13:13 +02:00
Douglas Anderson
0d5b476f8f pinctrl: spmi-mpp: Fix pmic_mpp_config_get() to be compliant
If you look at "pinconf-groups" in debugfs for ssbi-mpp you'll notice
it looks like nonsense.

The problem is fairly well described in commit 1cf86bc212 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c82895 ("pinctrl: msm: Fix msm_config_group_get() to be
compliant"), but it was pointed out that ssbi-mpp has the same
problem.  Let's fix it there too.

NOTE: in case it's helpful to someone reading this, the way to tell
whether to do the -EINVAL or not is to look at the PCONFDUMP for a
given attribute.  If the last element (has_arg) is false then you need
to do the -EINVAL trick.

ALSO NOTE: it seems unlikely that the values returned when we try to
get PIN_CONFIG_BIAS_PULL_UP will actually be printed since "has_arg"
is false for that one, but I guess it's still fine to return different
values so I kept doing that.  It seems like another driver (ssbi-gpio)
uses a custom attribute (PM8XXX_QCOM_PULL_UP_STRENGTH) for something
similar so maybe a future change should do that here too.

Fixes: cfb24f6ebd ("pinctrl: Qualcomm SPMI PMIC MPP pin controller driver")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-05 12:11:18 +02:00
Douglas Anderson
b432414b99 pinctrl: ssbi-gpio: Fix pm8xxx_pin_config_get() to be compliant
If you look at "pinconf-groups" in debugfs for ssbi-gpio you'll notice
it looks like nonsense.

The problem is fairly well described in commit 1cf86bc212 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c82895 ("pinctrl: msm: Fix msm_config_group_get() to be
compliant"), but it was pointed out that ssbi-gpio has the same
problem.  Let's fix it there too.

Fixes: b4c45fe974 ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-05 12:10:50 +02:00
Linus Walleij
2e38b882b9 pinctrl: sh-pfc: Updates for v4.20
- Add SATA and audio pin groups on R-Car M3-N,
   - Add EtherAVB pin groups on RZ/G1C,
   - Add PWM and display (DU) pin groups on R-Car E3,
   - Add support for the new RZ/G2M (r8a774a1) SoC.
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Merge tag 'sh-pfc-for-v4.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.20

  - Add SATA and audio pin groups on R-Car M3-N,
  - Add EtherAVB pin groups on RZ/G1C,
  - Add PWM and display (DU) pin groups on R-Car E3,
  - Add support for the new RZ/G2M (r8a774a1) SoC.
2018-08-31 15:42:33 +02:00
Igor Stoppa
27d91e80d5 pinctrl: remove unnecessary unlikely()
WARN_ON() already contains an unlikely(), so it's not necessary to
wrap it into another.

Signed-off-by: Igor Stoppa <igor.stoppa@huawei.com>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:29:12 +02:00
Andy Shevchenko
ae4610873f pinctrl: lewisburg: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:54 +02:00
Andy Shevchenko
558b34ba10 pinctrl: sunrisepoint: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:50 +02:00
Andy Shevchenko
4ee73414a4 pinctrl: icelake: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:46 +02:00
Andy Shevchenko
6016b099c3 pinctrl: geminilake: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:43 +02:00
Andy Shevchenko
c804d8ae20 pinctrl: denverton: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:38 +02:00
Andy Shevchenko
b417748c0f pinctrl: cedarfork: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:35 +02:00
Andy Shevchenko
05a100e4ac pinctrl: cannonlake: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:31 +02:00
Andy Shevchenko
5689d6aaea pinctrl: broxton: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:27 +02:00
Andy Shevchenko
6d7c05faaf pinctrl: intel: Introduce common macro for PM operations
This common macro will simplify the code of pin control drivers
for Intel SoCs.

Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:23 +02:00
Andy Shevchenko
0c03e92e7d pinctrl: sunrisepoint: Convert to use intel_pinctrl_probe_by_hid()
Get rid of code duplication by converting to use intel_pinctrl_probe_by_hid().

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:19 +02:00
Andy Shevchenko
c98a96672b pinctrl: cannonlake: Convert to use intel_pinctrl_probe_by_hid()
Get rid of code duplication by converting to use intel_pinctrl_probe_by_hid().

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:15 +02:00
Andy Shevchenko
70c263c42c pinctrl: intel: Introduce intel_pinctrl_probe_by_hid() internal API
Introduce intel_pinctrl_probe_by_hid() internal API to simplify drivers,
which are using ACPI _HID to distinguish which SoC data needs to be used
when being probed.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:11 +02:00
Andy Shevchenko
61db6c9db3 pinctrl: baytrail: Convert to use device_get_match_data()
Get rid of code duplication by converting to use device_get_match_data().

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:07 +02:00
Andy Shevchenko
79b7d19eba pinctrl: geminilake: Convert to use intel_pinctrl_probe_by_uid()
Get rid of code duplication by converting to use intel_pinctrl_probe_by_uid().

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:03 +02:00
Andy Shevchenko
99d9806f85 pinctrl: broxton: Convert to use intel_pinctrl_probe_by_uid()
Get rid of code duplication by converting to use intel_pinctrl_probe_by_uid().

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:24:59 +02:00
Andy Shevchenko
924cf80057 pinctrl: intel: Introduce intel_pinctrl_probe_by_uid() internal API
Introduce intel_pinctrl_probe_by_uid() internal API to simplify drivers,
which are using ACPI _UID to distinguish which SoC data needs to be used
when being probed.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:24:37 +02:00
Laurent Pinchart
2ed03c835d pinctrl: sh-pfc: r8a77990: Add DU pins, groups and function
This patch adds DU pins, groups and function for the R8A77990 (E3) SoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-30 14:17:20 +02:00
Linus Walleij
5624bf9635 Merge branch 'ib-ingenic' into devel 2018-08-29 14:10:34 +02:00
Rob Herring
94f4e54cec pinctrl: Convert to using %pOFn instead of device_node.name
In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Sean Wang <sean.wang@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Barry Song <baohua@kernel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-omap@vger.kernel.org
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 14:05:36 +02:00
Andy Shevchenko
803ceb297a pinctrl: intel: Fix a spelling typo in kernel documentation
The parameter 'community' had been spelled incorrectly.
Fix it here.

As a side effect it satisfies static checkers that issue
the following warnings:

drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Function parameter or member 'community' not described in 'intel_gpio_to_pin'
drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Excess function parameter 'commmunity' description in 'intel_gpio_to_pin'

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:50:21 +02:00
Gustavo A. R. Silva
d290e096d2 pinctrl: lpc18xx: mark expected switch fall-throughs
In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.

Addresses-Coverity-ID: 1292308 ("Missing break in switch")
Addresses-Coverity-ID: 1292309 ("Missing break in switch")
Addresses-Coverity-ID: 1309546 ("Missing break in switch")
Addresses-Coverity-ID: 1357369 ("Missing break in switch")
Addresses-Coverity-ID: 1357389 ("Missing break in switch")
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:47:16 +02:00
Linus Walleij
28d6eeb4f0 pinctrl: ingenic: Include the right header
This is a GPIO driver so only include <linux/gpio/driver.h>

Cc: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:39:54 +02:00
Paul Cercueil
57e2143473 gpio: ingenic: Remove driver
The pinctrl-ingenic driver is now handling the GPIO chips directly.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:38:20 +02:00
Paul Cercueil
635c20a1fa pinctrl: ingenic: Drop dependency on MACH_INGENIC
Depending on MACH_INGENIC prevent us from creating a generic kernel that
works on more than one MIPS board. Instead, we just depend on MIPS being
set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:37:59 +02:00
Paul Cercueil
f2a967658a pinctrl: ingenic: Add support for the JZ4725B
Add support for the JZ4725B and compatible SoCs from Ingenic.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:37:35 +02:00
Paul Cercueil
ebd6651418 pinctrl: ingenic: Implement .get_direction for GPIO chips
This allows to read from debugfs whether the GPIOs requested are set as
input or output.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:37:14 +02:00
Paul Cercueil
e72394e2ea pinctrl: ingenic: Merge GPIO functionality
Merge the code of the gpio-ingenic driver into the pinctrl-ingenic
driver.

The reason behind this, is that the same hardware block handles both pin
config / muxing and GPIO.

ingenic_gpio_probe() have been marked as __init, but for the most part,
the code is the exact same as what it was in the gpio-ingenic driver.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:36:48 +02:00
Paul Cercueil
4717b11f80 pinctrl: ingenic: Mark probe function as __init
By using platform_driver_probe() instead of platform_driver_register(),
we can mark the ingenic_pinctrl_probe() function as __init.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:36:23 +02:00
Paul Cercueil
556a36a71e pinctrl: ingenic: Probe driver at subsys_initcall
Using postcore_initcall() makes the driver try to initialize way too
early.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:36:02 +02:00
Paul Cercueil
890e48be8d dt-bindings: pinctrl: Update pinctrl-ingenic for JZ4725B and GPIO merge
The pinctrl-ingenic driver now supports the JZ4725B SoC.

Furthermore, the gpio-ingenic driver was dropped and the pinctrl-ingenic
driver is now responsible for providing the GPIO functionality.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 13:35:14 +02:00
Masahiro Yamada
375fef5916 pinctrl: uniphier: drop meaningless pin from SD1 pin-mux of Pro4
The pin 327 was supposed to be used as a voltage control line for the
SD card regulator, but the SD card port1 does not support UHS-I.  It
only supports 3.3V signaling, hence this pin is pointless.

Just a note about the background.  At first, hardware engineers tried
to implement the UHS for this port.  Then, they needed to shrink the
silicon die size, and gave up the UHS, but forgot to remove the pin
assignment.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:50:12 +02:00
Richard Fitzgerald
305fa67ee4 pinctrl: madera: Fix missing space in debugfs output
The SCHMITT tag was being dumped without a separating space.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:44:27 +02:00
Richard Fitzgerald
d2f7a82204 pinctrl: madera: Return ENOTSUPP for unsupported pin attributes
The pin_config_[get|set] functions should return ENOTSUPP if
the requested attribute isn't supported.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:42:02 +02:00
Richard Fitzgerald
25cb9e5a0e pinctrl: madera: Set is_generic
We are using the generic pin configuration interface so
we can set is_generic.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:41:11 +02:00
Yixun Lan
29ae0952e8 pinctrl: meson-g12a: add pinctrl driver support
Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
A new driver is needed here due to the differences in the pins.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:34:53 +02:00
Yixun Lan
3cd3c83f67 pinctrl: Add compatibles for Amlogic Meson G12A pin controllers
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:34:53 +02:00
Tomer Maimon
3b588e43ee pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
Add Nuvoton BMC NPCM750/730/715/705 Pinmux and
GPIO controller driver.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
[Add back select GPIO_GENERIC]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:28:42 +02:00
Tomer Maimon
d0e4e8f0d6 dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton BMC
NPCM750/730/715/705 pinmux and GPIO controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 09:56:25 +02:00
Stephen Boyd
fe2731211e pinctrl: msm: Configure interrupts as input and gpio mode
When requesting a gpio as an interrupt, we should make sure to mux the
pin as the GPIO function and configure it to be an input so that various
functions or output signals don't affect the interrupt state of the pin.
So far, we've relied on pinmux configurations in DT to handle this, but
let's explicitly configure this in the code so that DT implementers
don't have to get this part right.

Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 09:42:45 +02:00
Stephen Boyd
1de7ddb3a1 pinctrl: msm: Mux out gpio function with gpio_request()
We rely on devices to use pinmuxing configurations in DT to select the
GPIO function (function 0) if they're going to use the gpio in GPIO
mode. Let's simplify things for driver authors by implementing
gpio_request_enable() for this pinctrl driver to mux out the GPIO
function when the gpio is use from gpiolib.

Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 09:41:12 +02:00