Commit Graph

14 Commits

Author SHA1 Message Date
Simon Goldschmidt
e793b284d7 arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Follow the recent trend for the license description.

This is also in an effort to fully sync the devicetrees with U-Boot.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28 09:24:52 -06:00
Jaehoon Chung
984f624e94 ARM: dts: socfpga: remove 'num-slots' property for dwmmc
Since 'num-slots' had already deprecated, remove the property in
device-tree file.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-03-15 09:27:24 +01:00
Florian Vaussard
332ddfab42 ARM: dts: socfpga: Add unit name to memory nodes
Memory nodes in Arria5, Cyclone5 and Arria10 do not have a unit name.
This will trigger several warnings like this one (when compiled with
W=1):

Node /memory has a reg or ranges property, but no unit name

Add the corresponding unit name to each node.

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Jaehoon Chung
f5bbe55a27 ARM: dts: socfpga: unuse the slot-node and deprecate the supports-highspeed for
dw-mmc

dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And "supports-highspeed" property in dw-mmc is deprecated.
"supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tushar Behera <trblinux@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-09-04 10:15:13 -05:00
Steffen Trumtrar
7da9b436d8 ARM: socfpga: dts: convert to preprocessor includes
Convert all socfpga DT files to the dtc preprocessor include syntax.
This allows to include header files in the devicetrees like other
SoC-types already do.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-05 22:33:14 -05:00
Linus Torvalds
cbda94e039 ARM: SoC: driver changes
These changes are mostly for ARM specific device drivers that either
 don't have an upstream maintainer, or that had the maintainer ask
 us to pick up the changes to avoid conflicts. A large chunk of this
 are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from
 that, reset controllers for STi as well as a large rework of the
 Marvell Orion/EBU watchdog driver are notable.
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Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Arnd Bergmann:
 "These changes are mostly for ARM specific device drivers that either
  don't have an upstream maintainer, or that had the maintainer ask us
  to pick up the changes to avoid conflicts.

  A large chunk of this are clock drivers (bcm281xx, exynos, versatile,
  shmobile), aside from that, reset controllers for STi as well as a
  large rework of the Marvell Orion/EBU watchdog driver are notable"

* tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
  Revert "net: stmmac: Add SOCFPGA glue driver"
  ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks
  ARM: STi: Add reset controller support to mach-sti Kconfig
  drivers: reset: stih416: add softreset controller
  drivers: reset: stih415: add softreset controller
  drivers: reset: Reset controller driver for STiH416
  drivers: reset: Reset controller driver for STiH415
  drivers: reset: STi SoC system configuration reset controller support
  dts: socfpga: Add sysmgr node so the gmac can use to reference
  dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
  reset: Add optional resets and stubs
  ARM: shmobile: r7s72100: fix bus clock calculation
  Power: Reset: Generalize qnap-poweroff to work on Synology devices.
  dts: socfpga: Update clock entry to support multiple parents
  ARM: socfpga: Update socfpga_defconfig
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  net: stmmac: Add SOCFPGA glue driver
  watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
  drivers: cci: Export CCI PMU revision
  ...
2014-04-05 15:37:40 -07:00
Dinh Nguyen
2755e18748 dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 01:11:46 +01:00
Arnd Bergmann
b80a6373d6 Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
This reverts commit 7e0b4cd062.

The binding changes need to be done differently as well, let's
take them through netdev, and merge the dts changes in a new
patch here.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 01:26:00 +01:00
Dinh Nguyen
9b931361ff dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.

Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Finally, fix an indentation error for the sysmgr node.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>
2014-03-09 23:11:35 -05:00
Dinh Nguyen
7e0b4cd062 dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: David S. Miller <davem@davemloft.net>
---
v3: Remove stray empty line at end of socfpga_cyclone5_socdk.dts
v2: Use the dwmac-sti as an example for a glue layer and split patch up
to have dts as a separate patch. Also cc dts maintainers since there is
a new binding.
2014-03-02 14:57:57 -06:00
Dinh Nguyen
3d954cf151 ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>

v2:
- Moved "disabled" status to dtsi file
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11 16:34:57 -07:00
Dinh Nguyen
042000b003 ARM: socfpga: Add clock entries into device tree
Adds the main PLL clock groups for SOCFPGA into device tree file
so that the clock framework to query the clock and clock rates
appropriately.

$cat /sys/kernel/debug/clk/clk_summary
   clock                        enable_cnt  prepare_cnt  rate
---------------------------------------------------------------------
 osc1                           2           2            25000000
    sdram_pll                   0           0            400000000
       s2f_usr2_clk             0           0            66666666
       ddr_dq_clk               0           0            200000000
       ddr_2x_dqs_clk           0           0            400000000
       ddr_dqs_clk              0           0            200000000
    periph_pll                  2           2            500000000
       s2f_usr1_clk             0           0            50000000
       per_base_clk             4           4            100000000
       per_nand_mmc_clk         0           0            25000000
       per_qsi_clk              0           0            250000000
       emac1_clk                1           1            125000000
       emac0_clk                0           0            125000000
    main_pll                    1           1            1600000000
       cfg_s2f_usr0_clk         0           0            100000000
       main_nand_sdmmc_clk      0           0            100000000
       main_qspi_clk            0           0            400000000
       dbg_base_clk             0           0            400000000
       mainclk                  0           0            400000000
       mpuclk                   1           1            800000000
          smp_twd               1           1            200000000

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-14 20:17:59 -07:00
Dinh Nguyen
d6dd735f4b arm: socfpga: Add SMP support for actual socfpga harware
Because the CPU1 start address is different for socfpga-vt and
socfpga-cyclone5, we add code to use the correct CPU1 start addr.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11 19:37:26 -08:00
Dinh Nguyen
c2ad284412 arm: socfpga: Add new device tree source for actual socfpga HW
Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11 19:37:19 -08:00