Commit Graph

47 Commits

Author SHA1 Message Date
Ben Wolsieffer
8554cba1d6 irqchip/stm32-exti: add missing DT IRQ flag translation
The STM32F4/7 EXTI driver was missing the xlate callback, so IRQ trigger
flags specified in the device tree were being ignored. This was
preventing the RTC alarm interrupt from working, because it must be set
to trigger on the rising edge to function correctly.

Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231003162003.1649967-1-ben.wolsieffer@hefring.com
2023-10-07 12:47:12 +01:00
Rob Herring
ee07675046 irqchip: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230714174645.4058547-1-robh@kernel.org
2023-08-21 17:49:11 +01:00
Antonio Borneo
48f31e4964 irqchip/stm32-exti: Fix warning on initialized field overwritten
While compiling with W=1, both gcc and clang complain about a
tricky way to initialize an array by filling it with a non-zero
value and then overrride some of the array elements.
In this case the override is intentional, so just disable the
specific warning for only this part of the code.

Note: the flag "-Woverride-init" is recognized by both compilers,
but the warning msg from clang reports "-Winitializer-overrides".
The doc of clang clarifies that the two flags are synonyms, so use
here only the flag name common on both compilers.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Fixes: c297493336 ("irqchip/stm32-exti: Simplify irq description table")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230601155614.34490-1-antonio.borneo@foss.st.com
2023-06-17 07:30:00 +01:00
Marek Vasut
1c51879688 irqchip/stm32-exti: Add STM32MP15xx IWDG2 EXTI to GIC map
The EXTI interrupt 46 is mapped to GIC interrupt 151. Add the
missing mapping, which is used for IWDG2 pretimeout interrupt
and wake up source.

Reviewed-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230517194349.105745-1-marex@denx.de
2023-06-17 07:25:32 +01:00
Antonio Borneo
8fc7a6198a irqchip/stm32-exti: Remove check on always false condition
The field drv_data is assigned during driver's probe, where it's
already checked to be not NULL.

Remove the always false check '!host_data->drv_data'.

This fixes a warning "variable dereferenced before check" detected
by '0-DAY CI Kernel Test Service'.

Fixes: c297493336 ("irqchip/stm32-exti: Simplify irq description table")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/lkml/202208131739.gJvcs9ls-lkp@intel.com/
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220817125758.5975-1-antonio.borneo@foss.st.com
2022-09-12 16:31:25 +01:00
Antonio Borneo
c297493336 irqchip/stm32-exti: Simplify irq description table
Having removed the event trigger type from struct stm32_desc_irq
makes worthless keep using a struct.

Replace the struct by a single dimension array and use 8 bit type
to reduce the overal memory footprint.
On armv7a this patch reduces by 7% the size of the driver, from
   text    data     bss     dec     hex filename
   6977     424       4    7405    1ced irq-stm32-exti.o
to
   6449     424       4    6877    1add irq-stm32-exti.o

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606162757.415354-7-antonio.borneo@foss.st.com
2022-07-07 09:07:44 +01:00
Antonio Borneo
ce4ef8f9f2 irqchip/stm32-exti: Read event trigger type from event_trg register
The flag reporting whether an event is 'direct' or 'configurable'
is available in the read-only registers EVENT_TRG.

Drop this redundant information from the struct stm32_desc_irq and
use the proper bit from EVENT_TRG register.
On armv7a this patch reduces by 3% the size of the driver, from
   text    data     bss     dec     hex filename
   7233     424       4    7661    1ded irq-stm32-exti.o
to
   6977     424       4    7405    1ced irq-stm32-exti.o

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606162757.415354-6-antonio.borneo@foss.st.com
2022-07-07 09:07:44 +01:00
Alexandre Torgue
b38040f016 irqchip/stm32-exti: Tag emr register as undefined for stm32mp15
The reference manual RM0436 of stm32mp15 till version v4.0 was
erroneously reporting the Event Mask Registers (EMR) for the
Cortex-A CPUs.
These registers have been removed from v5.0 of the manual and the
corresponding offsets have been marked as 'Reserved'.

Prevent accessing these reserved addresses by tagging the EMR
offsets as UNDEF_REG and modifying the code to handle this case.

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606162757.415354-5-antonio.borneo@foss.st.com
2022-07-07 09:07:44 +01:00
Antonio Borneo
c16ae60921 irqchip/stm32-exti: Prevent illegal read due to unbounded DT value
The value hwirq is received from DT. If it exceeds the maximum
valid value it causes the code to address unexisting irq chips
reading outside the array boundary.

Check the value of hwirq before using it.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606162757.415354-4-antonio.borneo@foss.st.com
2022-07-07 09:07:44 +01:00
Loic Pallardy
f8b3eb4245 irqchip/stm32-exti: Fix irq_mask/irq_unmask for direct events
The driver has to mask/unmask the corresponding flag in the
Interrupt Mask Register (IMR).
This is already done for configurable event, while direct events
only forward the mask/unmask request to the parent.

Use the existing stm32_exti_h_mask()/stm32_exti_h_unmask() for
direct events too.

Signed-off-by: Loic Pallardy <loic.pallardy@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606162757.415354-3-antonio.borneo@foss.st.com
2022-07-07 09:07:44 +01:00
Ludovic Barre
3e17683ff4 irqchip/stm32-exti: Fix irq_set_affinity return value
When there is no parent, there is no specific action to do in
stm32-exti irqchip. In such case, it's incorrect returning an
error.

Let irq_set_affinity to return IRQ_SET_MASK_OK_DONE when there is
no parent.

Signed-off-by: Ludovic Barre <ludovic.barre@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606162757.415354-2-antonio.borneo@foss.st.com
2022-07-07 09:07:44 +01:00
Alexandre Torgue
04133bb1e7 irqchip/stm32-exti: Add STM32MP13 support
Enhance stm32-exti driver to support STM32MP13 SoC. This SoC uses the same
hardware version than STM32MP15. Only EXTI line mapping is changed and
following EXTI lines are supported: GPIO, RTC, I2C[1-5], UxART[1-8],
USBH_EHCI, USBH_OHCI, USB_OTG, LPTIM[1-5], ETH[1-2].

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220202140005.860-3-alexandre.torgue@foss.st.com
2022-02-09 13:43:07 +00:00
Cai Huoqing
fd9ac236c2 irqchip/stm32: Make use of the helper function devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210908105715.1780-1-caihuoqing@baidu.com
2021-10-19 11:24:05 +01:00
Marc Zyngier
046a6ee234 irqchip: Bulk conversion to generic_handle_domain_irq()
Wherever possible, replace constructs that match either
generic_handle_irq(irq_find_mapping()) or
generic_handle_irq(irq_linear_revmap()) to a single call to
generic_handle_domain_irq().

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-06-10 13:09:19 +01:00
Zhen Lei
fbb80d5ad4 irqchip: Remove redundant error printing
When devm_ioremap_resource() fails, a clear enough error message will be
printed by its subfunction __devm_ioremap_resource(). The error
information contains the device name, failure cause, and possibly resource
information.

Therefore, remove the error printing here to simplify code and reduce the
binary size.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210511125428.6108-2-thunder.leizhen@huawei.com
2021-05-16 13:07:18 +01:00
Erwan Le Ray
e12c455055 irqchip/stm32: Add usart instances exti direct event support
Add following usart instances exti direct event support (used for UART wake
up).
- exti 26 (USART1) is mapped to GIC 37
- exti 27 (USART2) is mapped to GIC 38
- exti 28 (USART3) is mapped to GIC 39
- exti 29 (USART6) is mapped to GIC 71
- exti 31 (UART5) is mapped to GIC 53
- exti 32 (UART7) is mapped to GIC 82
- exti 33 (UART8) is mapped to GIC 83

Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210319184253.5841-4-erwan.leray@foss.st.com
2021-04-07 13:25:52 +01:00
Fabrice Gasnier
a00e85b581 irqchip/stm32-exti: Add all LP timer exti direct events support
Add all remaining LP timer exti direct events, e.g. for LP Timer 2 to 5.
LP timer 1 is already listed (e.g. exti 47).

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1602859219-15684-2-git-send-email-fabrice.gasnier@st.com
2020-10-25 12:04:13 +00:00
qiuguorui1
e579076ac0 irqchip/stm32-exti: Avoid losing interrupts due to clearing pending bits by mistake
In the current code, when the eoi callback of the exti clears the pending
bit of the current interrupt, it will first read the values of fpr and
rpr, then logically OR the corresponding bit of the interrupt number,
and finally write back to fpr and rpr.

We found through experiments that if two exti interrupts,
we call them int1/int2, arrive almost at the same time. in our scenario,
the time difference is 30 microseconds, assuming int1 is triggered first.

there will be an extreme scenario: both int's pending bit are set to 1,
the irq handle of int1 is executed first, and eoi handle is then executed,
at this moment, all pending bits are cleared, but the int 2 has not
finally been reported to the cpu yet, which eventually lost int2.

According to stm32's TRM description about rpr and fpr: Writing a 1 to this
bit will trigger a rising edge event on event x, Writing 0 has no
effect.

Therefore, when clearing the pending bit, we only need to clear the
pending bit of the irq.

Fixes: 927abfc446 ("irqchip/stm32: Add stm32mp1 support with hierarchy domain")
Signed-off-by: qiuguorui1 <qiuguorui1@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org # v4.18+
Link: https://lore.kernel.org/r/20200820031629.15582-1-qiuguorui1@huawei.com
2020-08-25 10:57:05 +01:00
Alexandre Torgue
9d6a5fe175 irqchip/stm32-exti: Map direct event to irq parent
EXTI lines are mainly used to wake-up system from CStop low power mode.
Currently, if a device wants to use a EXTI (direct) line as wakeup line,
it has to declare 2 interrupts:
 - one for EXTI used to wake-up system (with dedicated_wake_irq api).
 - one for GIC used to get the wake up reason inside the concerned IP.

This split is not really needed as each EXTI line is actually "linked " to
a GIC. So to avoid this useless double interrupt management in each
wake-up driver, this patch lets the STM32 EXTI driver abstract it by
mapping each EXTI line to his corresponding GIC.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200717140717.29606-1-alexandre.torgue@st.com
2020-07-27 08:55:04 +01:00
Fabien Dessenne
5257169ade irqchip/stm32-exti: Use the hwspin_lock_timeout_in_atomic() API
Now that the hwspin_lock_timeout_in_atomic() API is available use it.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200706081115.25180-1-alexandre.torgue@st.com
2020-07-27 08:55:02 +01:00
Alexandre Torgue
25591d4c64 irqchip/stm32: Add irq retrigger support
This commit introduces retrigger support for stm32_ext_h chip.
It consists to rise the GIC interrupt mapped to an EXTI line.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20200219143229.18084-2-alexandre.torgue@st.com
2020-03-08 14:25:45 +00:00
Fabien Dessenne
cfbf9e4970 irqchip/stm32: Use a platform driver for stm32mp1-exti device
This irqchip driver uses the hwspinlock framework (coprocessor HW regs
access concurrency) for the stm32mp1-exti device.
Hence, this driver needs to handle the hwspinlock driver dependency
using the deferred probe mechanism which requires to move this driver
into a platform one with a probe() ops.
This applies only for the device which is "st,stm32mp1-exti" compatible,
the management of the other devices (st,stm32h7-exti / st,stm32-exti) is
kept unchanged (use IRQCHIP_DECLARE)

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-29 15:45:01 +01:00
Thomas Gleixner
3ce8461f45 irqchip updates for 5.1, take #2
- irqsteer error handling fix
 - GICv3 range coalescing fix
 - stm32 coprocessor coexistence fixes
 - mbigen MSI teardown fix
 - non-DT secondary GIC infrastructure removed
 - various cleanups (brcmstb-l2, mmp)
 - new DT bindings (r8a774c0)
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlyTciIVHG1hcmMuenlu
 Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDHbUP/1ndbJE6O5S24YqbeffNc3dr6hka
 zyYpzY63KtS39TWxrLmZJlXkMecSXlY4QN3FqZd+g81p+E5zUlZ+PklqFYG6pBSj
 6lHsXp4Bo20IAKJTG+4g9K3Am+i3FNoglB2ROPLF4A6pAVvyDWJL0CXCwHG8gLsS
 NbjDIQpcKRFOGO4qdsTNRYjEVaadShz7koLeQQJ8w/Cnraq8u7ETtAq7irmYv/c6
 PX0MUfl12FtqsGZR+xC5th1PYBq5I7E/BsGNnABf9dREpUD4b0IgFV2yPg0r+mMd
 rSU7OZXWv+JLsQuK4FvHdlM1w7d/g5awG67Mt84eScU4LxjVV68MWtsj0WtNpIOp
 sCiQZ9tifBz1C2K/6iXoRLEYbrzUFOyGQX9AZXKoXqCB4eu1ZUKT7zeTtFYxIdPO
 jc9vGT2v7zlKsEpuj5BJEsNSRUJcGZgC7CQvJTxYWLbu7henpPkh6nf/PkbrDKIB
 HtuSygju1YzMH4imvZoVuhB60Bii6ZExVy6a4STYcUJu+Qj8/kyF6sHuZv4YMUnm
 yKGcXxAQE2C2SdYfGl2u0JradMB4kPU1+2uA7uOq/kTxcm30nGJ/YcYYEL/BaXt9
 Clg7WNiTSB6NOrYLhPYOfGa1NwniFTvZWeo9C61o4gslNLukXG885U9swo+NXPYq
 UlJduzmQ0kDJ00ne
 =SBUi
 -----END PGP SIGNATURE-----

Merge tag 'irqchip-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip updates for 5.1 from Marc Zyngier:

 - irqsteer error handling fix
 - GICv3 range coalescing fix
 - stm32 coprocessor coexistence fixes
 - mbigen MSI teardown fix
 - non-DT secondary GIC infrastructure removed
 - various cleanups (brcmstb-l2, mmp)
 - new DT bindings (r8a774c0)
2019-03-21 12:30:54 +01:00
Fabien Dessenne
6a77623d78 irqchip/stm32: Don't set rising configuration registers at init
The rising configuration status register (rtsr) is not banked.
As it is shared with the co-processor, it should not be written at probe
time, else the co-processor configuration will be lost.

Fixes: f9fc174550 ("irqchip/stm32: Add host and driver data structures")
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-03-21 11:08:26 +00:00
Fabien Dessenne
0dda09666f irqchip/stm32: Don't clear rising/falling config registers at init
Falling and rising configuration and status registers are not banked.
As they are shared with M4 co-processor, they should not be cleared
at probe time, else M4 co-processor configuration will be lost.

Fixes: f9fc174550 ("irqchip/stm32: Add host and driver data structures")
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-03-21 11:08:25 +00:00
Loic Pallardy
1d47f48bf2 irqchip/stm32-exti: Add domain translate function
Domain translate function is needed to recover irq
configuration parameters from DT node

Fixes: 927abfc446 ("irqchip/stm32: Add stm32mp1 support with hierarchy domain")
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-01-17 16:51:59 +00:00
Benjamin Gaignard
fb94109b76 irqchip/stm32: protect configuration registers with hwspinlock
If a hwspinlock is defined in device tree use it to protect
configuration registers.

Do not request for hwspinlock during the exti driver init since the
hwspinlock driver is not probed yet at that stage and the exti driver
does not support deferred probe.
Instead of this, postpone the hwspinlock request at the first time the
hwspinlock is actually needed.

Use the hwspin_trylock_raw() API which is the most appropriated here
Indeed:
- hwspin_lock_() calls are under spin_lock protection (chip_data->rlock
  or gc->lock).
- the _timeout() API relies on jiffies count which won't work if IRQs
  are disabled which is the case here (a large part of the IRQ setup is
  done atomically (see irq/manage.c))
As a consequence implement the retry/timeout lock from here. And since
all of this is done atomically, reduce the timeout delay to 1 ms.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-12-18 15:38:31 +00:00
Yangtao Li
f9c75bca44 irqchhip: Convert to using %pOFn instead of device_node.name
In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-12-13 09:35:56 +00:00
Thomas Gleixner
20b420dc42 irqchip updates for 4.19, take #2
- bcm7038: compilation fix for !SMP
 - stm32: fix teardown on probe error
 - s3c24xx: fix compilation warning
 - renesas-irqc: r8a774a1 support
 - tango: chained irq setup simplification
 - gic-v3: allow wake-up sources
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAluAC8YVHG1hcmMuenlu
 Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDsvgP/1LWT1TS/mnxhfo71yueEI75X3Ju
 ZKQ8Za5o6nbu2CvwedEOtPVfAqp5Mg3wNJZKiN4H0db3dxftzqqp7ZQ1P7ZtheZC
 69k0DKXQKN2BXURX3zDHhYA86kjrRcUEJfjF8Wi8Pe1UjrO4lm7fQZEVg9SiSigx
 TxFOakeSlHZqrC0DwEj5P7RpyAQhqb/7ygg9TNjlNgda8F98RmUNm38nEUj+IbPK
 UySYnHTe02Z5nD/9K+piB8gFgpTIfQlhWPA/kgODlsCJUuUY18RkB0CZzRuUBv3a
 58qqpopuvH1jEVqWi3ffXr6m1kPF7Ys8GACC0laH2QgArT5OSGet9Hn7Edo5qh1p
 UPdvJEpuIsgQc1nPEcw84h1SGYg2lEtY0ZR4FdDnh3QQ45Kbkhx0HWLM/14YU/wI
 jutiUAZ7BstdlRwzmjNWwcW2pjhE3/FDBUTifQb/qvh4MEM9Mi4Jr3XARSTuW8o5
 zZXmm47sOomuDl8RyIKvPuQRhmnN0ix86dba0bMIMYx2G9dRjb51o9gfN1nY/E6C
 bWayUZNmSaMAPi+xXBSw+O9mIqg2mwlLzq4EIKMHRUyMBqNL3mFIaefgT5yOLgMG
 98Co+VLgpnp7eraAmHJWLrdf4QhiMD+cHkOD41s5eu0E+BGKLWS/cZdROa4jvucs
 1JzPGTd0o4PHd5vV
 =Mr5O
 -----END PGP SIGNATURE-----

Merge tag 'irqchip-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip updates for 4.19, take #2 from Marc Zyngier:

 - bcm7038: compilation fix for !SMP
 - stm32: fix teardown on probe error
 - s3c24xx: fix compilation warning
 - renesas-irqc: r8a774a1 support
 - tango: chained irq setup simplification
 - gic-v3: allow wake-up sources
2018-08-24 16:06:42 +02:00
Dan Carpenter
4096165d55 irqchip/stm32: Fix init error handling
If there are any errors in stm32_exti_host_init() then it leads to a
NULL dereference in the callers.  The function should clean up after
itself.

Fixes: f9fc174550 ("irqchip/stm32: Add host and driver data structures")
Reviewed-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-08-13 09:03:44 +01:00
Ludovic Barre
6bdd0299cf irqchip/stm32: Add exti0 translation for stm32mp1
This patch fixes a datasheet issue, in the draft version the "exti0"
was not connected whereas is it.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-07-19 16:12:27 +01:00
Arnd Bergmann
a84277bf3e irqchip/stm32: Fix non-SMP build warning
A CONFIG_SMP=n build emits a harmless compile-time warning:

drivers/irqchip/irq-stm32-exti.c:495:12: error: 'stm32_exti_h_set_affinity' defined but not used [-Werror=unused-function]

The #ifdef is inconsistent here, and it's better to use an IS_ENABLED() check
that lets the compiler silently drop that function.

Fixes: 927abfc446 ("irqchip/stm32: Add stm32mp1 support with hierarchy domain")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ludovic Barre <ludovic.barre@st.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lkml.kernel.org/r/20180605114347.1347128-1-arnd@arndb.de
2018-06-06 12:05:19 +02:00
Ludovic Barre
73958b31c1 irqchip/stm32: Add suspend/resume support for hierarchy domain
This patch adds suspend/resume feature for exti hierarchy domain.
-suspend function sets wake_active into imr of each banks
-resume function restores the mask_cache interrupt into
 imr of each banks

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:22 +01:00
Ludovic Barre
927abfc446 irqchip/stm32: Add stm32mp1 support with hierarchy domain
Exti controller has been differently integrated on stm32mp1 SoC.
A parent irq has only one external interrupt. A hierachy domain could
be used. Handlers are call by parent, each parent interrupt could be
masked and unmasked according to the needs.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:22 +01:00
Ludovic Barre
5a2490e029 irqchip/stm32: Prepare common functions
This patch prepares functions which could be reused by
next variant of stm32 exti controller.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:21 +01:00
Ludovic Barre
f9fc174550 irqchip/stm32: Add host and driver data structures
This patch adds host and driver data structures to support
different stm32 exti controllers with variants.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:21 +01:00
Ludovic Barre
d9e2b19b02 irqchip/stm32: Add suspend support
This patch adds suspend feature.
-Use default irq_set_wake function to store wakeup request.
-Suspend function set wake_active into imr of each bank
 and save rising/falling trigger registers.
-Resume function restore the mask_cache interrupt into
 imr of each bank and restore rising/falling trigger registers.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:20 +01:00
Ludovic Barre
be6230f0c2 irqchip/stm32: Add falling pending register support
This patch adds support of rising/falling pending registers.
Falling pending register (fpr) is needed for next revision.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:20 +01:00
Ludovic Barre
ea80aa2a1a irqchip/stm32: Checkpatch fix
-WARNING: struct irq_domain_ops should normally be const
-CHECK: Alignment should match open parenthesis

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:20 +01:00
Radoslaw Pietrzyk
ff78716d43 irqchip/stm32: Optimizes and cleans up stm32-exti irq_domain
- In stm32_exti_alloc function, discards irq_domain_set_info
  with handle_simple_irq. This overwrite the setting defined while init
  of generic chips. Exti controller manages edge irq type.
- Removes acking in chained irq handler as this is done by
  irq_chip itself inside handle_edge_irq
- removes unneeded irq_domain_ops.xlate callback

Acked-by: Ludovic Barre <ludovic.barre@st.com>
Tested-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:37:54 +01:00
Benjamin Gaignard
8de50dc262 irqchip/stm32: Fix copyright
Uniformize STMicroelectronics copyrights header and add SPDX identifier

CC: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20171130084500.23439-1-benjamin.gaignard@st.com
2018-01-29 16:24:53 +01:00
Ludovic Barre
90af7c254f irqchip/stm32: Move the wakeup on interrupt mask
Move irq_set_wake on interrupt mask, needed to wake up from
low power mode as the event mask is not able to do so.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:43 +00:00
Ludovic Barre
2ca6b9bcaa irqchip/stm32: Fix initial values
-After cold boot, imr default value depends on hardware configuration.
-After hot reboot the registers must be cleared to avoid residue.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:35 +00:00
Ludovic Barre
539c603e14 irqchip/stm32: Add stm32h7 support
stm32h7 has up to 96 inputs
(3 banks of 32 inputs max).

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:28 +00:00
Ludovic Barre
6dd64ee17e irqchip/stm32: Add multi-bank management
-Prepare to manage multi-bank of external interrupts
(N banks of 32 inputs).
-Prepare to manage registers offsets by compatible
(registers offsets could be different follow per stm32 platform).

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:06 +00:00
Rob Herring
e81f54c668 irqchip: Convert to using %pOF instead of full_name
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Lee Jones <lee@kernel.org>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-tegra@vger.kernel.org
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-08-23 10:09:28 +01:00
Alexandre TORGUE
e072041688 drivers/irqchip: Add STM32 external interrupts support
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Originally-from: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: arnd@arndb.de
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: bruherrera@gmail.com
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: lee.jones@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1474387259-18926-3-git-send-email-alexandre.torgue@st.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-09-21 14:13:21 +02:00