Commit Graph

2 Commits

Author SHA1 Message Date
Chen-Yu Tsai
178ca5312a clk: sunxi-ng: mux: Increase fixed pre-divider div size
Some clocks have a predivider value that is larger than what u8 can
store. One such example is the OUT clk found on A20/A31, which has
a /750 pre-divider on one of the osc24M parents.

Increase the size of the div field to u16.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08 20:03:20 +02:00
Maxime Ripard
2a65ed42dc clk: sunxi-ng: Add mux clock support
Some clocks in the Allwinner SoCs clocks unit are just muxes.

However, those muxes might also be found in some other complicated clocks
that would benefit from the code in there to deal with "advanced" features,
like pre-dividers.

Introduce a set of helpers to reduce the code duplication in such cases.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-6-maxime.ripard@free-electrons.com
2016-07-08 18:04:42 -07:00