CONFIG_SM_GCC_8650 depends on ARM64 but it is selected by
CONFIG_SM_GPUCC_8650, which can be selected on ARM, resulting in a
Kconfig warning.
WARNING: unmet direct dependencies detected for SM_GCC_8650
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n])
Selected by [y]:
- SM_GPUCC_8650 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y]
Add the same dependencies to CONFIG_SM_GPUCC_8650 to resolve the
warning.
Fixes: 8676fd4f38 ("clk: qcom: add the SM8650 GPU Clock Controller driver")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240318-fix-some-qcom-kconfig-deps-v1-2-ea0773e3df5a@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
CONFIG_SC_GCC_8280XP depends on ARM64 but it is selected by
CONFIG_SC_CAMCC_8280XP, which can be selected on ARM, resulting in a
Kconfig warning.
WARNING: unmet direct dependencies detected for SC_GCC_8280XP
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n])
Selected by [y]:
- SC_CAMCC_8280XP [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y]
Add the same dependencies to CONFIG_SC_CAMCC_8280XP to resolve the
warning.
Fixes: ff93872a9c ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240318-fix-some-qcom-kconfig-deps-v1-1-ea0773e3df5a@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
On SM8650 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display af54000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 9e939f0083 ("clk: qcom: add the SM8650 Display Clock Controller driver")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-4-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
On SM8550 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 90114ca114 ("clk: qcom: add SM8550 DISPCC driver")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-3-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
On SM6350 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 837519775f ("clk: qcom: Add display clock controller driver for SM6350")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-2-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
On SM8450 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 16fb89f92e ("clk: qcom: Add support for Display Clock Controller on SM8450")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-1-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The register map used for 'cbf_pll' is the same as the one defined for
the CLK_ALPHA_PLL_TYPE_HUAYRA_APSS indice in the 'clk_alpha_pll_regs'
array.
Drop the local register map and use the global one instead to reduce
code duplication.
No functional changes intended. Compile tested only.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-5-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The clk_init_data structures are never modified, so add const
qualifier to the ones where it is missing.
No functional changes.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-4-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The match data structures are used only by the apss_ipq_pll_probe()
function and are never modified so mark those as constant.
No functional changes.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-3-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Move the locally defined Huayra register map to 'clk_alpha_pll_regs'
in order to allow using that by other drivers, like the clk-cbf-8996.
No functional changes.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-2-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The register offset array defined locally for the
CLK_ALPHA_PLL_TYPE_STROMER_PLUS is the same as the
entry defined for CLK_ALPHA_PLL_TYPE_STROMER in the
'clk_alpha_pll_regs' array.
To avoid code duplication, remove the local definition
and use the global one instead.
No functional changes.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-1-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Booting v6.8 results in a hang on various IPQ5018 based boards.
Investigating the problem showed that the hang happens when the
clk_alpha_pll_stromer_plus_set_rate() function tries to write
into the PLL_MODE register of the APSS PLL.
Checking the downstream code revealed that it uses [1] stromer
specific operations for IPQ5018, whereas in the current code
the stromer plus specific operations are used.
The ops in the 'ipq_pll_stromer_plus' clock definition can't be
changed since that is needed for IPQ5332, so add a new alpha pll
clock declaration which uses the correct stromer ops and use this
new clock for IPQ5018 to avoid the boot failure.
Also, change pll_type in 'ipq5018_pll_data' to
CLK_ALPHA_PLL_TYPE_STROMER to better reflect that it is a Stromer
PLL and change the apss_ipq_pll_probe() function accordingly.
1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c#L67
Cc: stable@vger.kernel.org
Fixes: 50492f9294 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Tested-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20240315-apss-ipq-pll-ipq5018-hang-v2-1-6fe30ada2009@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Rework nss_port5/6 to use the new multiple configuration implementation
and correctly fix the clocks for these port under some corner case.
This is particularly relevant for device that have 2.5G or 10G port
connected to port5 or port 6 on ipq8074. As the parent are shared
across multiple port it may be required to select the correct
configuration to accomplish the desired clock. Without this patch such
port doesn't work in some specific ethernet speed as the clock will be
set to the wrong frequency as we just select the first configuration for
the related frequency instead of selecting the best one.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20231220221724.3822-4-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Some RCG frequency can be reached by multiple configuration.
Add clk_rcg2_fm_ops ops to support these special RCG configurations.
These alternative ops will select the frequency using a CEIL policy.
When the correct frequency is found, the correct config is selected by
calculating the final rate (by checking the defined parent and values
in the config that is being checked) and deciding based on the one that
is less different than the requested one.
These check are skipped if there is just one config for the requested
freq.
qcom_find_freq_multi is added to search the freq with the new struct
freq_multi_tbl.
__clk_rcg2_select_conf is used to select the correct conf by simulating
the final clock.
If a conf can't be found due to parent not reachable, a WARN is printed
and -EINVAL is returned.
Tested-by: Wei Lei <quic_leiwei@quicinc.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20231220221724.3822-3-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Some RCG frequency can be reached by multiple configuration.
We currently declare multiple configuration for the same frequency but
that is not supported and always the first configuration will be taken.
These multiple configuration are needed as based on the current parent
configuration, it may be needed to use a different configuration to
reach the same frequency.
To handle this introduce 3 new macro, C, FM and FMS:
- C is used to declare a freq_conf where src, pre_div, m and n are
provided.
- FM is used to declare a freq_multi_tbl with the frequency and an
array of confs to insert all the config for the provided frequency.
- FMS is used to declare a freq_multi_tbl with the frequency and an
array of a single conf with the provided src, pre_div, m and n.
Struct clk_rcg2 is changed to add a union type to reference a simple
freq_tbl or a complex freq_multi_tbl.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20231220221724.3822-2-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
It doesn't appear that the configuration is for the HFPLL is generic, so
add a qcs404-specific compatible and rename the existing struct to
qcs404.
Keep qcom,hfpll in the driver for compatibility with old dtbs.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20240218-hfpll-yaml-v2-2-31543e0d6261@z3ntu.xyz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add missing descriptions of the 'num_vco' and 'flags' members to
clk_alpha_pll structure's documentation. Also reorder the member
description entries to match the order of the declarations.
Eliminates the following warnings:
drivers/clk/qcom/clk-alpha-pll.h:72: info: Scanning doc for struct clk_alpha_pll
drivers/clk/qcom/clk-alpha-pll.h:91: warning: Function parameter or struct member 'num_vco' not described in 'clk_alpha_pll'
drivers/clk/qcom/clk-alpha-pll.h:91: warning: Function parameter or struct member 'flags' not described in 'clk_alpha_pll'
No functional changes.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240321-alpha-pll-kerneldoc-v1-1-0d76926b72c3@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The register offset arrays are ordered based on the register
offsets for all PLLs but the Stromer. For consistency, reorder
the Stromer specific array as well.
No functional changes.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240311-alpha-pll-stromer-cleanup-v1-2-f7c0c5607cca@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The offset of the CONFIG_CTL_U register defined for the Stromer
PLL is wrong. It is not aligned on a 4 bytes boundary which might
causes errors in regmap operations.
Maybe the intention behind of using the 0xff value was to indicate
that the register is not implemented in the PLL, but this is not
verified anywhere in the code. Moreover, this value is not used
even in other register offset arrays despite that those PLLs also
have unimplemented registers.
Additionally, on the Stromer PLLs the current code only touches
the CONFIG_CTL_U register if the result of pll_has_64bit_config()
is true which condition is not affected by the change.
Due to the reasons above, simply remove the CONFIG_CTL_U entry
from the Stromer specific array.
Fixes: e47a4f55f2 ("clk: qcom: clk-alpha-pll: Add support for Stromer PLLs")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240311-alpha-pll-stromer-cleanup-v1-1-f7c0c5607cca@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The PLL0 is configured by the bootloader and is the parent of the
mdp_clk_src. The Trion implementation of the configure function is
already skipping this step if the PLL is enabled, so lets extend the
same behavior to Lucid Evo variant.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20240418-clk-qcom-lucid-evo-skip-configuring-enabled-v1-1-caede5f1c7a3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded
based on the alias from of_device_id table. Clocks are considered core
components, so usually they are built-in, however these can be built and
used as modules on some generic kernel.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240410155356.224098-1-krzk@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
These are changes that for some reason ended up not making it into the
first four branches but that should still make it into 6.9:
- A rework of the omap clock support that touches both drivers and
device tree files
- The reset controller branch changes that had a dependency on late
bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
drivers branch
- The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
changes that got delayed and needed some extra time in linux-next
for wider testing.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmX5vYcACgkQYKtH/8kJ
UiemkhAAu2lYNpttx+qVlEzQvPKyID5Y+E0cVRmM5e79/fOumNomSzFwtKztCbz2
PV1CHwmDYANKsI8tl91PAe8PzD+9Er+8xa6YYVSMG5bLC2aGdF4k5hzMnRmfhlDe
uRT/9iNH0w+S1p44+wXI9Y++uZhxJtCqa6kytxybl6YrG2/l3Wm0PVcMAD/MWT1l
OULRg5gv3+7qHLKE0ffd0J7I7zCvKA5cEqnieGSO8+k1jsOE3BvgLttfPUuUsi3x
8yWAJ2cEv293Cao8x8rw39TYIHQOznLMNzK/GCIemL4k9TafbGbuVPUGQZ6oX1SQ
+/biiUV8CMLzanw2Ds7piQ/4J8EoJjh7jCf9pETORlHLaCMQaYUk4I2KnBWmjxuO
QBy6Py68EkyT1zv7YFkpdxeABkwkrObMmVsjfyltd2lCF6oC+xbIw5IOVPgnUiTc
WANL3y+hS5zv+ABmpkRhDPe9KrcoO95sJgGaoMPatwD1/2JkdV7EkvbXWdnipb1w
REYk4xuRlJcAgyjc5nrQXR8FuPX63c08NFkOw+AInFV8ipyH+8nkesb0w54aegsR
Tihhl0WUxk/e9FLFVlPiYRNdyqOb2HKteRwRxsA1LqqcWdpYjplBrkZhHb3+ESnP
lQaQ7AtZRoIjwsImYen3M2W1cFS214BAqoonLLYSd0ponCB05Ng=
=IzoE
-----END PGP SIGNATURE-----
Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more ARM SoC updates from Arnd Bergmann:
"These are changes that for some reason ended up not making it into the
first four branches but that should still make it into 6.9:
- A rework of the omap clock support that touches both drivers and
device tree files
- The reset controller branch changes that had a dependency on late
bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
drivers branch
- The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
changes that got delayed and needed some extra time in linux-next
for wider testing"
* tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
soc: fsl: dpio: fix kcalloc() argument order
bus: ts-nbus: Improve error reporting
bus: ts-nbus: Convert to atomic pwm API
riscv: dts: starfive: jh7110: Add camera subsystem nodes
ARM: bcm: stop selecing CONFIG_TICK_ONESHOT
ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
clk: ti: Improve clksel clock bit parsing for reg property
clk: ti: Handle possible address in the node name
dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
dt-bindings: riscv: cpus: reg matches hart ID
reset: Instantiate reset GPIO controller for shared reset-gpios
reset: gpio: Add GPIO-based reset controller
cpufreq: do not open-code of_phandle_args_equal()
of: Add of_phandle_args_equal() helper
reset: simple: add support for Sophgo SG2042
dt-bindings: reset: sophgo: support SG2042
riscv: dts: microchip: add specific compatible for mpfs pdma
riscv: dts: microchip: add missing CAN bus clocks
ARM: brcmstb: Add debug UART entry for 74165
...
some more devm helpers and we seem to be going in the direction of "just turn
this stuff on already and leave me alone!" with the addition of a
devm_clk_bulk_get_all_enable() API. I'm hoping that we can make that into a
genpd that drivers attach instead, but this API should help drivers simplify in
the meantime.
Outside of the devm wrappers, we've got the usual clk driver updates that are
dominated by the major phone SoC vendors (Samsung and Qualcomm) and the
non-critical driver fixes for things like incorrect topology descriptions and
wrong registers or bit fields. More details are below, but I'd say that it
looks pretty ordinary. The only thing that really jumps out at me is the
Renesas clk driver that's ignoring clks that are assigned to remote processors
in DeviceTree. That's a new feature that they're using to avoid marking clks as
CLK_IGNORE_UNUSED based on the configuration of the system.
Core:
- Increase dev_id len for clkdev lookups
- Add a devm_clk_bulk_get_all_enable() API to get and enable all clks
for a device
- Add a devm variant of clk_rate_exclusive_get()
New Drivers:
- Display, TCSR, GPU, and Camera clock controllers for Qualcomm's X1 Elite SoC
- Google GS101 PERIC0 and PERIC1 clock controllers
- Exynos850 PDMA clocks
- Exynos850 CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock controllers
Removed Drivers:
- Remove the unused Qualcomm sc7180 modem clk driver
Updates:
- Fix some static checker errors in the Hisilicon clk driver
- Polarfire MSSPLL hardware has 4 output clocks (the driver supported
previously only one output); each of these 4 outputs feed dividers and the
output of each divider feed individual hardware blocks (e.g. CAN, Crypto,
eMMC); individual hardware block drivers need to control their clocks thus
clock driver support was added for all MSSPLL output clocks
- Typo fixes in the Qualcomm IPQ5018 GCC driver
- Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi
- Properly terminate frequency tables in different Qualcomm clk drivers
- Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953
- Add missing UFS CLKREF clks on Qualcomm SC8180X
- Avoid significant delays during boot by adding a softdep on rpmhpd to
Qualcomm SDM845 gcc driver
- Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC driver
- Fix the custom GPU GX "do-nothing" method in the Qualcomm GDSC driver
- Add an external regulator to GX GDSC on Qualcomm SC8280XP GPU clk driver
- Switch display, GPU, video, and camera Qualcomm clk drivers to
module_platform_driver()
- Set a longer delay for Venus resets on many Qualcomm SoCs
- Correct the GDSC wait times in the Qualcomm SDM845 display clk driver
- Fix clock listing Oops on Amlogic axg
- New pll-rate for Rockchip rk3568
- i2s rate improvements for Rockchip rk3399
- Rockchip rk3588 syscon clock fixes and removal of overall clock-number from
the rk3588 binding header
- A prerequisite for later improvements to the Rockchip rk3588 linked clocks
- Minor clean-ups and error handling improvements in both composite-8m and SCU
i.MX clock drivers
- Fix for SAI_MCLK_SEL definition for i.MX8MP
- Register the Samsung CMU MISC clock controller earlier, so the Multi Core
Timer clocksource can use it on Google GS101
- Propagate Exynos850 SPI IPCLK rate change to parents, so the SPI will get
proper clock rates
- Refactor the generic Samsung CPU clock controllers code, preparing it for
supporting Exynos850 CPU clocks
- Fix some clk kerneldoc warnings
- Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on Renesas
R-Car V4M
- Ignore all clocks which are assigned to a non-Linux system in the Renesas
clk driver
- Add watchdog clock on Renesas RZ/G3S
- Add camera (CRU) clock and reset on Renesas RZ/G2UL
- Add support for the Renesas R-Car V4M (R8A779H0) SoC
- Convert some clk bindings to YAML so they can be validated
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmXzUpURHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSXEvQ/+K0Llv6Jgs/VJkg086qE7z82KvIQRUasi
Rhxtq8P9DS4KYBd1BB0Wwsrh2CyW9ZWUn0unQ1ZtbxCHKE1lweYb4UkafNamRynT
cKlXR5wGNtbHUF6Gmdjw+lkuF6pxj3ZcmV47bQyhLMctndWn434sIn3gpv2pTYF2
Q/ZwhhiS2ZQU1hdpgHwe9iIRJ7QcGlWKyhRx9m5QSRIL7eZFiUvBcYNAdoSa1ovr
FZOSUAUaxxDu16VrC8mPjaMQ3lDqz8DVSw3i1cDsMdYHbBidzlNLzBH9L+qFgXng
cYqYR3dlJ6HuXr9wwwe5X3Pm01VZ6Askl16h9tUnZgtZuSuxMPeWMw2brZZPNFOn
L0SvHdLFj4MzyhgXWtQughttzdOwaRP9lNZNZwchMU5aEU0e3GDeBUBeJ0CRAAqD
DHRYQW3vDlIG4mhrr54GgQ5XjeHqj9W5OrGU/dWmBp+/e1wB3MB47UJf0GJ7F9kA
BNvMFtk9hRJkmqsKY93mWpKOe3su2Fl/1vlhK9Tw5V8h/GzBnEsVDUNRYaRaN+wd
gYTEo73T2FJ4OSYncRDeSPXTmKeI2+4sa1XJKx8rasEZNOR2V3DH/8bMXZhjSbzL
nZDh+eu0uyS6+xVReE6349ivSPyNDEXO0IbI7yq7jjSYB+LxW49O2xMeoYuNSjtz
RxKHQr0skqs=
=rRIa
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Not a ton of stuff happening in the clk framework. We got some more
devm helpers and we seem to be going in the direction of "just turn
this stuff on already and leave me alone!" with the addition of a
devm_clk_bulk_get_all_enable() API. I'm hoping that we can make that
into a pmdomain that drivers attach instead, but this API should help
drivers simplify in the meantime.
Outside of the devm wrappers, we've got the usual clk driver updates
that are dominated by the major phone SoC vendors (Samsung and
Qualcomm) and the non-critical driver fixes for things like incorrect
topology descriptions and wrong registers or bit fields. More details
are below, but I'd say that it looks pretty ordinary. The only thing
that really jumps out at me is the Renesas clk driver that's ignoring
clks that are assigned to remote processors in DeviceTree. That's a
new feature that they're using to avoid marking clks as
CLK_IGNORE_UNUSED based on the configuration of the system.
Core:
- Increase dev_id len for clkdev lookups
- Add a devm_clk_bulk_get_all_enable() API to get and enable all clks
for a device
- Add a devm variant of clk_rate_exclusive_get()
New Drivers:
- Display, TCSR, GPU, and Camera clock controllers for Qualcomm's X1
Elite SoC
- Google GS101 PERIC0 and PERIC1 clock controllers
- Exynos850 PDMA clocks
- Exynos850 CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock
controllers
Removed Drivers:
- Remove the unused Qualcomm sc7180 modem clk driver
Updates:
- Fix some static checker errors in the Hisilicon clk driver
- Polarfire MSSPLL hardware has 4 output clocks (the driver supported
previously only one output); each of these 4 outputs feed dividers
and the output of each divider feed individual hardware blocks
(e.g. CAN, Crypto, eMMC); individual hardware block drivers need to
control their clocks thus clock driver support was added for all
MSSPLL output clocks
- Typo fixes in the Qualcomm IPQ5018 GCC driver
- Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi
- Properly terminate frequency tables in different Qualcomm clk
drivers
- Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953
- Add missing UFS CLKREF clks on Qualcomm SC8180X
- Avoid significant delays during boot by adding a softdep on rpmhpd
to Qualcomm SDM845 gcc driver
- Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC
driver
- Fix the custom GPU GX "do-nothing" method in the Qualcomm GDSC
driver
- Add an external regulator to GX GDSC on Qualcomm SC8280XP GPU clk
driver
- Switch display, GPU, video, and camera Qualcomm clk drivers to
module_platform_driver()
- Set a longer delay for Venus resets on many Qualcomm SoCs
- Correct the GDSC wait times in the Qualcomm SDM845 display clk
driver
- Fix clock listing Oops on Amlogic axg
- New pll-rate for Rockchip rk3568
- i2s rate improvements for Rockchip rk3399
- Rockchip rk3588 syscon clock fixes and removal of overall
clock-number from the rk3588 binding header
- A prerequisite for later improvements to the Rockchip rk3588 linked
clocks
- Minor clean-ups and error handling improvements in both
composite-8m and SCU i.MX clock drivers
- Fix for SAI_MCLK_SEL definition for i.MX8MP
- Register the Samsung CMU MISC clock controller earlier, so the
Multi Core Timer clocksource can use it on Google GS101
- Propagate Exynos850 SPI IPCLK rate change to parents, so the SPI
will get proper clock rates
- Refactor the generic Samsung CPU clock controllers code, preparing
it for supporting Exynos850 CPU clocks
- Fix some clk kerneldoc warnings
- Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
Renesas R-Car V4M
- Ignore all clocks which are assigned to a non-Linux system in the
Renesas clk driver
- Add watchdog clock on Renesas RZ/G3S
- Add camera (CRU) clock and reset on Renesas RZ/G2UL
- Add support for the Renesas R-Car V4M (R8A779H0) SoC
- Convert some clk bindings to YAML so they can be validated"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
clk: zynq: Prevent null pointer dereference caused by kmalloc failure
clk: fractional-divider: Use bit operations consistently
clk: fractional-divider: Move mask calculations out of lock
clk: Fix clk_core_get NULL dereference
clk: starfive: jh7110-vout: Convert to platform remove callback returning void
clk: starfive: jh7110-isp: Convert to platform remove callback returning void
clk: imx: imx8-acm: Convert to platform remove callback returning void
clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset
clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk'
clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk'
clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc
clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays
clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays
clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays
clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays
clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays
clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays
clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays
clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe()
clk: Add a devm variant of clk_rate_exclusive_get()
...
Highlights:
- acer-wmi: New HW support
- amd/pmf: Support for new revision of heartbeat notify
- asus-wmi: Correctly handle HW without LEDs
- fujitsu-laptop: Battery charge control support
- hp-wmi: Support for new thermal profiles
- ideapad-laptop: Support for refresh rate key
- intel/pmc: Put AI accelerator (GNA) into D3 if it has no
driver to allow entry into low-power modes, and
temporarily removed Lunar Lake SSRAM support due
to breaking FW changes causing probe fail
(further breaking FW changes are still pending)
- pmc/punit_atom: Report devices that prevent reacing low power
levels
- surface: Fan speed function support
- thinkpad_acpi: Support for more sperial keys and complete the
list of models with non-standard fan registers
- touchscreen_dmi: New HW support
- wmi: Continued modernization efforts
- Removal of obsoleted ledtrig-audio call and the related dependency
- Debug & metrics interface improvements
- Miscellaneous cleanups / fixes / improvements
The following is an automated shortlog grouped by driver:
acer-wmi:
- Add predator_v4 module parameter
- Add support for Acer PH16-71
amd/hsmp:
- Add support for ACPI based probing
- Cache pci_dev in struct hsmp_socket
- Change devm_kzalloc() to devm_kcalloc()
- Check num_sockets against MAX_AMD_SOCKETS
- Create static func to handle platdev
- Define a struct to hold mailbox regs
- Move dev from platdev to hsmp_socket
- Move hsmp_test to probe
- Non-ACPI support for AMD F1A_M00~0Fh
- Remove extra parenthesis and add a space
- Restructure sysfs group creation
amd/pmf:
- Add missing __iomem attribute to policy_base
- Add support to get APTS index numbers for static slider
- Add support to get sbios requests in PMF driver
- Add support to get sps default APTS index values
- Add support to notify sbios heart beat event
- Differentiate PMF ACPI versions
- Disable debugfs support for querying power thermals
- Do not use readl() for policy buffer access
- Fix possible out-of-bound memory accesses
- Fix return value of amd_pmf_start_policy_engine()
- Update sps power thermals according to the platform-profiles
- Use struct for cookie header
asus-wmi:
- Consider device is absent when the read is ~0
- Revert: Support WMI event queue
clk: x86:
- Move clk-pmc-atom register defines to include/linux/platform_data/x86/pmc_atom.h
dell-privacy:
- Remove usage of wmi_has_guid()
Documentation/x86/amd/hsmp:
- Updating urls
drivers/mellanox:
- Convert snprintf to sysfs_emit
fujitsu-laptop:
- Add battery charge control support
hp-wmi:
- Add thermal profile support for 8BAD boards
- Tidy up module source code
ideapad-laptop:
- map Fn + R key to KEY_REFRESH_RATE_TOGGLE
- support Fn+R dual-function key
Input:
- allocate keycode for Display refresh rate toggle
intel/ifs:
- Add an entry rendezvous for SAF
- Add current batch number to trace output
- Remove unnecessary initialization of 'ret'
- Replace the exit rendezvous with an entry rendezvous for ARRAY_BIST
- Trace on all HT threads when executing a test
intel/pmc/arl:
- Put GNA device in D3
intel/pmc:
- Improve PKGC residency counters debug
intel/pmc/lnl:
- Remove SSRAM support
intel_scu_ipcutil:
- Make scu static
intel_scu_pcidrv:
- Remove unused intel-mid.h
intel_scu_wdt:
- Remove unused intel-mid.h
intel/tpmi:
- Change vsec offset to u64
intel/vsec:
- Remove nuisance message
ISST:
- Allow reading core-power state on HWP disabled systems
mlxbf-pmc:
- Cleanup signed/unsigned mix-up
- fix signedness bugs
- Ignore unsupported performance blocks
mlxbf-pmc: mlxbf_pmc_event_list():
- make size ptr optional
mlxbf-pmc:
- Replace uintN_t with kernel-style types
mlxreg-hotplug:
- Remove redundant NULL-check
pmc_atom:
- Annotate d3_sts register bit defines
- Check state of PMC clocks on s2idle
- Check state of PMC managed devices on s2idle
silicom-platform:
- clean up a check
surface: aggregator_registry:
- add entry for fan speed
thinkpad_acpi:
- Add more ThinkPads with non-standard reg address for fan
- Fix to correct wrong temp reporting on some ThinkPads
- remove redundant assignment to variable i
- Simplify thermal mode checking
- Support for mode FN key
touchscreen_dmi:
- Add an extra entry for a variant of the Chuwi Vi8 tablet
wmi:
- Always evaluate _WED when receiving an event
- Check if event data is not NULL
- Check if WMxx control method exists
- Do not instantiate older WMI drivers multiple times
- Ignore duplicated GUIDs in legacy matches
- Make input buffer mandatory when evaluating methods
- Prevent incompatible event driver from probing
- Remove obsolete duplicate GUID allowlist
- Remove unnecessary out-of-memory message
- Replace pr_err() with dev_err()
- Stop using ACPI device class
- Update documentation regarding _WED
- Use ACPI device name in netlink event
- Use FW_BUG when warning about missing control methods
x86/atom:
- Check state of Punit managed devices on s2idle
x86: ibm_rtl:
- make rtl_subsys const
x86: wmi:
- make wmi_bus_type const
platform/x86:
- make fw_attr_class constant
- remove obsolete calls to ledtrig_audio_get
Merges:
- Merge tag 'platform-drivers-x86-v6.8-2' into pdx/for-next
- Merge tag 'platform-drivers-x86-v6.8-4' into pdx86/for-next
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQSCSUwRdwTNL2MhaBlZrE9hU+XOMQUCZfLZKgAKCRBZrE9hU+XO
MWqnAQCZW0KiSzXbJkTN4GWlMOqnlaJsiflnPeVNxH59bDUTeQEA/OdSzyiDUqKr
zJcGnOyILuQ3wCvQ5SuqRCwjFHXOQg0=
=8y6r
-----END PGP SIGNATURE-----
Merge tag 'platform-drivers-x86-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
Pull x86 platform driver updates from Ilpo Järvinen:
- New acer-wmi HW support
- Support for new revision of amd/pmf heartbeat notify
- Correctly handle asus-wmi HW without LEDs
- fujitsu-laptop battery charge control support
- Support for new hp-wmi thermal profiles
- Support ideapad-laptop refresh rate key
- Put intel/pmc AI accelerator (GNA) into D3 if it has no driver to
allow entry into low-power modes, and temporarily removed Lunar Lake
SSRAM support due to breaking FW changes causing probe fail (further
breaking FW changes are still pending)
- Report pmc/punit_atom devices that prevent reacing low power levels
- Surface Fan speed function support
- Support for more sperial keys and complete the list of models with
non-standard fan registers in thinkpad_acpi
- New DMI touchscreen HW support
- Continued modernization efforts of wmi
- Removal of obsoleted ledtrig-audio call and the related dependency
- Debug & metrics interface improvements
- Miscellaneous cleanups / fixes / improvements
* tag 'platform-drivers-x86-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (87 commits)
platform/x86/intel/pmc: Improve PKGC residency counters debug
platform/x86: asus-wmi: Consider device is absent when the read is ~0
Documentation/x86/amd/hsmp: Updating urls
platform/mellanox: mlxreg-hotplug: Remove redundant NULL-check
platform/x86/amd/pmf: Update sps power thermals according to the platform-profiles
platform/x86/amd/pmf: Add support to get sps default APTS index values
platform/x86/amd/pmf: Add support to get APTS index numbers for static slider
platform/x86/amd/pmf: Add support to notify sbios heart beat event
platform/x86/amd/pmf: Add support to get sbios requests in PMF driver
platform/x86/amd/pmf: Disable debugfs support for querying power thermals
platform/x86/amd/pmf: Differentiate PMF ACPI versions
x86/platform/atom: Check state of Punit managed devices on s2idle
platform/x86: pmc_atom: Check state of PMC clocks on s2idle
platform/x86: pmc_atom: Check state of PMC managed devices on s2idle
platform/x86: pmc_atom: Annotate d3_sts register bit defines
clk: x86: Move clk-pmc-atom register defines to include/linux/platform_data/x86/pmc_atom.h
platform/x86: make fw_attr_class constant
platform/x86/intel/tpmi: Change vsec offset to u64
platform/x86: intel_scu_pcidrv: Remove unused intel-mid.h
platform/x86: intel_scu_wdt: Remove unused intel-mid.h
...
- Increase dev_id len for clkdev lookups
* clk-samsung: (25 commits)
clk: samsung: Add CPU clock support for Exynos850
clk: samsung: Pass mask to wait_until_mux_stable()
clk: samsung: Keep register offsets in chip specific structure
clk: samsung: Keep CPU clock chip specific data in a dedicated struct
clk: samsung: Pass register layout type explicitly to CLK_CPU()
clk: samsung: Pass actual CPU clock registers base to CPU_CLK()
clk: samsung: Group CPU clock functions by chip
clk: samsung: Use single CPU clock notifier callback for all chips
clk: samsung: Reduce params count in exynos_register_cpu_clock()
clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c
clk: samsung: Improve clk-cpu.c style
dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
clk: samsung: gs101: add support for cmu_peric1
clk: samsung: gs101: drop extra empty line
dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
clk: samsung: exynos850: Propagate SPI IPCLK rate change
clk: samsung: gs101: gpio_peric0_pclk needs to be kept on
clk: samsung: exynos850: Add PDMA clocks
dt-bindings: clock: tesla,fsd: Fix spelling mistake
clk: samsung: gs101: add support for cmu_peric0
...
* clk-imx:
clk: imx: imx8mp: Fix SAI_MCLK_SEL definition
clk: imx: scu: Use common error handling code in imx_clk_scu_alloc_dev()
clk: imx: composite-8m: Delete two unnecessary initialisations in __imx8m_clk_hw_composite()
clk: imx: composite-8m: Less function calls in __imx8m_clk_hw_composite() after error detection
* clk-rockchip:
clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent
clk: rockchip: rk3588: use linked clock ID for GATE_LINK
clk: rockchip: rk3588: fix indent
clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
dt-bindings: clock: rk3588: drop CLK_NR_CLKS
clk: rockchip: rk3588: fix CLK_NR_CLKS usage
clk: rockchip: rk3568: Add PLL rate for 128MHz
* clk-clkdev:
clkdev: Update clkdev id usage to allow for longer names
* clk-rate-exclusive:
clk: Add a devm variant of clk_rate_exclusive_get()
Move the register defines for the Atom (Bay Trail, Cherry Trail) PMC
clocks to include/linux/platform_data/x86/pmc_atom.h.
This is a preparation patch to extend the S0i3 readiness checks
in drivers/platform/x86/pmc_atom.c with checking that the PMC
clocks are off on suspend entry.
Note these are added to include/linux/platform_data/x86/pmc_atom.h rather
then to include/linux/platform_data/x86/clk-pmc-atom.h because the former
already has all the other Atom PMC register defines.
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20240305105915.76242-2-hdegoede@redhat.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
The kmalloc() in zynq_clk_setup() will return null if the
physical memory has run out. As a result, if we use snprintf()
to write data to the null address, the null pointer dereference
bug will happen.
This patch uses a stack variable to replace the kmalloc().
Fixes: 0ee52b157b ("clk: zynq: Add clock controller driver")
Suggested-by: Michal Simek <michal.simek@amd.com>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
Link: https://lore.kernel.org/r/20240301084437.16084-1-duoming@zju.edu.cn
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use BIT() where makes sense. This alings usage of bit operations
in the same pieces of code. Moreover, strictly speaking by the
letter of the C standard, left shift of 1 by 31 bits is UB (undefined
behaviour), switching to BIT() addresses that as well.
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240303120732.240355-1-andy.shevchenko@gmail.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There is no need to calculate masks under the lock taken.
Move them out of it.
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240303121410.240761-1-andy.shevchenko@gmail.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It is possible for clk_core_get to dereference a NULL in the following
sequence:
clk_core_get()
of_clk_get_hw_from_clkspec()
__of_clk_get_hw_from_provider()
__clk_get_hw()
__clk_get_hw() can return NULL which is dereferenced by clk_core_get() at
hw->core.
Prior to commit dde4eff47c ("clk: Look for parents with clkdev based
clk_lookups") the check IS_ERR_OR_NULL() was performed which would have
caught the NULL.
Reading the description of this function it talks about returning NULL but
that cannot be so at the moment.
Update the function to check for hw before dereferencing it and return NULL
if hw is NULL.
Fixes: dde4eff47c ("clk: Look for parents with clkdev based clk_lookups")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240302-linux-next-24-03-01-simple-clock-fixes-v1-1-25f348a5982b@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/90054b8b2e118bc04ec37e044d0ac518bb177cf4.1709721042.git.u.kleine-koenig@pengutronix.de
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/312ec7052c4e327c0b365e167a8e86b406cb7dfa.1709721042.git.u.kleine-koenig@pengutronix.de
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/ba373ce7341518216a4940e76ce61d759b912b3d.1709721042.git.u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Updates for TI clksel clocks to use the standard reg property instead of
the non-standard ti,bit-shift legacy property.
There are still lots of TI composite clock related devicetree warnings for
missing bindings, and overlapping reg properties. We have grouped some of
the TI composite clocks under the clksel clock node, but did not consider
the reg property issue. Let's update the existing users before we continue
grouping more of the composite clocks.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAmXcc2gRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMa+RAArqO2Q+JzQHfmZFZrZoRMGTBJ4kDwVkcj
JGauvrQQrcTS9Cg8Yk4Rjs5GBhdIMKJXNCyOnP7cxF37SqwvU6FZfwuZbRNdXA4u
V+0L/LHjMWdLyPww1DiigWydxXgaVrWJ33ebN8r12jRnmDB3F1s7QtKqR4Dyg0zn
AdErSCbxU3DrkoRzSzo8i4wcGUmud61LNdtFQb7i7IRLP8VHQbAThjGVzZIAOTa5
nqf89fAeeNLDBscBxDtqHFxwsUtAwg9Lg28N977ivzzfr2gDFzTx/arkVpLqT7Zz
2nnYXVk4Yh3r9gj1MvoJJjOrbGOtF2CJRuXjKkpaNJlNO+11rdGNMr+y9o743MNY
LxkXuCqfIvpcYAz8KlRpP94nL1NYML9e+P/KCtuauyOm4Gl9SDgJoxj43uHdyRJN
CWabT5w5UZK9MDQ+NcmlFRHHU5OTe+MFQUoV5+qJz0cVEWdMCttrMOm3UrcdQQym
0wugZJHng77aZNrw4yK1f3P6dXSO+Sf6SmbX2/8pwWXrdfHa4AjXfHqC/6VURyU9
tYU31fMQbIrI7P+brxc3X2pmwI4r716A83lw3CDpzOCxk7+KBLdfjIRIK0d2k2GZ
DRFRNbR7nMQIPGjxXSy7TyLOZ/OCEqzYzy4JjVkG4Yj8Oze5VldpEeb1znPkm04K
gebOLtYQVI4=
=HPYX
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXl+K4ACgkQYKtH/8kJ
UieKUA//W7ZaEVG04hH53o6NIiPiNHsyyT9XF+VnPRybbBUB6IevbOLDnLsAA8f+
h3cvOaLoykmZ78Lf0DOwB1JVYdEal6J/IVLyLQs7sVdjaJpGqy8M65D/7Sz9ZMHQ
vsDKTx2+q5BJS1zXsZqsDL2M6nthXb3kB6Sv6c2F6166oD2IuR4fjZ7Ed8I4irBB
h2/Ullqyvl3Wj+i7CC3gIlXE/t3ZUFJGVPtTmJWf+AhK9YJT7D2AfUWUr7txz/R+
wAVt4GPxs+uJFPsEzIDtUS6TL12ZxiQe6/aAEvO89Pg9PgtYfZoxTqomzGcvO0fV
N4e8khuzqYYJODr4Hax9+Dp2B0P5rEo2hPj8Pldf8d60Ob6immhXsEvoPjpBOnZS
ZxKrudZmF8yzBwEKtzlUWuA9km/HwmUcBbeWehzKKGAobsQRmBoFzb/EzOHldTTn
rCFIq4g4g7MAl17eCABxITtJihd5vhoEJ3HBt8iwGlFjz/llIgUoVhbOr/K0PfUG
hZkHzHiZR6X/il9dmNAZJLljG3diwpX+hN++znH9aDlYn8JikdjoxYfO9pSlQMCK
0cLJE7z1XfOUORjWDjkBhlAVit7xy3Hb5gg3PxrbDA53jXzS7Qb1rYGOzGpzN80Y
GMlJ2gJO8Wa43HntA/0LUL9BX/s2DFgBAJQttoGsgxJm7kPcemg=
=KkTU
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/late
Update TI clksel clocks to use reg
Updates for TI clksel clocks to use the standard reg property instead of
the non-standard ti,bit-shift legacy property.
There are still lots of TI composite clock related devicetree warnings for
missing bindings, and overlapping reg properties. We have grouped some of
the TI composite clocks under the clksel clock node, but did not consider
the reg property issue. Let's update the existing users before we continue
grouping more of the composite clocks.
* tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
clk: ti: Improve clksel clock bit parsing for reg property
clk: ti: Handle possible address in the node name
Link: https://lore.kernel.org/r/pull-1709102378-94138@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
from Theobroma-Systems and the rk3588-based Toybrick TB-RK3588X.
Some fixes to conform to dt-bindings for i2s (rk3588, rk356x) and
rk356x video-decoder (missing interrupt-names).
Correcting the vendor in the compatible for OrangePi RK3399 and BananaPi
R2 Pro (discussed with DT-maintainers beforehand of course).
The VO1-GRF syscon needs its clock to work, and that clock also needed to
be actually exported forst, so we're sharing a branch with the Rockchip
clock-tree (that already got merged into the main clock-tree for 6.9) for
this small shared code.
And as another step on the long road to graphics output on rk3588, 6.9 will
get the hdmi-phy via the phy-tree, so here the dts node is added.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmXjFSEQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgZ12CACL8EGrdL32f+Yg+4pgKiC79C0WFh05F56I
KAgK4nRs3IjOR8zRUx5Wez3uKd7vbH/3GhqSurJQ894FNqpOKYJ48cnokaG/hUV3
dimEr5dPcSZGVdRcaQRH+B7Pe5hFmw98dZxIDfWOZzZ4XwShcfDYFx6xlGmcba+e
KyMwjrVHyjh3M384yDx14oJw8bqn2b+oFFaZxCoz93zX9g1FUFbF6IuOsJ0KXXDR
SRHP+s2jGxUyBltsXyQc4sa4e9i8hDbAZuBwgozLReSgTy+GJqxj87pcsc/4uCAE
w8MW9RW/xwuFrU+BLs0UNOtdSn8BdHjEyEFc0SEtFAW9HVtoCozP
=awlr
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXleR4ACgkQYKtH/8kJ
UifN5w//dcJ1v6HXK31S0Egneku8WUV4ytQuLXvYeg41zIIIEv36sBeqDQxd5taa
z2/Vy4plHCECvXWjZFEGfK44Hn/0KevrG3rHOzhNUhZV10M1KBHP5uxUYVtrmcYr
crZsLGy90ZLnZqdKjep1bSxMv1o5QdU9LUjBZmclZEeMky4CH3ZB+sMY9shN6YZM
wWewSwsLSoa2pAxP9g3izJjFKcwALDjNapmuXe/KFWOIOfJrm3kvASu993sfILYA
/Wx3IRMerM9tsxAz1/KfKyKYnfT4HbF2RlNTf8OaYdypXU4eLpMboL31k8jCBoTT
TNVkY5M722r9rbg5hTM4LTRRuEC4rfuDJEyEdHWEgqPIdXK4pwMncQDBVwimunIN
sEG5TajVI34e9ZInptJQ/ZBCKCllC5gpAPcLw9GrRw7guuCfIbpQj0F+2lDFR9Ob
FtYW7Ua6Nbw7jPbOCW6qrF/ujnbG3X317aYugpuqiakPW/G+kv11CtRsWZV+OBTv
SXgRqtYTKprFJxOY5nMnlkG7+ps/B2ctgOGuq1mjcoodsZDF8WW6q00U9Jf9IbVF
f78ed9DOJ+M70NKJ1QLBIXDLhcZ/Mlv2m9akG8YqmVvBs9efRPQc0mnFQUvWiMDq
7xFXZRl2i2xe5IX0JIE7Ujvox/APZARrHhQldHfkC9S5jSlCi0E=
=SbMB
-----END PGP SIGNATURE-----
Merge tag 'v6.9-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Initial support for the rk3568 Qnap TS433 NAS, the rk3588-based Tiger SoM
from Theobroma-Systems and the rk3588-based Toybrick TB-RK3588X.
Some fixes to conform to dt-bindings for i2s (rk3588, rk356x) and
rk356x video-decoder (missing interrupt-names).
Correcting the vendor in the compatible for OrangePi RK3399 and BananaPi
R2 Pro (discussed with DT-maintainers beforehand of course).
The VO1-GRF syscon needs its clock to work, and that clock also needed to
be actually exported forst, so we're sharing a branch with the Rockchip
clock-tree (that already got merged into the main clock-tree for 6.9) for
this small shared code.
And as another step on the long road to graphics output on rk3588, 6.9 will
get the hdmi-phy via the phy-tree, so here the dts node is added.
* tag 'v6.9-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433
arm64: dts: rockchip: Add basic support for QNAP TS-433
dt-bindings: arm: rockchip: Add QNAP TS-433
arm64: dts: rockchip: add Haikou baseboard with RK3588-Q7 SoM
arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM
dt-bindings: arm: rockchip: Add Theobroma-Systems RK3588 Q7 with baseboard
arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s
arm64: dts: rockchip: fix reset-names for rk356x i2s2 controller
arm64: dts: rockchip: add missing interrupt-names for rk356x vdpu
arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588
dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X
arm64: dts: rockchip: Add devicetree support for TB-RK3588X board
arm64: dts: rockchip: adjust vendor on orangepi rk3399 board
arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board
dt-bindings: arm: rockchip: Correct vendor for Banana Pi R2 Pro
dt-bindings: arm: rockchip: Correct vendor for Orange Pi RK3399 board
arm64: dts: rockchip: Add HDMI0 PHY to rk3588
dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
dt-bindings: clock: rk3588: drop CLK_NR_CLKS
clk: rockchip: rk3588: fix CLK_NR_CLKS usage
Link: https://lore.kernel.org/r/3695004.ElGaqSPkdT@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The following table shows the values of the 'halt_reg' and the
'enable_reg' fields from the pcie clocks defined in the current
driver:
clock halt_reg enable_reg
gcc_pcie0_ahb_clk 0x75010 0x75010
gcc_pcie0_aux_clk 0x75014 0x75014
gcc_pcie0_axi_m_clk 0x75008 0x75008
gcc_pcie0_axi_s_bridge_clk 0x75048 0x75048
gcc_pcie0_axi_s_clk 0x7500c 0x7500c
gcc_pcie0_pipe_clk 0x75018 0x75018
gcc_pcie1_ahb_clk 0x76010 0x76010
gcc_pcie1_aux_clk 0x76014 0x76014
gcc_pcie1_axi_m_clk 0x76008 0x76008
gcc_pcie1_axi_s_bridge_clk 0x76048 0x76048
gcc_pcie1_axi_s_clk 0x7600c 0x7600c
gcc_pcie1_pipe_clk 8* 0x76018
Based on the table, it is quite likely that the pcie0 and the pci1
clocks are using the same register layout, however it seems that
the value of the 'halt_reg' field in the 'gcc_pcie1_pipe_clk' clock
is wrong.
In the downstream driver [1], the same '0x76018' value is used for
both the 'halt_reg' and for the 'enable_reg' fields of the
'gcc_pcie1_pipe_clk' clock.
Update the current driver to use the same value used downstream as
probably that is the correct value.
1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L2316
Fixes: e3fdbef1ba ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20240225-gcc-ipq5018-register-fixes-v1-2-3c191404d9f0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The value of the 'enable_reg' field in the 'gcc_gmac0_sys_clk'
clock definition seems wrong as it is greater than the
'max_register' value defined in the regmap configuration.
Additionally, all other gmac specific branch clock definitions
within the driver uses the same value both for the 'enable_reg'
and for the 'halt_reg' fields.
Due to the lack of documentation the correct value is not known.
Looking into the downstream driver does not help either, as that
uses the same (presumably wrong) value [1].
Nevertheless, change the 'enable_reg' field of 'gcc_gmac0_sys_clk'
to use the value from the 'halt_reg' field so it follows the pattern
used in other gmac clock definitions. The change is based on the
assumption that the register layout of this clock is the same
as the other gmac clocks.
1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L1889
Fixes: e3fdbef1ba ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20240225-gcc-ipq5018-register-fixes-v1-1-3c191404d9f0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The desired DT pattern for clock indexing is the following:
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&bi_tcxo_div2>,
<&bi_tcxo_ao_div2>,
<&sleep_clk>;
In order to facilitate that indexing structure we need to have DT_IFACE
enum defined.
Fixes: 76126a5129 ("clk: qcom: Add camcc clock driver for x1e80100")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240302-linux-next-24-03-01-simple-clock-fixes-v1-2-25f348a5982b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The frequency table arrays are supposed to be terminated with an
empty element. Add such entry to the end of the arrays where it
is missing in order to avoid possible out-of-bound access when
the table is traversed by functions like qcom_find_freq() or
qcom_find_freq_floor().
Only compile tested.
Fixes: d8b212014e ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-7-074334f0905c@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The frequency table arrays are supposed to be terminated with an
empty element. Add such entry to the end of the arrays where it
is missing in order to avoid possible out-of-bound access when
the table is traversed by functions like qcom_find_freq() or
qcom_find_freq_floor().
Only compile tested.
Fixes: 2b46cd23a5 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-6-074334f0905c@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The frequency table arrays are supposed to be terminated with an
empty element. Add such entry to the end of the arrays where it
is missing in order to avoid possible out-of-bound access when
the table is traversed by functions like qcom_find_freq() or
qcom_find_freq_floor().
Only compile tested.
Fixes: ff93872a9c ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-5-074334f0905c@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The frequency table arrays are supposed to be terminated with an
empty element. Add such entry to the end of the arrays where it
is missing in order to avoid possible out-of-bound access when
the table is traversed by functions like qcom_find_freq() or
qcom_find_freq_floor().
Only compile tested.
Fixes: d75b82cff4 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-4-074334f0905c@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
