* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (52 commits)
drm/kms: Init the CRTC info fields for modes forced from the command line.
drm/radeon/r600: CS parser updates
drm/radeon/kms: add debugfs for power management for AtomBIOS devices
drm/radeon/kms: initial mode validation support
drm/radeon/kms/atom/dce3: call transmitter init on mode set
drm/radeon/kms: store detailed connector info
drm/radeon/kms/atom/dce3: fix up usPixelClock calculation for Transmitter tables
drm/radeon/kms/r600: fix rs880 support v2
drm/radeon/kms/r700: fix some typos in chip init
drm/radeon/kms: remove some misleading debugging output
drm/radeon/kms: stop putting VRAM at 0 in MC space on r600s.
drm/radeon/kms: disable D1VGA and D2VGA if enabled
drm/radeon/kms: Don't RMW CP_RB_CNTL
drm/radeon/kms: fix coherency issues on AGP cards.
drm/radeon/kms: fix rc410 suspend/resume.
drm/radeon/kms: add quirk for hp dc5750
drm/radeon/kms/atom: fix potential oops in spread spectrum code
drm/kms: typo fix
drm/radeon/kms/atom: Make card_info per device
drm/radeon/kms/atom: Fix DVO support
...
Generally this is done at post, but might not always be done
with softboot or for connectors on docking stations.
Could probably be done once when the driver loads/resumes
rather than on each mode set.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This will be useful for mode validation and certain
atom tables.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Lots of cases were wrong or missing.
v2: rebased against drm-next
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Ironlake suspend/resume support
drm/i915: kill warning in intel_find_pll_g4x_dp
drm/i915: update watermarks before enabling PLLs
drm/i915: add FIFO watermark support for G4x
drm/i915: quiet DP i2c init
drm/i915: fix panel fitting filter coefficient select for Ironlake
drm/i915: fix to setup display reference clock control on Ironlake
drm/i915: Install a fence register for fbc on g4x
drm/i915: save/restore BLC histogram control reg across suspend/resume
drm/i915: Fix FDI M/N setting according with correct color depth
drm/i915: disable powersave feature for Ironlake currently
drm/i915: Fix render reclock availability detection.
drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
drm/i915: disable FBC for Pineview, fixing a boot hang.
Noticed by Andre on IRC.
Also fix up some minor whitespace issues.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The Lenovo W500 laptop hangs inside an SMI on brightness changes,
I thought it just needed the VGA disable but it turned out to require
slightly more work, setting the MC locations up just like the IGP
chip requirements seems to make it all happy again and I can boot
and play with brightness.
We should probably just do this for all chips and give up the VRAM
at 0x0 idea, it never seems to buy us anything but pain.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Once kms is enabled we don't need these, and it causes a problem
with the Lenovo W500 ACPI brightness implementation, it hangs
in a loop inside an SMI.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Immediate readback seems faulty on some chips. I
suspect it takes a while to get through the fifo
to the actual register backbone. There's no need
to read it back, so, just write the driver's copy
of the register's value directly.
Should fix bug 24535 and possibly 24218
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
When we are evicting from VRAM->RAM we allocate the ttm object,
but we don't set the caching policy on it before blitting into it.
This means on AGP we end up blitting into cached pages, and
the CPU later flushes out on top of them. This was mostly seen as
font corruption.
The other question is why we don't evict VRAM->GTT in a lot of cases,
this would save us some cache transitions since a lot of objects
that are evicted from VRAM will probably end up being pulled back in
a few operations later, and evicting them to system memory involves
2 unnecessary cache transitions.
Signed-off-by: Dave Airlie <airlied@redhat.com>
In commit c1c7af6089 ("drm/i915: force
mode set at lid open time") the intel graphics driver was taught to
restore the LVDS mode on lid open.
That caused problems with interaction with the suspend/resume code,
which commonly runs at the same time (suspend is often caused by the lid
close event, while lid open is commonly a resume event), which was
worked around with in commit 06891e27a9
("drm/i915: fix suspend/resume breakage in lid notifier").
However, in the meantime the lid event code had also grown a user event
notifier (commit 06324194ee: "drm/i915:
generate a KMS uevent at lid open/close time"), and now _that_ causes
problems with suspend/resume and some versions of Xorg reacting to those
uevents by setting the mode.
So this effectively reverts that commit 06324194ee, and makes the lid
open protection logic against suspend/resume more explicit. This fixes
at least one laptop. See
http://bugzilla.kernel.org/show_bug.cgi?id=14484
for more details.
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Riccardo Magliocchetti <riccardo.magliocchetti@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This fixes suspend/resume on my rc410 motherboard, it restores
the memory controller setup before posting the GPU, since it seems
to need the MC_FB_LOCATION setup correctly.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Make sure we have an LVDS encoder before casting enc_priv.
[airlied: also fix two missing cpu_to_le16 casts we noticed on irc]
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Make the struct card_info, which is a per struct radeon_device dataset, a
struct member of the radeon device instead of a static per kernel module
value. This should avoid potential problems with two radeon cards installed in
one system.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
DVO in 12 bit mode (which seems to be the most common
config) requires 2x ppll.
Fixes fdo bug 21857.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Limiting the pll output range is a good thing generally as
it limits the number of possible pll combinations for a given
frequency presumably to the ones that work best on each card.
That's why the limits are in the bios tables. However, certain
duallink DVI monitors seem to like pll combinations that would
be limited by this at least on pre-DCE 3.0 r6xx hardware. This
might need to be adjusted per family or per clock range in the
future.
See fdo bug 24727.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This sets the fbcon to use TRUECOLOR by default, it then
only modifies the pseudo palette for fbcon, and only touches
the real palette when in 8-bit pseudo color mode.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example:
>hsync/vsync width is zero
>sync is beyond the blank.
So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Since we register all radeon devices, and the arbiter only cares about
VGA class ones, we will fail to startup on display controller class devices.
We don't gain anything by using the return value here.
this helps kms on sparc64 get started.
Reported-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Spread spectrum is a periodic disturbance added
to the feedback divider to change the pixel clock
periodically to reduce interference.
Only enabled on LVDS.
v2: add support for r4xx and fix DCE 3
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The *_HIGH regs are reversed. The secondary ones are in the
primary block and vice versa.
We currently only use a 32 bit internal address, so these are
0 for now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This patch only changes this is the swap path, where it doesn't loop.
Signed-off-by: Robert Noland <rnoland@2hip.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
- Reduce the chance of error and avoid a bit of overhead.
- Use switch to assign color and format
Signed-off-by: Robert Noland <rnoland@2hip.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Where supported use ulMinPixelClockPLL_Output rather than
usMinPixelClockPLL_Output for pll_out_min. This seems to
improve pll selection on some boards.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The problem boils down to the order when the bit11
of the texture size is or'ed to the original width.
In the end each mipmap level has the same width or
height because of that 11 bit is ored to the scaled
down lod with and thus blows up the size again to the
full size or more due to the power of two rounding
afterwards.
The attached patch changes this order so that the
texture sizes are computed correct. Also the on error
the yet missing inputs to the size computation are
printed which helped me to find out where it really breaks.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This sets the fbcon to use TRUECOLOR by default, it then
only modifies the pseudo palette for fbcon, and only touches
the real palette when in 8-bit pseudo color mode.
Signed-off-by: Dave Airlie <airlied@redhat.com>
This adds registers save/restore for Ironlake to make suspend work.
Signed-off-by: Guo, Chaohong <chaohong.guo@intel.com>
[zhenyuw: some code re-orgnization, and add more save/restore for
FDI link and transcoder registers, also fix palette register for Ironlake]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
When coming back from DPMS or turning on a display, make sure we have
the watermarks set up before turning on the display plane, otherwise we
may get underruns.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Dirk Hohndel <hohndel@infradead.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Turns out G4x needs to have sensible watermarks set, especially for
self-refresh enabled modes. Add support for it.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Dirk Hohndel <hohndel@infradead.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Must set filter selection as hardcoded coefficients for medium 3x3
filtering, which matches vbios setting for Ironlake.
This fixes display corrupt issue on HP arrandale with new vbios.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
For new stepping of PCH, the display reference clock
is fully under driver's control. This one trys to setup
all needed reference clock for different outputs. Older
stepping of PCH chipset should be ignoring this.
This fixes output failure issue on newer PCH which requires
driver to take control of reference clock enabling.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Original radeon didn't have a connector table in the
bios. Check for the CRT table and if we have one,
add a VGA connector.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
Need to check the return type for the quirk function
to decide whether we add the connectors and encoders.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example:
>hsync/vsync width is zero
>sync is beyond the blank.
So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
D1MODE_INTERLEAVE_EN was getting set in some cases
in the encoder quirks function due to the changes in
5a9bcacc0a
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
