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ath9k_hw: clean up EEPROM endian handling on AR9003
Remove the double swapping of the descriptor data structure, instead keep it little-endian (native format of the eeprom data), and byteswap on access. This allows sparse to verify endian access to the eeprom struct. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Felix Fietkau
John W. Linville
parent
9bff0bc401
commit
ffdc4cbe5b
@ -38,6 +38,9 @@
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#define AR_SWITCH_TABLE_ALL (0xfff)
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#define AR_SWITCH_TABLE_ALL_S (0)
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#define LE16(x) __constant_cpu_to_le16(x)
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#define LE32(x) __constant_cpu_to_le32(x)
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static const struct ar9300_eeprom ar9300_default = {
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.eepromVersion = 2,
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.templateVersion = 2,
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@ -45,7 +48,7 @@ static const struct ar9300_eeprom ar9300_default = {
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.custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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.baseEepHeader = {
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.regDmn = {0, 0x1f},
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.regDmn = { LE16(0), LE16(0x1f) },
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.txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
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.opCapFlags = {
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.opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
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@ -76,15 +79,15 @@ static const struct ar9300_eeprom ar9300_default = {
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.modalHeader2G = {
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/* ar9300_modal_eep_header 2g */
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/* 4 idle,t1,t2,b(4 bits per setting) */
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.antCtrlCommon = 0x110,
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.antCtrlCommon = LE32(0x110),
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/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
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.antCtrlCommon2 = 0x22222,
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.antCtrlCommon2 = LE32(0x22222),
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/*
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* antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
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* rx1, rx12, b (2 bits each)
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*/
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.antCtrlChain = {0x150, 0x150, 0x150},
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.antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
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/*
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* xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
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@ -287,12 +290,12 @@ static const struct ar9300_eeprom ar9300_default = {
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},
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.modalHeader5G = {
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/* 4 idle,t1,t2,b (4 bits per setting) */
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.antCtrlCommon = 0x110,
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.antCtrlCommon = LE32(0x110),
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/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
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.antCtrlCommon2 = 0x22222,
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.antCtrlCommon2 = LE32(0x22222),
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/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
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.antCtrlChain = {
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0x000, 0x000, 0x000,
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LE16(0x000), LE16(0x000), LE16(0x000),
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},
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/* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
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.xatten1DB = {0, 0, 0},
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@ -620,9 +623,9 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
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case EEP_MAC_MSW:
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return eep->macAddr[4] << 8 | eep->macAddr[5];
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case EEP_REG_0:
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return pBase->regDmn[0];
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return le16_to_cpu(pBase->regDmn[0]);
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case EEP_REG_1:
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return pBase->regDmn[1];
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return le16_to_cpu(pBase->regDmn[1]);
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case EEP_OP_CAP:
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return pBase->deviceCap;
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case EEP_OP_MODE:
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@ -640,94 +643,81 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
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/* Bit 4 is internal regulator flag */
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return (pBase->featureEnable & 0x10) >> 4;
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case EEP_SWREG:
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return pBase->swreg;
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return le32_to_cpu(pBase->swreg);
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default:
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return 0;
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}
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}
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#ifdef __BIG_ENDIAN
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static void ar9300_swap_eeprom(struct ar9300_eeprom *eep)
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static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
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u8 *buffer)
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{
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u32 dword;
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u16 word;
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int i;
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u16 val;
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word = swab16(eep->baseEepHeader.regDmn[0]);
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eep->baseEepHeader.regDmn[0] = word;
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if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
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return false;
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word = swab16(eep->baseEepHeader.regDmn[1]);
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eep->baseEepHeader.regDmn[1] = word;
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dword = swab32(eep->baseEepHeader.swreg);
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eep->baseEepHeader.swreg = dword;
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dword = swab32(eep->modalHeader2G.antCtrlCommon);
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eep->modalHeader2G.antCtrlCommon = dword;
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dword = swab32(eep->modalHeader2G.antCtrlCommon2);
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eep->modalHeader2G.antCtrlCommon2 = dword;
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dword = swab32(eep->modalHeader5G.antCtrlCommon);
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eep->modalHeader5G.antCtrlCommon = dword;
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dword = swab32(eep->modalHeader5G.antCtrlCommon2);
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eep->modalHeader5G.antCtrlCommon2 = dword;
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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word = swab16(eep->modalHeader2G.antCtrlChain[i]);
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eep->modalHeader2G.antCtrlChain[i] = word;
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word = swab16(eep->modalHeader5G.antCtrlChain[i]);
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eep->modalHeader5G.antCtrlChain[i] = word;
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*buffer = (val >> (8 * (address % 2))) & 0xff;
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return true;
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}
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}
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#endif
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static bool ar9300_hw_read_eeprom(struct ath_hw *ah,
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long address, u8 *buffer, int many)
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static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
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u8 *buffer)
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{
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u16 val;
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if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
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return false;
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buffer[0] = val >> 8;
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buffer[1] = val & 0xff;
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return true;
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}
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static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
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int count)
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{
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int i;
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u8 value[2];
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unsigned long eepAddr;
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unsigned long byteAddr;
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u16 *svalue;
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struct ath_common *common = ath9k_hw_common(ah);
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int i;
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if ((address < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) {
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if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
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ath_print(common, ATH_DBG_EEPROM,
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"eeprom address not in range\n");
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return false;
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}
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for (i = 0; i < many; i++) {
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eepAddr = (u16) (address + i) / 2;
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byteAddr = (u16) (address + i) % 2;
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svalue = (u16 *) value;
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if (!ath9k_hw_nvram_read(common, eepAddr, svalue)) {
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/*
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* Since we're reading the bytes in reverse order from a little-endian
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* word stream, an even address means we only use the lower half of
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* the 16-bit word at that address
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*/
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if (address % 2 == 0) {
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if (!ar9300_eeprom_read_byte(common, address--, buffer++))
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goto error;
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count--;
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}
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for (i = 0; i < count / 2; i++) {
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if (!ar9300_eeprom_read_word(common, address, buffer))
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goto error;
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address -= 2;
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buffer += 2;
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}
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if (count % 2)
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if (!ar9300_eeprom_read_byte(common, address, buffer))
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goto error;
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return true;
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error:
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ath_print(common, ATH_DBG_EEPROM,
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"unable to read eeprom region\n");
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"unable to read eeprom region at offset %d\n", address);
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return false;
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}
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*svalue = le16_to_cpu(*svalue);
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buffer[i] = value[byteAddr];
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}
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return true;
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}
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static bool ar9300_read_eeprom(struct ath_hw *ah,
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int address, u8 *buffer, int many)
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{
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int it;
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for (it = 0; it < many; it++)
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if (!ar9300_hw_read_eeprom(ah,
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(address - it),
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(buffer + it), 1))
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return false;
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return true;
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}
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static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
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int *length, int *major, int *minor)
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@ -927,30 +917,13 @@ fail:
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*/
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static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
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{
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u8 *mptr = NULL;
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int mdata_size;
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u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
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mptr = (u8 *) &ah->eeprom.ar9300_eep;
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mdata_size = sizeof(struct ar9300_eeprom);
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if (mptr && mdata_size > 0) {
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/* At this point, mptr points to the eeprom data structure
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* in it's "default" state. If this is big endian, swap the
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* data structures back to "little endian"
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*/
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/* First swap, default to Little Endian */
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#ifdef __BIG_ENDIAN
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ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
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#endif
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if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) >= 0)
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return true;
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/* Second Swap, back to Big Endian */
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#ifdef __BIG_ENDIAN
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ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
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#endif
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}
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if (ar9300_eeprom_restore_internal(ah, mptr,
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sizeof(struct ar9300_eeprom)) < 0)
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return false;
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return true;
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}
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/* XXX: review hardware docs */
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@ -998,21 +971,25 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
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static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
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{
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struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
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__le32 val;
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if (is2ghz)
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return eep->modalHeader2G.antCtrlCommon;
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val = eep->modalHeader2G.antCtrlCommon;
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else
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return eep->modalHeader5G.antCtrlCommon;
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val = eep->modalHeader5G.antCtrlCommon;
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return le32_to_cpu(val);
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}
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static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
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{
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struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
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__le32 val;
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if (is2ghz)
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return eep->modalHeader2G.antCtrlCommon2;
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val = eep->modalHeader2G.antCtrlCommon2;
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else
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return eep->modalHeader5G.antCtrlCommon2;
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val = eep->modalHeader5G.antCtrlCommon2;
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return le32_to_cpu(val);
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}
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static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
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@ -1020,15 +997,16 @@ static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
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bool is2ghz)
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{
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struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
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__le16 val = 0;
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if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
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if (is2ghz)
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return eep->modalHeader2G.antCtrlChain[chain];
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val = eep->modalHeader2G.antCtrlChain[chain];
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else
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return eep->modalHeader5G.antCtrlChain[chain];
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val = eep->modalHeader5G.antCtrlChain[chain];
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}
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return 0;
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return le16_to_cpu(val);
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}
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static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
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@ -169,7 +169,7 @@ enum CompressAlgorithm {
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};
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struct ar9300_base_eep_hdr {
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u16 regDmn[2];
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__le16 regDmn[2];
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/* 4 bits tx and 4 bits rx */
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u8 txrxMask;
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struct eepFlags opCapFlags;
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@ -199,16 +199,16 @@ struct ar9300_base_eep_hdr {
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u8 rxBandSelectGpio;
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u8 txrxgain;
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/* SW controlled internal regulator fields */
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u32 swreg;
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__le32 swreg;
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} __packed;
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struct ar9300_modal_eep_header {
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/* 4 idle, t1, t2, b (4 bits per setting) */
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u32 antCtrlCommon;
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__le32 antCtrlCommon;
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/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
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u32 antCtrlCommon2;
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__le32 antCtrlCommon2;
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/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
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u16 antCtrlChain[AR9300_MAX_CHAINS];
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__le16 antCtrlChain[AR9300_MAX_CHAINS];
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/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
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u8 xatten1DB[AR9300_MAX_CHAINS];
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/* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
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