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cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors
Add EPP driver support for AMD SoCs which support a dedicated MSR for CPPC. EPP is used by the DPM controller to configure the frequency that a core operates at during short periods of activity. The SoC EPP targets are configured on a scale from 0 to 255 where 0 represents maximum performance and 255 represents maximum efficiency. The amd-pstate driver exports profile string names to userspace that are tied to specific EPP values. The balance_performance string (0x80) provides the best balance for efficiency versus power on most systems, but users can choose other strings to meet their needs as well. $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_preferences default performance balance_performance balance_power power $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preference balance_performance To enable the driver,it needs to add `amd_pstate=active` to kernel command line and kernel will load the active mode epp driver Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Mario Limonciello <Mario.Limonciello@amd.com> Reviewed-by: Wyes Karny <wyes.karny@amd.com> Tested-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Perry Yuan
Rafael J. Wysocki
parent
36c5014e54
commit
ffa5096a7c
@ -59,9 +59,52 @@
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* we disable it by default to go acpi-cpufreq on these processors and add a
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* module parameter to be able to enable it manually for debugging.
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*/
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static struct cpufreq_driver *current_pstate_driver;
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static struct cpufreq_driver amd_pstate_driver;
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static struct cpufreq_driver amd_pstate_epp_driver;
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static int cppc_state = AMD_PSTATE_DISABLE;
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/*
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* AMD Energy Preference Performance (EPP)
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* The EPP is used in the CCLK DPM controller to drive
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* the frequency that a core is going to operate during
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* short periods of activity. EPP values will be utilized for
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* different OS profiles (balanced, performance, power savings)
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* display strings corresponding to EPP index in the
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* energy_perf_strings[]
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* index String
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*-------------------------------------
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* 0 default
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* 1 performance
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* 2 balance_performance
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* 3 balance_power
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* 4 power
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*/
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enum energy_perf_value_index {
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EPP_INDEX_DEFAULT = 0,
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EPP_INDEX_PERFORMANCE,
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EPP_INDEX_BALANCE_PERFORMANCE,
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EPP_INDEX_BALANCE_POWERSAVE,
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EPP_INDEX_POWERSAVE,
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};
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static const char * const energy_perf_strings[] = {
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[EPP_INDEX_DEFAULT] = "default",
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[EPP_INDEX_PERFORMANCE] = "performance",
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[EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
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[EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
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[EPP_INDEX_POWERSAVE] = "power",
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NULL
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};
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static unsigned int epp_values[] = {
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[EPP_INDEX_DEFAULT] = 0,
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[EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE,
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[EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE,
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[EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE,
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[EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
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};
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static inline int get_mode_idx_from_str(const char *str, size_t size)
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{
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int i;
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@ -73,6 +116,114 @@ static inline int get_mode_idx_from_str(const char *str, size_t size)
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return -EINVAL;
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}
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static DEFINE_MUTEX(amd_pstate_limits_lock);
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static DEFINE_MUTEX(amd_pstate_driver_lock);
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static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
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{
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u64 epp;
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int ret;
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if (boot_cpu_has(X86_FEATURE_CPPC)) {
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if (!cppc_req_cached) {
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epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
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&cppc_req_cached);
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if (epp)
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return epp;
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}
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epp = (cppc_req_cached >> 24) & 0xFF;
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} else {
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ret = cppc_get_epp_perf(cpudata->cpu, &epp);
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if (ret < 0) {
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pr_debug("Could not retrieve energy perf value (%d)\n", ret);
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return -EIO;
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}
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}
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return (s16)(epp & 0xff);
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}
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static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata)
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{
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s16 epp;
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int index = -EINVAL;
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epp = amd_pstate_get_epp(cpudata, 0);
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if (epp < 0)
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return epp;
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switch (epp) {
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case AMD_CPPC_EPP_PERFORMANCE:
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index = EPP_INDEX_PERFORMANCE;
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break;
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case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
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index = EPP_INDEX_BALANCE_PERFORMANCE;
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break;
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case AMD_CPPC_EPP_BALANCE_POWERSAVE:
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index = EPP_INDEX_BALANCE_POWERSAVE;
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break;
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case AMD_CPPC_EPP_POWERSAVE:
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index = EPP_INDEX_POWERSAVE;
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break;
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default:
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break;
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}
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return index;
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}
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static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
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{
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int ret;
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struct cppc_perf_ctrls perf_ctrls;
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if (boot_cpu_has(X86_FEATURE_CPPC)) {
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u64 value = READ_ONCE(cpudata->cppc_req_cached);
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value &= ~GENMASK_ULL(31, 24);
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value |= (u64)epp << 24;
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
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if (!ret)
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cpudata->epp_cached = epp;
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} else {
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perf_ctrls.energy_perf = epp;
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ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
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if (ret) {
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pr_debug("failed to set energy perf value (%d)\n", ret);
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return ret;
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}
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cpudata->epp_cached = epp;
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}
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return ret;
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}
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static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
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int pref_index)
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{
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int epp = -EINVAL;
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int ret;
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if (!pref_index) {
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pr_debug("EPP pref_index is invalid\n");
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return -EINVAL;
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}
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if (epp == -EINVAL)
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epp = epp_values[pref_index];
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if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
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pr_debug("EPP cannot be set under performance policy\n");
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return -EBUSY;
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}
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ret = amd_pstate_set_epp(cpudata, epp);
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return ret;
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}
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static inline int pstate_enable(bool enable)
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{
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return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable);
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@ -81,11 +232,21 @@ static inline int pstate_enable(bool enable)
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static int cppc_enable(bool enable)
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{
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int cpu, ret = 0;
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struct cppc_perf_ctrls perf_ctrls;
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for_each_present_cpu(cpu) {
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ret = cppc_set_enable(cpu, enable);
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if (ret)
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return ret;
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/* Enable autonomous mode for EPP */
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if (cppc_state == AMD_PSTATE_ACTIVE) {
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/* Set desired perf as zero to allow EPP firmware control */
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perf_ctrls.desired_perf = 0;
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ret = cppc_set_perf(cpu, &perf_ctrls);
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if (ret)
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return ret;
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}
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}
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return ret;
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@ -429,7 +590,7 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata)
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return;
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cpudata->boost_supported = true;
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amd_pstate_driver.boost_enabled = true;
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current_pstate_driver->boost_enabled = true;
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}
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static void amd_perf_ctl_reset(unsigned int cpu)
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@ -603,10 +764,61 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
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return sprintf(&buf[0], "%u\n", perf);
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}
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static ssize_t show_energy_performance_available_preferences(
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struct cpufreq_policy *policy, char *buf)
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{
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int i = 0;
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int offset = 0;
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while (energy_perf_strings[i] != NULL)
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offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i++]);
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sysfs_emit_at(buf, offset, "\n");
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return offset;
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}
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static ssize_t store_energy_performance_preference(
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struct cpufreq_policy *policy, const char *buf, size_t count)
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{
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struct amd_cpudata *cpudata = policy->driver_data;
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char str_preference[21];
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ssize_t ret;
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ret = sscanf(buf, "%20s", str_preference);
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if (ret != 1)
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return -EINVAL;
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ret = match_string(energy_perf_strings, -1, str_preference);
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if (ret < 0)
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return -EINVAL;
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mutex_lock(&amd_pstate_limits_lock);
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ret = amd_pstate_set_energy_pref_index(cpudata, ret);
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mutex_unlock(&amd_pstate_limits_lock);
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return ret ?: count;
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}
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static ssize_t show_energy_performance_preference(
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struct cpufreq_policy *policy, char *buf)
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{
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struct amd_cpudata *cpudata = policy->driver_data;
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int preference;
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preference = amd_pstate_get_energy_pref_index(cpudata);
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if (preference < 0)
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return preference;
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return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]);
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}
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cpufreq_freq_attr_ro(amd_pstate_max_freq);
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cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
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cpufreq_freq_attr_ro(amd_pstate_highest_perf);
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cpufreq_freq_attr_rw(energy_performance_preference);
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cpufreq_freq_attr_ro(energy_performance_available_preferences);
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static struct freq_attr *amd_pstate_attr[] = {
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&amd_pstate_max_freq,
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@ -615,6 +827,186 @@ static struct freq_attr *amd_pstate_attr[] = {
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NULL,
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};
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static struct freq_attr *amd_pstate_epp_attr[] = {
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&amd_pstate_max_freq,
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&amd_pstate_lowest_nonlinear_freq,
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&amd_pstate_highest_perf,
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&energy_performance_preference,
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&energy_performance_available_preferences,
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NULL,
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};
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static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
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{
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int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
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struct amd_cpudata *cpudata;
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struct device *dev;
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int rc;
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u64 value;
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/*
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* Resetting PERF_CTL_MSR will put the CPU in P0 frequency,
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* which is ideal for initialization process.
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*/
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amd_perf_ctl_reset(policy->cpu);
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dev = get_cpu_device(policy->cpu);
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if (!dev)
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goto free_cpudata1;
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cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
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if (!cpudata)
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return -ENOMEM;
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cpudata->cpu = policy->cpu;
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cpudata->epp_policy = 0;
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rc = amd_pstate_init_perf(cpudata);
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if (rc)
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goto free_cpudata1;
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min_freq = amd_get_min_freq(cpudata);
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max_freq = amd_get_max_freq(cpudata);
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nominal_freq = amd_get_nominal_freq(cpudata);
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lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata);
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if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) {
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dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n",
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min_freq, max_freq);
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ret = -EINVAL;
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goto free_cpudata1;
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}
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policy->cpuinfo.min_freq = min_freq;
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policy->cpuinfo.max_freq = max_freq;
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/* It will be updated by governor */
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policy->cur = policy->cpuinfo.min_freq;
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/* Initial processor data capability frequencies */
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cpudata->max_freq = max_freq;
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cpudata->min_freq = min_freq;
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cpudata->nominal_freq = nominal_freq;
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cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq;
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policy->driver_data = cpudata;
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cpudata->epp_cached = amd_pstate_get_epp(cpudata, 0);
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policy->min = policy->cpuinfo.min_freq;
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policy->max = policy->cpuinfo.max_freq;
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/*
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* Set the policy to powersave to provide a valid fallback value in case
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* the default cpufreq governor is neither powersave nor performance.
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*/
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policy->policy = CPUFREQ_POLICY_POWERSAVE;
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if (boot_cpu_has(X86_FEATURE_CPPC)) {
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policy->fast_switch_possible = true;
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ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
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if (ret)
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return ret;
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
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if (ret)
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return ret;
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WRITE_ONCE(cpudata->cppc_cap1_cached, value);
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}
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amd_pstate_boost_init(cpudata);
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return 0;
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free_cpudata1:
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kfree(cpudata);
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return ret;
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}
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static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)
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{
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pr_debug("CPU %d exiting\n", policy->cpu);
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policy->fast_switch_possible = false;
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return 0;
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}
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static void amd_pstate_epp_init(unsigned int cpu)
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{
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struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
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struct amd_cpudata *cpudata = policy->driver_data;
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u32 max_perf, min_perf;
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u64 value;
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s16 epp;
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max_perf = READ_ONCE(cpudata->highest_perf);
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min_perf = READ_ONCE(cpudata->lowest_perf);
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value = READ_ONCE(cpudata->cppc_req_cached);
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if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
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min_perf = max_perf;
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/* Initial min/max values for CPPC Performance Controls Register */
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value &= ~AMD_CPPC_MIN_PERF(~0L);
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value |= AMD_CPPC_MIN_PERF(min_perf);
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value &= ~AMD_CPPC_MAX_PERF(~0L);
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value |= AMD_CPPC_MAX_PERF(max_perf);
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/* CPPC EPP feature require to set zero to the desire perf bit */
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value &= ~AMD_CPPC_DES_PERF(~0L);
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value |= AMD_CPPC_DES_PERF(0);
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if (cpudata->epp_policy == cpudata->policy)
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goto skip_epp;
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cpudata->epp_policy = cpudata->policy;
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if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
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epp = amd_pstate_get_epp(cpudata, value);
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if (epp < 0)
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goto skip_epp;
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/* force the epp value to be zero for performance policy */
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epp = 0;
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} else {
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/* Get BIOS pre-defined epp value */
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epp = amd_pstate_get_epp(cpudata, value);
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if (epp)
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goto skip_epp;
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}
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/* Set initial EPP value */
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if (boot_cpu_has(X86_FEATURE_CPPC)) {
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value &= ~GENMASK_ULL(31, 24);
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value |= (u64)epp << 24;
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}
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skip_epp:
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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amd_pstate_set_epp(cpudata, epp);
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cpufreq_cpu_put(policy);
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}
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static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
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{
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struct amd_cpudata *cpudata = policy->driver_data;
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if (!policy->cpuinfo.max_freq)
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return -ENODEV;
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pr_debug("set_policy: cpuinfo.max %u policy->max %u\n",
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policy->cpuinfo.max_freq, policy->max);
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cpudata->policy = policy->policy;
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amd_pstate_epp_init(policy->cpu);
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return 0;
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}
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static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy)
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{
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cpufreq_verify_within_cpu_limits(policy);
|
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pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct cpufreq_driver amd_pstate_driver = {
|
||||
.flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
|
||||
.verify = amd_pstate_verify,
|
||||
@ -628,6 +1020,16 @@ static struct cpufreq_driver amd_pstate_driver = {
|
||||
.attr = amd_pstate_attr,
|
||||
};
|
||||
|
||||
static struct cpufreq_driver amd_pstate_epp_driver = {
|
||||
.flags = CPUFREQ_CONST_LOOPS,
|
||||
.verify = amd_pstate_epp_verify_policy,
|
||||
.setpolicy = amd_pstate_epp_set_policy,
|
||||
.init = amd_pstate_epp_cpu_init,
|
||||
.exit = amd_pstate_epp_cpu_exit,
|
||||
.name = "amd_pstate_epp",
|
||||
.attr = amd_pstate_epp_attr,
|
||||
};
|
||||
|
||||
static int __init amd_pstate_init(void)
|
||||
{
|
||||
int ret;
|
||||
@ -656,7 +1058,8 @@ static int __init amd_pstate_init(void)
|
||||
/* capability check */
|
||||
if (boot_cpu_has(X86_FEATURE_CPPC)) {
|
||||
pr_debug("AMD CPPC MSR based functionality is supported\n");
|
||||
amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
|
||||
if (cppc_state == AMD_PSTATE_PASSIVE)
|
||||
current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
|
||||
} else {
|
||||
pr_debug("AMD CPPC shared memory based functionality is supported\n");
|
||||
static_call_update(amd_pstate_enable, cppc_enable);
|
||||
@ -667,14 +1070,13 @@ static int __init amd_pstate_init(void)
|
||||
/* enable amd pstate feature */
|
||||
ret = amd_pstate_enable(true);
|
||||
if (ret) {
|
||||
pr_err("failed to enable amd-pstate with return %d\n", ret);
|
||||
pr_err("failed to enable with return %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = cpufreq_register_driver(&amd_pstate_driver);
|
||||
ret = cpufreq_register_driver(current_pstate_driver);
|
||||
if (ret)
|
||||
pr_err("failed to register amd_pstate_driver with return %d\n",
|
||||
ret);
|
||||
pr_err("failed to register with return %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -696,6 +1098,12 @@ static int __init amd_pstate_param(char *str)
|
||||
if (cppc_state == AMD_PSTATE_DISABLE)
|
||||
pr_info("driver is explicitly disabled\n");
|
||||
|
||||
if (cppc_state == AMD_PSTATE_ACTIVE)
|
||||
current_pstate_driver = &amd_pstate_epp_driver;
|
||||
|
||||
if (cppc_state == AMD_PSTATE_PASSIVE)
|
||||
current_pstate_driver = &amd_pstate_driver;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -12,6 +12,11 @@
|
||||
|
||||
#include <linux/pm_qos.h>
|
||||
|
||||
#define AMD_CPPC_EPP_PERFORMANCE 0x00
|
||||
#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
|
||||
#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF
|
||||
#define AMD_CPPC_EPP_POWERSAVE 0xFF
|
||||
|
||||
/*********************************************************************
|
||||
* AMD P-state INTERFACE *
|
||||
*********************************************************************/
|
||||
@ -47,6 +52,10 @@ struct amd_aperf_mperf {
|
||||
* @prev: Last Aperf/Mperf/tsc count value read from register
|
||||
* @freq: current cpu frequency value
|
||||
* @boost_supported: check whether the Processor or SBIOS supports boost mode
|
||||
* @epp_policy: Last saved policy used to set energy-performance preference
|
||||
* @epp_cached: Cached CPPC energy-performance preference value
|
||||
* @policy: Cpufreq policy value
|
||||
* @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value
|
||||
*
|
||||
* The amd_cpudata is key private data for each CPU thread in AMD P-State, and
|
||||
* represents all the attributes and goals that AMD P-State requests at runtime.
|
||||
@ -72,6 +81,12 @@ struct amd_cpudata {
|
||||
|
||||
u64 freq;
|
||||
bool boost_supported;
|
||||
|
||||
/* EPP feature related attributes*/
|
||||
s16 epp_policy;
|
||||
s16 epp_cached;
|
||||
u32 policy;
|
||||
u64 cppc_cap1_cached;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -90,5 +105,4 @@ static const char * const amd_pstate_mode_string[] = {
|
||||
[AMD_PSTATE_ACTIVE] = "active",
|
||||
NULL,
|
||||
};
|
||||
|
||||
#endif /* _LINUX_AMD_PSTATE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user