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ASoC: cs35l41: Move cs35l41 fs errata into shared code
This sequence is required to setup firmware, and will be needed for hda driver. Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220509214703.4482-8-vitalyr@opensource.cirrus.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -879,6 +879,7 @@ int cs35l41_set_channels(struct device *dev, struct regmap *reg,
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int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg);
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int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
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enum cs35l41_cspl_mbox_cmd cmd);
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int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap);
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int cs35l41_init_boost(struct device *dev, struct regmap *regmap,
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struct cs35l41_hw_cfg *hw_cfg);
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bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type);
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@ -667,6 +667,25 @@ static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
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{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
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};
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static const struct reg_sequence cs35l41_fs_errata_patch[] = {
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{ CS35L41_DSP1_RX1_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX2_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX3_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX4_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX5_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX6_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX7_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX8_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX1_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX2_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX3_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX4_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX5_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX6_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX7_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX8_RATE, 0x00000001 },
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};
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static const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = {
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{
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.id = 0x01,
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@ -1263,6 +1282,19 @@ int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
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}
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EXPORT_SYMBOL_GPL(cs35l41_set_cspl_mbox_cmd);
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int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap)
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{
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int ret;
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ret = regmap_multi_reg_write(regmap, cs35l41_fs_errata_patch,
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ARRAY_SIZE(cs35l41_fs_errata_patch));
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if (ret < 0)
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dev_err(dev, "Failed to write fs errata: %d\n", ret);
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return ret;
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}
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EXPORT_SYMBOL_GPL(cs35l41_write_fs_errata);
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MODULE_DESCRIPTION("CS35L41 library");
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MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
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MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>");
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@ -1093,25 +1093,6 @@ static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cf
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return 0;
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}
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static const struct reg_sequence cs35l41_fs_errata_patch[] = {
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{ CS35L41_DSP1_RX1_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX2_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX3_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX4_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX5_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX6_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX7_RATE, 0x00000001 },
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{ CS35L41_DSP1_RX8_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX1_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX2_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX3_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX4_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX5_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX6_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX7_RATE, 0x00000001 },
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{ CS35L41_DSP1_TX8_RATE, 0x00000001 },
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};
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static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
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{
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struct wm_adsp *dsp;
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@ -1132,12 +1113,9 @@ static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
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dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l41_dsp1_regions);
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dsp->cs_dsp.lock_regions = 0xFFFFFFFF;
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ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_fs_errata_patch,
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ARRAY_SIZE(cs35l41_fs_errata_patch));
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if (ret < 0) {
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dev_err(cs35l41->dev, "Failed to write fs errata: %d\n", ret);
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ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
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if (ret < 0)
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return ret;
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}
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ret = wm_halo_init(dsp);
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if (ret) {
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