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[MIPS] Alchemy common headers style cleanup
Fix several errors and warnings given by checkpatch.pl: - space after opening and before closing parentheses; - opening brace following 'struct' not on the same line; - leading spaces instead of tabs; - use of C99 // comments; - macros with complex values not enclosed in parentheses; - missing space between the type and asterisk in a variable declaration; - space between asterisk and function name; - including <asm/io.h> instead of <linux/io.h> and <asm/irq.h> instead of <linux/irq.h>; - use of '__inline__' instead of 'inline'; - space between function name and opening parenthesis; - line over 80 characters. In addition to these changes, also do the following: - remove needless parentheses; - insert spaces between operator and its operands; - replace spaces after the macro name with tabs in the #define directives and after the type in the structure field declarations; - remove excess tabs after the macro name in the #define directives and in the 'extern' variable declarations; - remove excess spaces between # and define for the SSI_*_MASK macros to align with other such macros; - put '||' operator on the same line with its first operand; - properly indent multi-line function prototypes; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line and/or adding space/asterisk on their left side; - make two-line comments that only have one line of text one-line; - convert the large multi-line comment in au1xxx_ide.h into several one-liners, replace spaces with tabs there; - fix typos/errors, capitalize acronyms, etc. in the comments; - insert missing and remove excess new lines; - update MontaVista copyright; - remove Pete Popov's and Steve Longerbeam's old email addresses... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Sergei Shtylyov
Ralf Baechle
parent
ad1d77a385
commit
ff6814d530
File diff suppressed because it is too large
Load Diff
@ -1,11 +1,10 @@
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/*
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* BRIEF MODULE DESCRIPTION
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* Defines for using and allocating dma channels on the Alchemy
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* Au1000 mips processor.
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* Defines for using and allocating DMA channels on the Alchemy
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* Au1x00 MIPS processors.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* stevel@mvista.com or source@mvista.com
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -31,7 +30,7 @@
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#ifndef __ASM_AU1000_DMA_H
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#define __ASM_AU1000_DMA_H
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#include <asm/io.h> /* need byte IO */
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#include <linux/io.h> /* need byte IO */
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#include <linux/spinlock.h> /* And spinlocks */
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#include <linux/delay.h>
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#include <asm/system.h>
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@ -50,36 +49,36 @@
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#define DMA_DAH_MASK (0x0f << 20)
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#define DMA_DID_BIT 16
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#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
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#define DMA_DS (1<<15)
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#define DMA_BE (1<<13)
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#define DMA_DR (1<<12)
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#define DMA_TS8 (1<<11)
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#define DMA_DS (1 << 15)
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#define DMA_BE (1 << 13)
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#define DMA_DR (1 << 12)
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#define DMA_TS8 (1 << 11)
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#define DMA_DW_BIT 9
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#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
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#define DMA_DW8 (0 << DMA_DW_BIT)
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#define DMA_DW16 (1 << DMA_DW_BIT)
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#define DMA_DW32 (2 << DMA_DW_BIT)
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#define DMA_NC (1<<8)
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#define DMA_IE (1<<7)
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#define DMA_HALT (1<<6)
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#define DMA_GO (1<<5)
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#define DMA_AB (1<<4)
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#define DMA_D1 (1<<3)
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#define DMA_BE1 (1<<2)
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#define DMA_D0 (1<<1)
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#define DMA_BE0 (1<<0)
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#define DMA_NC (1 << 8)
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#define DMA_IE (1 << 7)
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#define DMA_HALT (1 << 6)
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#define DMA_GO (1 << 5)
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#define DMA_AB (1 << 4)
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#define DMA_D1 (1 << 3)
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#define DMA_BE1 (1 << 2)
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#define DMA_D0 (1 << 1)
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#define DMA_BE0 (1 << 0)
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#define DMA_PERIPHERAL_ADDR 0x00000008
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#define DMA_BUFFER0_START 0x0000000C
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#define DMA_BUFFER1_START 0x00000014
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#define DMA_BUFFER0_COUNT 0x00000010
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#define DMA_BUFFER1_COUNT 0x00000018
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#define DMA_BAH_BIT 16
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#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
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#define DMA_COUNT_BIT 0
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#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
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#define DMA_PERIPHERAL_ADDR 0x00000008
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#define DMA_BUFFER0_START 0x0000000C
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#define DMA_BUFFER1_START 0x00000014
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#define DMA_BUFFER0_COUNT 0x00000010
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#define DMA_BUFFER1_COUNT 0x00000018
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#define DMA_BAH_BIT 16
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#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
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#define DMA_COUNT_BIT 0
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#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
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/* DMA Device ID's follow */
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/* DMA Device IDs follow */
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enum {
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DMA_ID_UART0_TX = 0,
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DMA_ID_UART0_RX,
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@ -110,7 +109,8 @@ enum {
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};
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struct dma_chan {
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int dev_id; // this channel is allocated if >=0, free otherwise
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int dev_id; /* this channel is allocated if >= 0, */
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/* free otherwise */
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unsigned int io;
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const char *dev_str;
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int irq;
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@ -132,23 +132,23 @@ extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
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extern void dump_au1000_dma_channel(unsigned int dmanr);
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extern spinlock_t au1000_dma_spin_lock;
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static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
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static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
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{
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if (dmanr >= NUM_AU1000_DMA_CHANNELS
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|| au1000_dma_table[dmanr].dev_id < 0)
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if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
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au1000_dma_table[dmanr].dev_id < 0)
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return NULL;
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return &au1000_dma_table[dmanr];
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}
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static __inline__ unsigned long claim_dma_lock(void)
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static inline unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&au1000_dma_spin_lock, flags);
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return flags;
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}
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static __inline__ void release_dma_lock(unsigned long flags)
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static inline void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
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}
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@ -156,48 +156,53 @@ static __inline__ void release_dma_lock(unsigned long flags)
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/*
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* Set the DMA buffer enable bits in the mode register.
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*/
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static __inline__ void enable_dma_buffer0(unsigned int dmanr)
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static inline void enable_dma_buffer0(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
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}
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static __inline__ void enable_dma_buffer1(unsigned int dmanr)
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static inline void enable_dma_buffer1(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
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}
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static __inline__ void enable_dma_buffers(unsigned int dmanr)
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static inline void enable_dma_buffers(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
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}
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static __inline__ void start_dma(unsigned int dmanr)
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static inline void start_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(DMA_GO, chan->io + DMA_MODE_SET);
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}
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#define DMA_HALT_POLL 0x5000
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static __inline__ void halt_dma(unsigned int dmanr)
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static inline void halt_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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int i;
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if (!chan)
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return;
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au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
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// poll the halt bit
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/* Poll the halt bit */
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for (i = 0; i < DMA_HALT_POLL; i++)
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if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
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break;
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@ -205,55 +210,57 @@ static __inline__ void halt_dma(unsigned int dmanr)
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printk(KERN_INFO "halt_dma: HALT poll expired!\n");
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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static inline void disable_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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halt_dma(dmanr);
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// now we can disable the buffers
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/* Now we can disable the buffers */
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au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
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}
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static __inline__ int dma_halted(unsigned int dmanr)
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static inline int dma_halted(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 1;
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return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
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}
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/* initialize a DMA channel */
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static __inline__ void init_dma(unsigned int dmanr)
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/* Initialize a DMA channel. */
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static inline void init_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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u32 mode;
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if (!chan)
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return;
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disable_dma(dmanr);
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// set device FIFO address
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au_writel(CPHYSADDR(chan->fifo_addr),
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chan->io + DMA_PERIPHERAL_ADDR);
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/* Set device FIFO address */
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au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
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mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
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if (chan->irq)
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mode |= DMA_IE;
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au_writel(~mode, chan->io + DMA_MODE_CLEAR);
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au_writel(mode, chan->io + DMA_MODE_SET);
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au_writel(mode, chan->io + DMA_MODE_SET);
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}
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/*
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* set mode for a specific DMA channel
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* Set mode for a specific DMA channel
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*/
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static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
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static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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/*
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@ -266,36 +273,37 @@ static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
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chan->mode |= mode;
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}
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static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
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static inline unsigned int get_dma_mode(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 0;
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return chan->mode;
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}
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static __inline__ int get_dma_active_buffer(unsigned int dmanr)
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static inline int get_dma_active_buffer(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return -1;
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return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
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}
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/*
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* set the device FIFO address for a specific DMA channel - only
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* Set the device FIFO address for a specific DMA channel - only
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* applicable to GPO4 and GPO5. All the other devices have fixed
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* FIFO addresses.
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*/
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static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
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unsigned int a)
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static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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if (chan->mode & DMA_DS) /* second bank of device ids */
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if (chan->mode & DMA_DS) /* second bank of device IDs */
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return;
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if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
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@ -307,16 +315,19 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
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/*
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* Clear the DMA buffer done bits in the mode register.
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*/
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static __inline__ void clear_dma_done0(unsigned int dmanr)
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static inline void clear_dma_done0(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
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}
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static __inline__ void clear_dma_done1(unsigned int dmanr)
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static inline void clear_dma_done1(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
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@ -325,16 +336,17 @@ static __inline__ void clear_dma_done1(unsigned int dmanr)
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/*
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* This does nothing - not applicable to Au1000 DMA.
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*/
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static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
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static inline void set_dma_page(unsigned int dmanr, char pagenr)
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{
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}
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/*
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* Set Buffer 0 transfer address for specific DMA channel.
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*/
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static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
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static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(a, chan->io + DMA_BUFFER0_START);
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@ -343,9 +355,10 @@ static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
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/*
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* Set Buffer 1 transfer address for specific DMA channel.
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*/
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static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
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static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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au_writel(a, chan->io + DMA_BUFFER1_START);
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@ -355,10 +368,10 @@ static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
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/*
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* Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
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*/
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static __inline__ void set_dma_count0(unsigned int dmanr,
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unsigned int count)
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static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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count &= DMA_COUNT_MASK;
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@ -368,10 +381,10 @@ static __inline__ void set_dma_count0(unsigned int dmanr,
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/*
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* Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
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*/
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static __inline__ void set_dma_count1(unsigned int dmanr,
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unsigned int count)
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static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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count &= DMA_COUNT_MASK;
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@ -381,10 +394,10 @@ static __inline__ void set_dma_count1(unsigned int dmanr,
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/*
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* Set both buffer transfer sizes (max 64k) for a specific DMA channel.
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*/
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static __inline__ void set_dma_count(unsigned int dmanr,
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unsigned int count)
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static inline void set_dma_count(unsigned int dmanr, unsigned int count)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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count &= DMA_COUNT_MASK;
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@ -396,35 +409,36 @@ static __inline__ void set_dma_count(unsigned int dmanr,
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* Returns which buffer has its done bit set in the mode register.
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* Returns -1 if neither or both done bits set.
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*/
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static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
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static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 0;
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return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
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return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
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}
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/*
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* Returns the DMA channel's Buffer Done IRQ number.
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*/
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static __inline__ int get_dma_done_irq(unsigned int dmanr)
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static inline int get_dma_done_irq(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return -1;
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return chan->irq;
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}
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/*
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* Get DMA residue count. Returns the number of _bytes_ left to transfer.
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*/
|
||||
static __inline__ int get_dma_residue(unsigned int dmanr)
|
||||
static inline int get_dma_residue(unsigned int dmanr)
|
||||
{
|
||||
int curBufCntReg, count;
|
||||
struct dma_chan *chan = get_dma_chan(dmanr);
|
||||
|
||||
if (!chan)
|
||||
return 0;
|
||||
|
||||
@ -442,4 +456,3 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
|
||||
}
|
||||
|
||||
#endif /* __ASM_AU1000_DMA_H */
|
||||
|
||||
|
||||
@ -2,12 +2,12 @@
|
||||
* FILE NAME au1000_gpio.h
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* API to Alchemy Au1000 GPIO device.
|
||||
* API to Alchemy Au1xx0 GPIO device.
|
||||
*
|
||||
* Author: MontaVista Software, Inc. <source@mvista.com>
|
||||
* Steve Longerbeam <stevel@mvista.com>
|
||||
* Steve Longerbeam
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Copyright 2001, 2008 MontaVista Software Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
@ -37,12 +37,12 @@
|
||||
|
||||
#define AU1000GPIO_IOC_MAGIC 'A'
|
||||
|
||||
#define AU1000GPIO_IN _IOR (AU1000GPIO_IOC_MAGIC, 0, int)
|
||||
#define AU1000GPIO_SET _IOW (AU1000GPIO_IOC_MAGIC, 1, int)
|
||||
#define AU1000GPIO_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 2, int)
|
||||
#define AU1000GPIO_OUT _IOW (AU1000GPIO_IOC_MAGIC, 3, int)
|
||||
#define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int)
|
||||
#define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int)
|
||||
#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
|
||||
#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
|
||||
#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
|
||||
#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
|
||||
#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
|
||||
#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
extern u32 get_au1000_avail_gpio_mask(void);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* au1550_spi.h - au1550 psc spi controller driver - platform data struct
|
||||
* au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
|
||||
*/
|
||||
|
||||
#ifndef _AU1550_SPI_H_
|
||||
|
||||
@ -23,10 +23,10 @@
|
||||
#ifndef _AU1XXX_H_
|
||||
#define _AU1XXX_H_
|
||||
|
||||
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
|
||||
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
|
||||
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
|
||||
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
|
||||
#include <asm/mach-db1x00/db1x00.h>
|
||||
|
||||
#elif defined(CONFIG_MIPS_PB1550)
|
||||
|
||||
@ -28,17 +28,18 @@
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
|
||||
* seen in the AU1550 part.
|
||||
/*
|
||||
* Specifics for the Au1xxx Descriptor-Based DMA Controller,
|
||||
* first seen in the AU1550 part.
|
||||
*/
|
||||
#ifndef _AU1000_DBDMA_H_
|
||||
#define _AU1000_DBDMA_H_
|
||||
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* The DMA base addresses.
|
||||
* The Channels are every 256 bytes (0x0100) from the channel 0 base.
|
||||
/*
|
||||
* The DMA base addresses.
|
||||
* The channels are every 256 bytes (0x0100) from the channel 0 base.
|
||||
* Interrupt status/enable is bits 15:0 for channels 15 to zero.
|
||||
*/
|
||||
#define DDMA_GLOBAL_BASE 0xb4003000
|
||||
@ -51,16 +52,14 @@ typedef volatile struct dbdma_global {
|
||||
u32 ddma_inten;
|
||||
} dbdma_global_t;
|
||||
|
||||
/* General Configuration.
|
||||
*/
|
||||
/* General Configuration. */
|
||||
#define DDMA_CONFIG_AF (1 << 2)
|
||||
#define DDMA_CONFIG_AH (1 << 1)
|
||||
#define DDMA_CONFIG_AL (1 << 0)
|
||||
|
||||
#define DDMA_THROTTLE_EN (1 << 31)
|
||||
|
||||
/* The structure of a DMA Channel.
|
||||
*/
|
||||
/* The structure of a DMA Channel. */
|
||||
typedef volatile struct au1xxx_dma_channel {
|
||||
u32 ddma_cfg; /* See below */
|
||||
u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
|
||||
@ -69,8 +68,7 @@ typedef volatile struct au1xxx_dma_channel {
|
||||
u32 ddma_irq; /* If bit 0 set, interrupt pending */
|
||||
u32 ddma_stat; /* See below */
|
||||
u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
|
||||
/* Remainder, up to the 256 byte boundary, is reserved.
|
||||
*/
|
||||
/* Remainder, up to the 256 byte boundary, is reserved. */
|
||||
} au1x_dma_chan_t;
|
||||
|
||||
#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
|
||||
@ -84,7 +82,8 @@ typedef volatile struct au1xxx_dma_channel {
|
||||
#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
|
||||
#define DDMA_CFG_EN (1 << 0) /* Channel enable */
|
||||
|
||||
/* Always set when descriptor processing done, regardless of
|
||||
/*
|
||||
* Always set when descriptor processing done, regardless of
|
||||
* interrupt enable state. Reflected in global intstat, don't
|
||||
* clear this until global intstat is read/used.
|
||||
*/
|
||||
@ -94,7 +93,8 @@ typedef volatile struct au1xxx_dma_channel {
|
||||
#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
|
||||
#define DDMA_STAT_H (1 << 0) /* Channel Halted */
|
||||
|
||||
/* "Standard" DDMA Descriptor.
|
||||
/*
|
||||
* "Standard" DDMA Descriptor.
|
||||
* Must be 32-byte aligned.
|
||||
*/
|
||||
typedef volatile struct au1xxx_ddma_desc {
|
||||
@ -106,8 +106,9 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
u32 dscr_dest1; /* See below */
|
||||
u32 dscr_stat; /* completion status */
|
||||
u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
|
||||
/* First 32bytes are HW specific!!!
|
||||
Lets have some SW data following.. make sure its 32bytes
|
||||
/*
|
||||
* First 32 bytes are HW specific!!!
|
||||
* Lets have some SW data following -- make sure it's 32 bytes.
|
||||
*/
|
||||
u32 sw_status;
|
||||
u32 sw_context;
|
||||
@ -130,10 +131,9 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
|
||||
#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
|
||||
|
||||
#define SW_STATUS_INUSE (1<<0)
|
||||
#define SW_STATUS_INUSE (1 << 0)
|
||||
|
||||
/* Command 0 device IDs.
|
||||
*/
|
||||
/* Command 0 device IDs. */
|
||||
#ifdef CONFIG_SOC_AU1550
|
||||
#define DSCR_CMD0_UART0_TX 0
|
||||
#define DSCR_CMD0_UART0_RX 1
|
||||
@ -198,16 +198,15 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
#define DSCR_CMD0_THROTTLE 30
|
||||
#define DSCR_CMD0_ALWAYS 31
|
||||
#define DSCR_NDEV_IDS 32
|
||||
/* THis macro is used to find/create custom device types */
|
||||
#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
|
||||
#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
|
||||
|
||||
/* This macro is used to find/create custom device types */
|
||||
#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
|
||||
((d) & 0xFF))
|
||||
#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
|
||||
|
||||
#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
|
||||
#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
|
||||
|
||||
/* Source/Destination transfer width.
|
||||
*/
|
||||
/* Source/Destination transfer width. */
|
||||
#define DSCR_CMD0_BYTE 0
|
||||
#define DSCR_CMD0_HALFWORD 1
|
||||
#define DSCR_CMD0_WORD 2
|
||||
@ -215,16 +214,14 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
|
||||
#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
|
||||
|
||||
/* DDMA Descriptor Type.
|
||||
*/
|
||||
/* DDMA Descriptor Type. */
|
||||
#define DSCR_CMD0_STANDARD 0
|
||||
#define DSCR_CMD0_LITERAL 1
|
||||
#define DSCR_CMD0_CMP_BRANCH 2
|
||||
|
||||
#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
|
||||
|
||||
/* Status Instruction.
|
||||
*/
|
||||
/* Status Instruction. */
|
||||
#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
|
||||
#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
|
||||
#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
|
||||
@ -232,23 +229,20 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
|
||||
#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
|
||||
|
||||
/* Descriptor Command 1
|
||||
*/
|
||||
/* Descriptor Command 1. */
|
||||
#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
|
||||
#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
|
||||
#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
|
||||
#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
|
||||
|
||||
/* Flag description.
|
||||
*/
|
||||
/* Flag description. */
|
||||
#define DSCR_CMD1_FL_MEM_STRIDE0 0
|
||||
#define DSCR_CMD1_FL_MEM_STRIDE1 1
|
||||
#define DSCR_CMD1_FL_MEM_STRIDE2 2
|
||||
|
||||
#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
|
||||
|
||||
/* Source1, 1-dimensional stride.
|
||||
*/
|
||||
/* Source1, 1-dimensional stride. */
|
||||
#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
|
||||
#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
|
||||
#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
|
||||
@ -256,8 +250,7 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
|
||||
#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
|
||||
|
||||
/* Dest1, 1-dimensional stride.
|
||||
*/
|
||||
/* Dest1, 1-dimensional stride. */
|
||||
#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
|
||||
#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
|
||||
#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
|
||||
@ -279,29 +272,27 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
|
||||
#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
|
||||
|
||||
/* The next descriptor pointer.
|
||||
*/
|
||||
/* The next descriptor pointer. */
|
||||
#define DSCR_NXTPTR_MASK (0x07ffffff)
|
||||
#define DSCR_NXTPTR(x) ((x) >> 5)
|
||||
#define DSCR_GET_NXTPTR(x) ((x) << 5)
|
||||
#define DSCR_NXTPTR_MS (1 << 27)
|
||||
|
||||
/* The number of DBDMA channels.
|
||||
*/
|
||||
/* The number of DBDMA channels. */
|
||||
#define NUM_DBDMA_CHANS 16
|
||||
|
||||
/*
|
||||
* Ddma API definitions
|
||||
* DDMA API definitions
|
||||
* FIXME: may not fit to this header file
|
||||
*/
|
||||
typedef struct dbdma_device_table {
|
||||
u32 dev_id;
|
||||
u32 dev_flags;
|
||||
u32 dev_tsize;
|
||||
u32 dev_devwidth;
|
||||
u32 dev_physaddr; /* If FIFO */
|
||||
u32 dev_intlevel;
|
||||
u32 dev_intpolarity;
|
||||
u32 dev_id;
|
||||
u32 dev_flags;
|
||||
u32 dev_tsize;
|
||||
u32 dev_devwidth;
|
||||
u32 dev_physaddr; /* If FIFO */
|
||||
u32 dev_intlevel;
|
||||
u32 dev_intpolarity;
|
||||
} dbdev_tab_t;
|
||||
|
||||
|
||||
@ -316,44 +307,41 @@ typedef struct dbdma_chan_config {
|
||||
au1x_ddma_desc_t *chan_desc_base;
|
||||
au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
|
||||
void *chan_callparam;
|
||||
void (*chan_callback)(int, void *);
|
||||
void (*chan_callback)(int, void *);
|
||||
} chan_tab_t;
|
||||
|
||||
#define DEV_FLAGS_INUSE (1 << 0)
|
||||
#define DEV_FLAGS_ANYUSE (1 << 1)
|
||||
#define DEV_FLAGS_OUT (1 << 2)
|
||||
#define DEV_FLAGS_IN (1 << 3)
|
||||
#define DEV_FLAGS_BURSTABLE (1 << 4)
|
||||
#define DEV_FLAGS_BURSTABLE (1 << 4)
|
||||
#define DEV_FLAGS_SYNC (1 << 5)
|
||||
/* end Ddma API definitions */
|
||||
/* end DDMA API definitions */
|
||||
|
||||
/* External functions for drivers to use.
|
||||
*/
|
||||
/* Use this to allocate a dbdma channel. The device ids are one of the
|
||||
* DSCR_CMD0 devices IDs, which is usually redefined to a more
|
||||
* meaningful name. The 'callback' is called during dma completion
|
||||
/*
|
||||
* External functions for drivers to use.
|
||||
* Use this to allocate a DBDMA channel. The device IDs are one of
|
||||
* the DSCR_CMD0 devices IDs, which is usually redefined to a more
|
||||
* meaningful name. The 'callback' is called during DMA completion
|
||||
* interrupt.
|
||||
*/
|
||||
extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
|
||||
void (*callback)(int, void *), void *callparam);
|
||||
void (*callback)(int, void *),
|
||||
void *callparam);
|
||||
|
||||
#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
|
||||
|
||||
/* Set the device width of a in/out fifo.
|
||||
*/
|
||||
/* Set the device width of an in/out FIFO. */
|
||||
u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
|
||||
|
||||
/* Allocate a ring of descriptors for dbdma.
|
||||
*/
|
||||
/* Allocate a ring of descriptors for DBDMA. */
|
||||
u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
|
||||
|
||||
/* Put buffers on source/destination descriptors.
|
||||
*/
|
||||
/* Put buffers on source/destination descriptors. */
|
||||
u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
|
||||
u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
|
||||
|
||||
/* Get a buffer from the destination descriptor.
|
||||
*/
|
||||
/* Get a buffer from the destination descriptor. */
|
||||
u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
|
||||
|
||||
void au1xxx_dbdma_stop(u32 chanid);
|
||||
@ -364,29 +352,34 @@ u32 au1xxx_get_dma_residue(u32 chanid);
|
||||
void au1xxx_dbdma_chan_free(u32 chanid);
|
||||
void au1xxx_dbdma_dump(u32 chanid);
|
||||
|
||||
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
|
||||
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
|
||||
|
||||
u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
|
||||
void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
|
||||
u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
|
||||
void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
|
||||
|
||||
/*
|
||||
Some compatibilty macros --
|
||||
Needed to make changes to API without breaking existing drivers
|
||||
*/
|
||||
#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
|
||||
#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
|
||||
#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
|
||||
* Some compatibilty macros -- needed to make changes to API
|
||||
* without breaking existing drivers.
|
||||
*/
|
||||
#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
|
||||
_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
|
||||
#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
|
||||
_au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
|
||||
#define put_source_flags(chanid, buf, nbytes, flags) \
|
||||
au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
|
||||
|
||||
|
||||
#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
|
||||
#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
|
||||
#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
|
||||
#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
|
||||
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
|
||||
#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
|
||||
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
|
||||
#define put_dest_flags(chanid, buf, nbytes, flags) \
|
||||
au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
|
||||
|
||||
/*
|
||||
* Flags for the put_source/put_dest functions.
|
||||
*/
|
||||
#define DDMA_FLAGS_IE (1<<0)
|
||||
#define DDMA_FLAGS_NOIE (1<<1)
|
||||
#define DDMA_FLAGS_IE (1 << 0)
|
||||
#define DDMA_FLAGS_NOIE (1 << 1)
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
#endif /* _AU1000_DBDMA_H_ */
|
||||
|
||||
@ -31,167 +31,164 @@
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
|
||||
#define DMA_WAIT_TIMEOUT 100
|
||||
#define NUM_DESCRIPTORS PRD_ENTRIES
|
||||
#define DMA_WAIT_TIMEOUT 100
|
||||
#define NUM_DESCRIPTORS PRD_ENTRIES
|
||||
#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
|
||||
#define NUM_DESCRIPTORS 2
|
||||
#define NUM_DESCRIPTORS 2
|
||||
#endif
|
||||
|
||||
#ifndef AU1XXX_ATA_RQSIZE
|
||||
#define AU1XXX_ATA_RQSIZE 128
|
||||
#define AU1XXX_ATA_RQSIZE 128
|
||||
#endif
|
||||
|
||||
/* Disable Burstable-Support for DBDMA */
|
||||
#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
|
||||
#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
|
||||
#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
/*
|
||||
* This will enable the device to be powered up when write() or read()
|
||||
* is called. If this is not defined, the driver will return -EBUSY.
|
||||
*/
|
||||
* This will enable the device to be powered up when write() or read()
|
||||
* is called. If this is not defined, the driver will return -EBUSY.
|
||||
*/
|
||||
#define WAKE_ON_ACCESS 1
|
||||
|
||||
typedef struct
|
||||
{
|
||||
spinlock_t lock; /* Used to block on state transitions */
|
||||
au1xxx_power_dev_t *dev; /* Power Managers device structure */
|
||||
unsigned stopped; /* USed to signaling device is stopped */
|
||||
typedef struct {
|
||||
spinlock_t lock; /* Used to block on state transitions */
|
||||
au1xxx_power_dev_t *dev; /* Power Managers device structure */
|
||||
unsigned stopped; /* Used to signal device is stopped */
|
||||
} pm_state;
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32 tx_dev_id, rx_dev_id, target_dev_id;
|
||||
u32 tx_chan, rx_chan;
|
||||
void *tx_desc_head, *rx_desc_head;
|
||||
ide_hwif_t *hwif;
|
||||
typedef struct {
|
||||
u32 tx_dev_id, rx_dev_id, target_dev_id;
|
||||
u32 tx_chan, rx_chan;
|
||||
void *tx_desc_head, *rx_desc_head;
|
||||
ide_hwif_t *hwif;
|
||||
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
|
||||
ide_drive_t *drive;
|
||||
struct dbdma_cmd *dma_table_cpu;
|
||||
dma_addr_t dma_table_dma;
|
||||
ide_drive_t *drive;
|
||||
struct dbdma_cmd *dma_table_cpu;
|
||||
dma_addr_t dma_table_dma;
|
||||
#endif
|
||||
int irq;
|
||||
u32 regbase;
|
||||
#ifdef CONFIG_PM
|
||||
pm_state pm;
|
||||
pm_state pm;
|
||||
#endif
|
||||
} _auide_hwif;
|
||||
|
||||
/*******************************************************************************
|
||||
* PIO Mode timing calculation : *
|
||||
* *
|
||||
* Static Bus Spec ATA Spec *
|
||||
* Tcsoe = t1 *
|
||||
* Toecs = t9 *
|
||||
* Twcs = t9 *
|
||||
* Tcsh = t2i | t2 *
|
||||
* Tcsoff = t2i | t2 *
|
||||
* Twp = t2 *
|
||||
* Tcsw = t1 *
|
||||
* Tpm = 0 *
|
||||
* Ta = t1+t2 *
|
||||
*******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/* PIO Mode timing calculation : */
|
||||
/* */
|
||||
/* Static Bus Spec ATA Spec */
|
||||
/* Tcsoe = t1 */
|
||||
/* Toecs = t9 */
|
||||
/* Twcs = t9 */
|
||||
/* Tcsh = t2i | t2 */
|
||||
/* Tcsoff = t2i | t2 */
|
||||
/* Twp = t2 */
|
||||
/* Tcsw = t1 */
|
||||
/* Tpm = 0 */
|
||||
/* Ta = t1+t2 */
|
||||
/******************************************************************************/
|
||||
|
||||
#define TCSOE_MASK (0x07<<29)
|
||||
#define TOECS_MASK (0x07<<26)
|
||||
#define TWCS_MASK (0x07<<28)
|
||||
#define TCSH_MASK (0x0F<<24)
|
||||
#define TCSOFF_MASK (0x07<<20)
|
||||
#define TWP_MASK (0x3F<<14)
|
||||
#define TCSW_MASK (0x0F<<10)
|
||||
#define TPM_MASK (0x0F<<6)
|
||||
#define TA_MASK (0x3F<<0)
|
||||
#define TS_MASK (1<<8)
|
||||
#define TCSOE_MASK (0x07 << 29)
|
||||
#define TOECS_MASK (0x07 << 26)
|
||||
#define TWCS_MASK (0x07 << 28)
|
||||
#define TCSH_MASK (0x0F << 24)
|
||||
#define TCSOFF_MASK (0x07 << 20)
|
||||
#define TWP_MASK (0x3F << 14)
|
||||
#define TCSW_MASK (0x0F << 10)
|
||||
#define TPM_MASK (0x0F << 6)
|
||||
#define TA_MASK (0x3F << 0)
|
||||
#define TS_MASK (1 << 8)
|
||||
|
||||
/* Timing parameters PIO mode 0 */
|
||||
#define SBC_IDE_PIO0_TCSOE (0x04<<29)
|
||||
#define SBC_IDE_PIO0_TOECS (0x01<<26)
|
||||
#define SBC_IDE_PIO0_TWCS (0x02<<28)
|
||||
#define SBC_IDE_PIO0_TCSH (0x08<<24)
|
||||
#define SBC_IDE_PIO0_TCSOFF (0x07<<20)
|
||||
#define SBC_IDE_PIO0_TWP (0x10<<14)
|
||||
#define SBC_IDE_PIO0_TCSW (0x04<<10)
|
||||
#define SBC_IDE_PIO0_TPM (0x0<<6)
|
||||
#define SBC_IDE_PIO0_TA (0x15<<0)
|
||||
#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
|
||||
#define SBC_IDE_PIO0_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_PIO0_TWCS (0x02 << 28)
|
||||
#define SBC_IDE_PIO0_TCSH (0x08 << 24)
|
||||
#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
|
||||
#define SBC_IDE_PIO0_TWP (0x10 << 14)
|
||||
#define SBC_IDE_PIO0_TCSW (0x04 << 10)
|
||||
#define SBC_IDE_PIO0_TPM (0x00 << 6)
|
||||
#define SBC_IDE_PIO0_TA (0x15 << 0)
|
||||
/* Timing parameters PIO mode 1 */
|
||||
#define SBC_IDE_PIO1_TCSOE (0x03<<29)
|
||||
#define SBC_IDE_PIO1_TOECS (0x01<<26)
|
||||
#define SBC_IDE_PIO1_TWCS (0x01<<28)
|
||||
#define SBC_IDE_PIO1_TCSH (0x06<<24)
|
||||
#define SBC_IDE_PIO1_TCSOFF (0x06<<20)
|
||||
#define SBC_IDE_PIO1_TWP (0x08<<14)
|
||||
#define SBC_IDE_PIO1_TCSW (0x03<<10)
|
||||
#define SBC_IDE_PIO1_TPM (0x00<<6)
|
||||
#define SBC_IDE_PIO1_TA (0x0B<<0)
|
||||
#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
|
||||
#define SBC_IDE_PIO1_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_PIO1_TWCS (0x01 << 28)
|
||||
#define SBC_IDE_PIO1_TCSH (0x06 << 24)
|
||||
#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
|
||||
#define SBC_IDE_PIO1_TWP (0x08 << 14)
|
||||
#define SBC_IDE_PIO1_TCSW (0x03 << 10)
|
||||
#define SBC_IDE_PIO1_TPM (0x00 << 6)
|
||||
#define SBC_IDE_PIO1_TA (0x0B << 0)
|
||||
/* Timing parameters PIO mode 2 */
|
||||
#define SBC_IDE_PIO2_TCSOE (0x05<<29)
|
||||
#define SBC_IDE_PIO2_TOECS (0x01<<26)
|
||||
#define SBC_IDE_PIO2_TWCS (0x01<<28)
|
||||
#define SBC_IDE_PIO2_TCSH (0x07<<24)
|
||||
#define SBC_IDE_PIO2_TCSOFF (0x07<<20)
|
||||
#define SBC_IDE_PIO2_TWP (0x1F<<14)
|
||||
#define SBC_IDE_PIO2_TCSW (0x05<<10)
|
||||
#define SBC_IDE_PIO2_TPM (0x00<<6)
|
||||
#define SBC_IDE_PIO2_TA (0x22<<0)
|
||||
#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
|
||||
#define SBC_IDE_PIO2_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_PIO2_TWCS (0x01 << 28)
|
||||
#define SBC_IDE_PIO2_TCSH (0x07 << 24)
|
||||
#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
|
||||
#define SBC_IDE_PIO2_TWP (0x1F << 14)
|
||||
#define SBC_IDE_PIO2_TCSW (0x05 << 10)
|
||||
#define SBC_IDE_PIO2_TPM (0x00 << 6)
|
||||
#define SBC_IDE_PIO2_TA (0x22 << 0)
|
||||
/* Timing parameters PIO mode 3 */
|
||||
#define SBC_IDE_PIO3_TCSOE (0x05<<29)
|
||||
#define SBC_IDE_PIO3_TOECS (0x01<<26)
|
||||
#define SBC_IDE_PIO3_TWCS (0x01<<28)
|
||||
#define SBC_IDE_PIO3_TCSH (0x0D<<24)
|
||||
#define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
|
||||
#define SBC_IDE_PIO3_TWP (0x15<<14)
|
||||
#define SBC_IDE_PIO3_TCSW (0x05<<10)
|
||||
#define SBC_IDE_PIO3_TPM (0x00<<6)
|
||||
#define SBC_IDE_PIO3_TA (0x1A<<0)
|
||||
#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
|
||||
#define SBC_IDE_PIO3_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_PIO3_TWCS (0x01 << 28)
|
||||
#define SBC_IDE_PIO3_TCSH (0x0D << 24)
|
||||
#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
|
||||
#define SBC_IDE_PIO3_TWP (0x15 << 14)
|
||||
#define SBC_IDE_PIO3_TCSW (0x05 << 10)
|
||||
#define SBC_IDE_PIO3_TPM (0x00 << 6)
|
||||
#define SBC_IDE_PIO3_TA (0x1A << 0)
|
||||
/* Timing parameters PIO mode 4 */
|
||||
#define SBC_IDE_PIO4_TCSOE (0x04<<29)
|
||||
#define SBC_IDE_PIO4_TOECS (0x01<<26)
|
||||
#define SBC_IDE_PIO4_TWCS (0x01<<28)
|
||||
#define SBC_IDE_PIO4_TCSH (0x04<<24)
|
||||
#define SBC_IDE_PIO4_TCSOFF (0x04<<20)
|
||||
#define SBC_IDE_PIO4_TWP (0x0D<<14)
|
||||
#define SBC_IDE_PIO4_TCSW (0x03<<10)
|
||||
#define SBC_IDE_PIO4_TPM (0x00<<6)
|
||||
#define SBC_IDE_PIO4_TA (0x12<<0)
|
||||
#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
|
||||
#define SBC_IDE_PIO4_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_PIO4_TWCS (0x01 << 28)
|
||||
#define SBC_IDE_PIO4_TCSH (0x04 << 24)
|
||||
#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
|
||||
#define SBC_IDE_PIO4_TWP (0x0D << 14)
|
||||
#define SBC_IDE_PIO4_TCSW (0x03 << 10)
|
||||
#define SBC_IDE_PIO4_TPM (0x00 << 6)
|
||||
#define SBC_IDE_PIO4_TA (0x12 << 0)
|
||||
/* Timing parameters MDMA mode 0 */
|
||||
#define SBC_IDE_MDMA0_TCSOE (0x03<<29)
|
||||
#define SBC_IDE_MDMA0_TOECS (0x01<<26)
|
||||
#define SBC_IDE_MDMA0_TWCS (0x01<<28)
|
||||
#define SBC_IDE_MDMA0_TCSH (0x07<<24)
|
||||
#define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
|
||||
#define SBC_IDE_MDMA0_TWP (0x0C<<14)
|
||||
#define SBC_IDE_MDMA0_TCSW (0x03<<10)
|
||||
#define SBC_IDE_MDMA0_TPM (0x00<<6)
|
||||
#define SBC_IDE_MDMA0_TA (0x0F<<0)
|
||||
#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
|
||||
#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
|
||||
#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
|
||||
#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
|
||||
#define SBC_IDE_MDMA0_TWP (0x0C << 14)
|
||||
#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
|
||||
#define SBC_IDE_MDMA0_TPM (0x00 << 6)
|
||||
#define SBC_IDE_MDMA0_TA (0x0F << 0)
|
||||
/* Timing parameters MDMA mode 1 */
|
||||
#define SBC_IDE_MDMA1_TCSOE (0x05<<29)
|
||||
#define SBC_IDE_MDMA1_TOECS (0x01<<26)
|
||||
#define SBC_IDE_MDMA1_TWCS (0x01<<28)
|
||||
#define SBC_IDE_MDMA1_TCSH (0x05<<24)
|
||||
#define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
|
||||
#define SBC_IDE_MDMA1_TWP (0x0F<<14)
|
||||
#define SBC_IDE_MDMA1_TCSW (0x05<<10)
|
||||
#define SBC_IDE_MDMA1_TPM (0x00<<6)
|
||||
#define SBC_IDE_MDMA1_TA (0x15<<0)
|
||||
#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
|
||||
#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
|
||||
#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
|
||||
#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
|
||||
#define SBC_IDE_MDMA1_TWP (0x0F << 14)
|
||||
#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
|
||||
#define SBC_IDE_MDMA1_TPM (0x00 << 6)
|
||||
#define SBC_IDE_MDMA1_TA (0x15 << 0)
|
||||
/* Timing parameters MDMA mode 2 */
|
||||
#define SBC_IDE_MDMA2_TCSOE (0x04<<29)
|
||||
#define SBC_IDE_MDMA2_TOECS (0x01<<26)
|
||||
#define SBC_IDE_MDMA2_TWCS (0x01<<28)
|
||||
#define SBC_IDE_MDMA2_TCSH (0x04<<24)
|
||||
#define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
|
||||
#define SBC_IDE_MDMA2_TWP (0x0D<<14)
|
||||
#define SBC_IDE_MDMA2_TCSW (0x04<<10)
|
||||
#define SBC_IDE_MDMA2_TPM (0x00<<6)
|
||||
#define SBC_IDE_MDMA2_TA (0x12<<0)
|
||||
#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
|
||||
#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
|
||||
#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
|
||||
#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
|
||||
#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
|
||||
#define SBC_IDE_MDMA2_TWP (0x0D << 14)
|
||||
#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
|
||||
#define SBC_IDE_MDMA2_TPM (0x00 << 6)
|
||||
#define SBC_IDE_MDMA2_TA (0x12 << 0)
|
||||
|
||||
#define SBC_IDE_TIMING(mode) \
|
||||
SBC_IDE_##mode##_TWCS | \
|
||||
SBC_IDE_##mode##_TCSH | \
|
||||
SBC_IDE_##mode##_TCSOFF | \
|
||||
SBC_IDE_##mode##_TWP | \
|
||||
SBC_IDE_##mode##_TCSW | \
|
||||
SBC_IDE_##mode##_TPM | \
|
||||
SBC_IDE_##mode##_TA
|
||||
(SBC_IDE_##mode##_TWCS | \
|
||||
SBC_IDE_##mode##_TCSH | \
|
||||
SBC_IDE_##mode##_TCSOFF | \
|
||||
SBC_IDE_##mode##_TWP | \
|
||||
SBC_IDE_##mode##_TCSW | \
|
||||
SBC_IDE_##mode##_TPM | \
|
||||
SBC_IDE_##mode##_TA)
|
||||
|
||||
@ -33,7 +33,6 @@
|
||||
#ifndef _AU1000_PSC_H_
|
||||
#define _AU1000_PSC_H_
|
||||
|
||||
|
||||
/* The PSC base addresses. */
|
||||
#ifdef CONFIG_SOC_AU1550
|
||||
#define PSC0_BASE_ADDR 0xb1a00000
|
||||
@ -47,8 +46,8 @@
|
||||
#define PSC1_BASE_ADDR 0xb1b00000
|
||||
#endif
|
||||
|
||||
/* The PSC select and control registers are common to
|
||||
* all protocols.
|
||||
/*
|
||||
* The PSC select and control registers are common to all protocols.
|
||||
*/
|
||||
#define PSC_SEL_OFFSET 0x00000000
|
||||
#define PSC_CTRL_OFFSET 0x00000004
|
||||
@ -59,18 +58,17 @@
|
||||
#define PSC_SEL_CLK_SERCLK (2 << 4)
|
||||
|
||||
#define PSC_SEL_PS_MASK 0x00000007
|
||||
#define PSC_SEL_PS_DISABLED (0)
|
||||
#define PSC_SEL_PS_SPIMODE (2)
|
||||
#define PSC_SEL_PS_I2SMODE (3)
|
||||
#define PSC_SEL_PS_AC97MODE (4)
|
||||
#define PSC_SEL_PS_SMBUSMODE (5)
|
||||
#define PSC_SEL_PS_DISABLED 0
|
||||
#define PSC_SEL_PS_SPIMODE 2
|
||||
#define PSC_SEL_PS_I2SMODE 3
|
||||
#define PSC_SEL_PS_AC97MODE 4
|
||||
#define PSC_SEL_PS_SMBUSMODE 5
|
||||
|
||||
#define PSC_CTRL_DISABLE (0)
|
||||
#define PSC_CTRL_SUSPEND (2)
|
||||
#define PSC_CTRL_ENABLE (3)
|
||||
#define PSC_CTRL_DISABLE 0
|
||||
#define PSC_CTRL_SUSPEND 2
|
||||
#define PSC_CTRL_ENABLE 3
|
||||
|
||||
/* AC97 Registers.
|
||||
*/
|
||||
/* AC97 Registers. */
|
||||
#define PSC_AC97CFG_OFFSET 0x00000008
|
||||
#define PSC_AC97MSK_OFFSET 0x0000000c
|
||||
#define PSC_AC97PCR_OFFSET 0x00000010
|
||||
@ -95,8 +93,7 @@
|
||||
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
|
||||
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
|
||||
|
||||
/* AC97 Config Register.
|
||||
*/
|
||||
/* AC97 Config Register. */
|
||||
#define PSC_AC97CFG_RT_MASK (3 << 30)
|
||||
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
|
||||
#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
|
||||
@ -118,20 +115,19 @@
|
||||
#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
|
||||
#define PSC_AC97CFG_GE_ENABLE (1)
|
||||
|
||||
/* Enable slots 3-12.
|
||||
*/
|
||||
/* Enable slots 3-12. */
|
||||
#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
|
||||
#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
|
||||
|
||||
/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
|
||||
/*
|
||||
* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
|
||||
* The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
|
||||
* arithmetic in the macro.
|
||||
*/
|
||||
#define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21)
|
||||
#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
|
||||
#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
|
||||
|
||||
/* AC97 Mask Register.
|
||||
*/
|
||||
/* AC97 Mask Register. */
|
||||
#define PSC_AC97MSK_GR (1 << 25)
|
||||
#define PSC_AC97MSK_CD (1 << 24)
|
||||
#define PSC_AC97MSK_RR (1 << 13)
|
||||
@ -148,8 +144,7 @@
|
||||
PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
|
||||
PSC_AC97MSK_RD | PSC_AC97MSK_TD)
|
||||
|
||||
/* AC97 Protocol Control Register.
|
||||
*/
|
||||
/* AC97 Protocol Control Register. */
|
||||
#define PSC_AC97PCR_RC (1 << 6)
|
||||
#define PSC_AC97PCR_RP (1 << 5)
|
||||
#define PSC_AC97PCR_RS (1 << 4)
|
||||
@ -157,8 +152,7 @@
|
||||
#define PSC_AC97PCR_TP (1 << 1)
|
||||
#define PSC_AC97PCR_TS (1 << 0)
|
||||
|
||||
/* AC97 Status register (read only).
|
||||
*/
|
||||
/* AC97 Status register (read only). */
|
||||
#define PSC_AC97STAT_CB (1 << 26)
|
||||
#define PSC_AC97STAT_CP (1 << 25)
|
||||
#define PSC_AC97STAT_CR (1 << 24)
|
||||
@ -174,8 +168,7 @@
|
||||
#define PSC_AC97STAT_DR (1 << 1)
|
||||
#define PSC_AC97STAT_SR (1 << 0)
|
||||
|
||||
/* AC97 Event Register.
|
||||
*/
|
||||
/* AC97 Event Register. */
|
||||
#define PSC_AC97EVNT_GR (1 << 25)
|
||||
#define PSC_AC97EVNT_CD (1 << 24)
|
||||
#define PSC_AC97EVNT_RR (1 << 13)
|
||||
@ -187,22 +180,18 @@
|
||||
#define PSC_AC97EVNT_RD (1 << 5)
|
||||
#define PSC_AC97EVNT_TD (1 << 4)
|
||||
|
||||
/* CODEC Command Register.
|
||||
*/
|
||||
/* CODEC Command Register. */
|
||||
#define PSC_AC97CDC_RD (1 << 25)
|
||||
#define PSC_AC97CDC_ID_MASK (3 << 23)
|
||||
#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
|
||||
#define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23)
|
||||
#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
|
||||
#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
|
||||
|
||||
/* AC97 Reset Control Register.
|
||||
*/
|
||||
/* AC97 Reset Control Register. */
|
||||
#define PSC_AC97RST_RST (1 << 1)
|
||||
#define PSC_AC97RST_SNC (1 << 0)
|
||||
|
||||
|
||||
/* PSC in I2S Mode.
|
||||
*/
|
||||
/* PSC in I2S Mode. */
|
||||
typedef struct psc_i2s {
|
||||
u32 psc_sel;
|
||||
u32 psc_ctrl;
|
||||
@ -215,8 +204,7 @@ typedef struct psc_i2s {
|
||||
u32 psc_i2sudf;
|
||||
} psc_i2s_t;
|
||||
|
||||
/* I2S Config Register.
|
||||
*/
|
||||
/* I2S Config Register. */
|
||||
#define PSC_I2SCFG_RT_MASK (3 << 30)
|
||||
#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
|
||||
#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
|
||||
@ -247,8 +235,7 @@ typedef struct psc_i2s {
|
||||
#define PSC_I2SCFG_MLJ (1 << 10)
|
||||
#define PSC_I2SCFG_XM (1 << 9)
|
||||
|
||||
/* The word length equation is simply LEN+1.
|
||||
*/
|
||||
/* The word length equation is simply LEN+1. */
|
||||
#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
|
||||
#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
|
||||
|
||||
@ -256,8 +243,7 @@ typedef struct psc_i2s {
|
||||
#define PSC_I2SCFG_MLF (1 << 1)
|
||||
#define PSC_I2SCFG_MS (1 << 0)
|
||||
|
||||
/* I2S Mask Register.
|
||||
*/
|
||||
/* I2S Mask Register. */
|
||||
#define PSC_I2SMSK_RR (1 << 13)
|
||||
#define PSC_I2SMSK_RO (1 << 12)
|
||||
#define PSC_I2SMSK_RU (1 << 11)
|
||||
@ -271,8 +257,7 @@ typedef struct psc_i2s {
|
||||
PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
|
||||
PSC_I2SMSK_RD | PSC_I2SMSK_TD)
|
||||
|
||||
/* I2S Protocol Control Register.
|
||||
*/
|
||||
/* I2S Protocol Control Register. */
|
||||
#define PSC_I2SPCR_RC (1 << 6)
|
||||
#define PSC_I2SPCR_RP (1 << 5)
|
||||
#define PSC_I2SPCR_RS (1 << 4)
|
||||
@ -280,8 +265,7 @@ typedef struct psc_i2s {
|
||||
#define PSC_I2SPCR_TP (1 << 1)
|
||||
#define PSC_I2SPCR_TS (1 << 0)
|
||||
|
||||
/* I2S Status register (read only).
|
||||
*/
|
||||
/* I2S Status register (read only). */
|
||||
#define PSC_I2SSTAT_RF (1 << 13)
|
||||
#define PSC_I2SSTAT_RE (1 << 12)
|
||||
#define PSC_I2SSTAT_RR (1 << 11)
|
||||
@ -294,8 +278,7 @@ typedef struct psc_i2s {
|
||||
#define PSC_I2SSTAT_DR (1 << 1)
|
||||
#define PSC_I2SSTAT_SR (1 << 0)
|
||||
|
||||
/* I2S Event Register.
|
||||
*/
|
||||
/* I2S Event Register. */
|
||||
#define PSC_I2SEVNT_RR (1 << 13)
|
||||
#define PSC_I2SEVNT_RO (1 << 12)
|
||||
#define PSC_I2SEVNT_RU (1 << 11)
|
||||
@ -305,8 +288,7 @@ typedef struct psc_i2s {
|
||||
#define PSC_I2SEVNT_RD (1 << 5)
|
||||
#define PSC_I2SEVNT_TD (1 << 4)
|
||||
|
||||
/* PSC in SPI Mode.
|
||||
*/
|
||||
/* PSC in SPI Mode. */
|
||||
typedef struct psc_spi {
|
||||
u32 psc_sel;
|
||||
u32 psc_ctrl;
|
||||
@ -318,8 +300,7 @@ typedef struct psc_spi {
|
||||
u32 psc_spitxrx;
|
||||
} psc_spi_t;
|
||||
|
||||
/* SPI Config Register.
|
||||
*/
|
||||
/* SPI Config Register. */
|
||||
#define PSC_SPICFG_RT_MASK (3 << 30)
|
||||
#define PSC_SPICFG_RT_FIFO1 (0 << 30)
|
||||
#define PSC_SPICFG_RT_FIFO2 (1 << 30)
|
||||
@ -355,8 +336,7 @@ typedef struct psc_spi {
|
||||
#define PSC_SPICFG_MLF (1 << 1)
|
||||
#define PSC_SPICFG_MO (1 << 0)
|
||||
|
||||
/* SPI Mask Register.
|
||||
*/
|
||||
/* SPI Mask Register. */
|
||||
#define PSC_SPIMSK_MM (1 << 16)
|
||||
#define PSC_SPIMSK_RR (1 << 13)
|
||||
#define PSC_SPIMSK_RO (1 << 12)
|
||||
@ -371,16 +351,14 @@ typedef struct psc_spi {
|
||||
PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
|
||||
PSC_SPIMSK_MD)
|
||||
|
||||
/* SPI Protocol Control Register.
|
||||
*/
|
||||
/* SPI Protocol Control Register. */
|
||||
#define PSC_SPIPCR_RC (1 << 6)
|
||||
#define PSC_SPIPCR_SP (1 << 5)
|
||||
#define PSC_SPIPCR_SS (1 << 4)
|
||||
#define PSC_SPIPCR_TC (1 << 2)
|
||||
#define PSC_SPIPCR_MS (1 << 0)
|
||||
|
||||
/* SPI Status register (read only).
|
||||
*/
|
||||
/* SPI Status register (read only). */
|
||||
#define PSC_SPISTAT_RF (1 << 13)
|
||||
#define PSC_SPISTAT_RE (1 << 12)
|
||||
#define PSC_SPISTAT_RR (1 << 11)
|
||||
@ -393,8 +371,7 @@ typedef struct psc_spi {
|
||||
#define PSC_SPISTAT_DR (1 << 1)
|
||||
#define PSC_SPISTAT_SR (1 << 0)
|
||||
|
||||
/* SPI Event Register.
|
||||
*/
|
||||
/* SPI Event Register. */
|
||||
#define PSC_SPIEVNT_MM (1 << 16)
|
||||
#define PSC_SPIEVNT_RR (1 << 13)
|
||||
#define PSC_SPIEVNT_RO (1 << 12)
|
||||
@ -405,13 +382,11 @@ typedef struct psc_spi {
|
||||
#define PSC_SPIEVNT_SD (1 << 5)
|
||||
#define PSC_SPIEVNT_MD (1 << 4)
|
||||
|
||||
/* Transmit register control.
|
||||
*/
|
||||
/* Transmit register control. */
|
||||
#define PSC_SPITXRX_LC (1 << 29)
|
||||
#define PSC_SPITXRX_SR (1 << 28)
|
||||
|
||||
/* PSC in SMBus (I2C) Mode.
|
||||
*/
|
||||
/* PSC in SMBus (I2C) Mode. */
|
||||
typedef struct psc_smb {
|
||||
u32 psc_sel;
|
||||
u32 psc_ctrl;
|
||||
@ -424,8 +399,7 @@ typedef struct psc_smb {
|
||||
u32 psc_smbtmr;
|
||||
} psc_smb_t;
|
||||
|
||||
/* SMBus Config Register.
|
||||
*/
|
||||
/* SMBus Config Register. */
|
||||
#define PSC_SMBCFG_RT_MASK (3 << 30)
|
||||
#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
|
||||
#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
|
||||
@ -452,8 +426,7 @@ typedef struct psc_smb {
|
||||
|
||||
#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
|
||||
|
||||
/* SMBus Mask Register.
|
||||
*/
|
||||
/* SMBus Mask Register. */
|
||||
#define PSC_SMBMSK_DN (1 << 30)
|
||||
#define PSC_SMBMSK_AN (1 << 29)
|
||||
#define PSC_SMBMSK_AL (1 << 28)
|
||||
@ -471,13 +444,11 @@ typedef struct psc_smb {
|
||||
PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
|
||||
PSC_SMBMSK_MD)
|
||||
|
||||
/* SMBus Protocol Control Register.
|
||||
*/
|
||||
/* SMBus Protocol Control Register. */
|
||||
#define PSC_SMBPCR_DC (1 << 2)
|
||||
#define PSC_SMBPCR_MS (1 << 0)
|
||||
|
||||
/* SMBus Status register (read only).
|
||||
*/
|
||||
/* SMBus Status register (read only). */
|
||||
#define PSC_SMBSTAT_BB (1 << 28)
|
||||
#define PSC_SMBSTAT_RF (1 << 13)
|
||||
#define PSC_SMBSTAT_RE (1 << 12)
|
||||
@ -491,8 +462,7 @@ typedef struct psc_smb {
|
||||
#define PSC_SMBSTAT_DR (1 << 1)
|
||||
#define PSC_SMBSTAT_SR (1 << 0)
|
||||
|
||||
/* SMBus Event Register.
|
||||
*/
|
||||
/* SMBus Event Register. */
|
||||
#define PSC_SMBEVNT_DN (1 << 30)
|
||||
#define PSC_SMBEVNT_AN (1 << 29)
|
||||
#define PSC_SMBEVNT_AL (1 << 28)
|
||||
@ -510,15 +480,13 @@ typedef struct psc_smb {
|
||||
PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
|
||||
PSC_SMBEVNT_MD)
|
||||
|
||||
/* Transmit register control.
|
||||
*/
|
||||
/* Transmit register control. */
|
||||
#define PSC_SMBTXRX_RSR (1 << 28)
|
||||
#define PSC_SMBTXRX_STP (1 << 29)
|
||||
#define PSC_SMBTXRX_DATAMASK (0xff)
|
||||
#define PSC_SMBTXRX_DATAMASK 0xff
|
||||
|
||||
/* SMBus protocol timers register.
|
||||
*/
|
||||
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)
|
||||
/* SMBus protocol timers register. */
|
||||
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
|
||||
#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
|
||||
#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
|
||||
#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
|
||||
@ -526,5 +494,4 @@ typedef struct psc_smb {
|
||||
#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
|
||||
#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
|
||||
|
||||
|
||||
#endif /* _AU1000_PSC_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user