mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 04:18:39 +08:00
Pin control bulk changes for the v5.18 kernel cycle
No core changes this time. Just new driver code and improvements!
New drivers:
- New driver for the Broadcom BCM4908 SoC.
- New subdriver for Tesla FSD (Full Self Driving) SoC, a
derivative of the Samsung Exynos pin control driver.
- New driver for the Amlogic Meson S4 SoC.
- New driver for the Sunplus SP7021 SoC.
- New driver for the Microsemi Ocelot family ServalT SoC.
- New subdriver for Intel Alder Lake-M SoC.
- New subdriver for Intel Ice Lake-N SoC, including PCH support.
- New subdriver for Renesas R8A779F0 SoC.
- New subdriver for Mediatek MT8186 SoC.
- New subdriver for NXP Freescale i.MX93 SoC.
- New driver for Nuvoton WPCM450 SoC.
- New driver for Qualcomm SC8280XP SoC.
Improvements:
- Wakeup support on Samsung Exynos850 and ExynosAutov9.
- Serious and voluminous maintenance cleanup and refactoring in
the Renesas drivers. Mainly sharing similar data between the
different SoC subdrivers.
- Qualcomm SM8450 EGPIO support.
- Drive strength support on the Mediatek MT8195.
- Add some missing groups and functions to the Ralink RT2880.
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Merge tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"No core changes this time. Just new driver code and improvements!
New drivers:
- New driver for the Broadcom BCM4908 SoC.
- New subdriver for Tesla FSD (Full Self Driving) SoC, a derivative
of the Samsung Exynos pin control driver.
- New driver for the Amlogic Meson S4 SoC.
- New driver for the Sunplus SP7021 SoC.
- New driver for the Microsemi Ocelot family ServalT SoC.
- New subdriver for Intel Alder Lake-M SoC.
- New subdriver for Intel Ice Lake-N SoC, including PCH support.
- New subdriver for Renesas R8A779F0 SoC.
- New subdriver for Mediatek MT8186 SoC.
- New subdriver for NXP Freescale i.MX93 SoC.
- New driver for Nuvoton WPCM450 SoC.
- New driver for Qualcomm SC8280XP SoC.
Improvements:
- Wakeup support on Samsung Exynos850 and ExynosAutov9.
- Serious and voluminous maintenance cleanup and refactoring in the
Renesas drivers. Mainly sharing similar data between the different
SoC subdrivers.
- Qualcomm SM8450 EGPIO support.
- Drive strength support on the Mediatek MT8195.
- Add some missing groups and functions to the Ralink RT2880"
* tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (188 commits)
pinctrl: mediatek: common-v1: fix semicolon.cocci warnings
pinctrl: nuvoton: wpcm450: Fix build error without OF
pinctrl: qcom-pmic-gpio: Add support for pm8450
dt-bindings: pinctrl: aspeed: Update gfx node in example
dt-bindings: pinctrl: rt2880: add missing pin groups and functions
pinctrl: ingenic: Fix regmap on X series SoCs
pinctrl: nuvoton: Fix return value check in wpcm450_gpio_register()
pinctrl: nuvoton: wpcm450: off by one in wpcm450_gpio_register()
pinctrl: nuvoton: wpcm450: select GENERIC_PINCTRL_GROUPS
pinctrl: nuvoton: Fix sparse warning
pinctrl: mediatek: mt8186: Account for probe refactoring
pinctrl: mediatek: common-v1: Commonize spec_ies_smt_set callback
pinctrl: mediatek: common-v1: Commonize spec_pupd callback
pinctrl: mediatek: common-v1: Use common probe function
pinctrl: mediatek: common-v1: Add common probe function
pinctrl: mediatek: paris: Unify probe function by using OF match data
pinctrl/rockchip: Add missing of_node_put() in rockchip_pinctrl_probe
pinctrl: nomadik: Add missing of_node_put() in nmk_pinctrl_probe
pinctrl: berlin: fix error return code of berlin_pinctrl_build_state()
pinctrl: qcom: Introduce sc8280xp TLMM driver
...
This commit is contained in:
Linus Torvalds
commit
ff61bc81b3
@ -75,6 +75,7 @@ additionalProperties: false
|
||||
|
||||
examples:
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- |
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#include <dt-bindings/clock/aspeed-clock.h>
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -84,6 +85,8 @@ examples:
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syscon: scu@1e6e2000 {
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compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
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reg = <0x1e6e2000 0x1a8>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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pinctrl: pinctrl {
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compatible = "aspeed,ast2500-pinctrl";
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@ -104,6 +107,12 @@ examples:
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gfx: display@1e6e6000 {
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compatible = "aspeed,ast2500-gfx", "syscon";
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reg = <0x1e6e6000 0x1000>;
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reg-io-width = <4>;
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clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
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resets = <&syscon ASPEED_RESET_CRT1>;
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interrupts = <0x19>;
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syscon = <&syscon>;
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memory-region = <&gfx_memory>;
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};
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};
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@ -130,3 +139,10 @@ examples:
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};
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};
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};
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gfx_memory: framebuffer {
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size = <0x01000000>;
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alignment = <0x01000000>;
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compatible = "shared-dma-pool";
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reusable;
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};
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@ -85,7 +85,7 @@ Optional Properties (for I2C pins):
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- function: String. Specifies the pin mux selection. Values
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must be one of: "alt1", "alt2", "alt3", "alt4"
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- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
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pull-up resisitors (1.2k, 1.8k, 2.7k) available
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pull-up resistors (1.2k, 1.8k, 2.7k) available
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in parallel for I2C pins, so the valid values
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are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
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- bias-disable: No arguments. Disable pin bias.
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@ -0,0 +1,72 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom BCM4908 pin controller
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maintainers:
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- Rafał Miłecki <rafal@milecki.pl>
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description:
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Binding for pin controller present on BCM4908 family SoCs.
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properties:
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compatible:
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const: brcm,bcm4908-pinctrl
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reg:
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maxItems: 1
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patternProperties:
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'-pins$':
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type: object
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$ref: pinmux-node.yaml#
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properties:
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function:
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enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
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led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
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led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
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led_25, led_26, led_27, led_28, led_29, led_30, led_31,
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hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
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usb1_pwr ]
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groups:
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minItems: 1
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maxItems: 2
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items:
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enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
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led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
|
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led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
|
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led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
|
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led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
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led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
|
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led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
|
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led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
|
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led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
|
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led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
|
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nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
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usb1_pwr_grp ]
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allOf:
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||||
- $ref: pinctrl.yaml#
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||||
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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pinctrl@ff800560 {
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compatible = "brcm,bcm4908-pinctrl";
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reg = <0xff800560 0x10>;
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led_0-a-pins {
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function = "led_0";
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groups = "led_0_grp_a";
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};
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};
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@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX93 IOMUX Controller
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maintainers:
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||||
- Peng Fan <peng.fan@nxp.com>
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description:
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||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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allOf:
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- $ref: "pinctrl.yaml#"
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properties:
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compatible:
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const: fsl,imx93-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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||||
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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||||
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
|
||||
"mux_reg" indicates the offset of mux register.
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- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
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- description: |
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||||
"input_reg" indicates the offset of select input register.
|
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- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
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- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
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||||
|
||||
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required:
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||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
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||||
- reg
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||||
|
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additionalProperties: false
|
||||
|
||||
examples:
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||||
# Pinmux controller node
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||||
- |
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||||
iomuxc: pinctrl@443c0000 {
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compatible = "fsl,imx93-iomuxc";
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reg = <0x30330000 0x10000>;
|
||||
|
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pinctrl_uart3: uart3grp {
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fsl,pins =
|
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<0x48 0x1f8 0x41c 0x1 0x0 0x49>,
|
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<0x4c 0x1fc 0x418 0x1 0x0 0x49>;
|
||||
};
|
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};
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||||
|
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...
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@ -16,6 +16,7 @@ Required properties for the root node:
|
||||
"amlogic,meson-g12a-periphs-pinctrl"
|
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"amlogic,meson-g12a-aobus-pinctrl"
|
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"amlogic,meson-a1-periphs-pinctrl"
|
||||
"amlogic,meson-s4-periphs-pinctrl"
|
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- reg: address and size of registers controlling irq functionality
|
||||
|
||||
=== GPIO sub-nodes ===
|
||||
|
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@ -145,7 +145,7 @@ examples:
|
||||
clocks = <&sys_clk>;
|
||||
pinctrl-0 = <&sgpio2_pins>;
|
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pinctrl-names = "default";
|
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reg = <0x1101059c 0x100>;
|
||||
reg = <0x1101059c 0x118>;
|
||||
microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
|
||||
bus-frequency = <25000000>;
|
||||
sgpio_in2: gpio@0 {
|
||||
|
||||
@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings
|
||||
Required properties:
|
||||
- compatible : Should be "mscc,ocelot-pinctrl",
|
||||
"mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
|
||||
"mscc,luton-pinctrl", "mscc,serval-pinctrl" or
|
||||
"microchip,lan966x-pinctrl"
|
||||
"mscc,luton-pinctrl", "mscc,serval-pinctrl",
|
||||
"microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
|
||||
- reg : Address and length of the register set for the device
|
||||
- gpio-controller : Indicates this device is a GPIO controller
|
||||
- #gpio-cells : Must be 2.
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Nuvoton WPCM450 pin control and GPIO
|
||||
|
||||
maintainers:
|
||||
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nuvoton,wpcm450-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
# There are three kinds of subnodes:
|
||||
# 1. a GPIO controller node for each GPIO bank
|
||||
# 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
|
||||
# 3. a pinconf node configures properties of a single pin
|
||||
|
||||
"^gpio@[0-7]$":
|
||||
type: object
|
||||
|
||||
description:
|
||||
Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
|
||||
GPIOs. Some GPIOs support interrupts.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
description:
|
||||
The interrupts associated with this GPIO bank
|
||||
|
||||
required:
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
|
||||
"^mux-":
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description:
|
||||
One or more groups of pins to mux to a certain function
|
||||
items:
|
||||
enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
|
||||
hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
|
||||
clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
|
||||
fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
|
||||
fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
|
||||
pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
|
||||
function:
|
||||
description:
|
||||
The function that a group of pins is muxed to
|
||||
enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
|
||||
hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
|
||||
dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
|
||||
gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
|
||||
fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
|
||||
pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
|
||||
hg2, hg3, hg4, hg5, hg6, hg7, gpio ]
|
||||
|
||||
dependencies:
|
||||
groups: [ function ]
|
||||
function: [ groups ]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
"^cfg-":
|
||||
$ref: pincfg-node.yaml#
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
A list of pins to configure in certain ways, such as enabling
|
||||
debouncing
|
||||
items:
|
||||
pattern: "^gpio1?[0-9]{1,2}$"
|
||||
|
||||
input-debounce: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
pinctrl: pinctrl@b8003000 {
|
||||
compatible = "nuvoton,wpcm450-pinctrl";
|
||||
reg = <0xb8003000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio0: gpio@0 {
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mux-rmii2 {
|
||||
groups = "rmii2";
|
||||
function = "rmii2";
|
||||
};
|
||||
|
||||
pinmux_uid: mux-uid {
|
||||
groups = "gspi", "sspi";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
pinctrl_uid: cfg-uid {
|
||||
pins = "gpio14";
|
||||
input-debounce = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
|
||||
|
||||
uid {
|
||||
label = "UID";
|
||||
linux,code = <102>;
|
||||
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
297
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
Normal file
297
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
Normal file
@ -0,0 +1,297 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek MT8186 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Sean Wang <sean.wang@mediatek.com>
|
||||
|
||||
description: |
|
||||
The Mediatek's Pin controller is used to control SoC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8186-pinctrl
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: |
|
||||
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
|
||||
the amount of cells must be specified as 2. See the below
|
||||
mentioned gpio binding representation for description of particular cells.
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
description: |
|
||||
Physical address base for gpio base registers. There are 8 different GPIO
|
||||
physical address base in mt8186.
|
||||
maxItems: 8
|
||||
|
||||
reg-names:
|
||||
description: |
|
||||
Gpio base register names.
|
||||
items:
|
||||
- const: iocfg0
|
||||
- const: iocfg_bm
|
||||
- const: iocfg_bl
|
||||
- const: iocfg_br
|
||||
- const: iocfg_lm
|
||||
- const: iocfg_rb
|
||||
- const: iocfg_tl
|
||||
- const: eint
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
description: The interrupt outputs to sysirq
|
||||
maxItems: 1
|
||||
|
||||
mediatek,rsel-resistance-in-si-unit:
|
||||
type: boolean
|
||||
description: |
|
||||
Identifying i2c pins pull up/down type which is RSEL. It can support
|
||||
RSEL define or si unit value(ohm) to set different resistance.
|
||||
|
||||
# PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'^pins':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and
|
||||
input schmitt.
|
||||
An example of using macro:
|
||||
pincontroller {
|
||||
/* GPIO0 set as multifunction GPIO0 */
|
||||
gpio-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
}
|
||||
};
|
||||
/* GPIO128 set as multifunction SDA0 */
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
|
||||
}
|
||||
};
|
||||
};
|
||||
$ref: "pinmux-node.yaml"
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are
|
||||
defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
|
||||
directly.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
mediatek,drive-strength-adv:
|
||||
description: |
|
||||
Describe the specific driving setup property.
|
||||
For I2C pins, the existing generic driving setup can only support
|
||||
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
|
||||
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
|
||||
driving setup, the existing generic setup will be disabled.
|
||||
The specific driving setup is controlled by E1E0EN.
|
||||
When E1=0/E0=0, the strength is 0.125mA.
|
||||
When E1=0/E0=1, the strength is 0.25mA.
|
||||
When E1=1/E0=0, the strength is 0.5mA.
|
||||
When E1=1/E0=1, the strength is 1mA.
|
||||
EN is used to enable or disable the specific driving setup.
|
||||
Valid arguments are described as below:
|
||||
0: (E1, E0, EN) = (0, 0, 0)
|
||||
1: (E1, E0, EN) = (0, 0, 1)
|
||||
2: (E1, E0, EN) = (0, 1, 0)
|
||||
3: (E1, E0, EN) = (0, 1, 1)
|
||||
4: (E1, E0, EN) = (1, 0, 0)
|
||||
5: (E1, E0, EN) = (1, 0, 1)
|
||||
6: (E1, E0, EN) = (1, 1, 0)
|
||||
7: (E1, E0, EN) = (1, 1, 1)
|
||||
So the valid arguments are from 0 to 7.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7]
|
||||
|
||||
bias-pull-down:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt8186 pull down PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203]
|
||||
description: mt8186 pull down RSEL type define value.
|
||||
- enum: [75000, 5000]
|
||||
description: mt8186 pull down RSEL type si unit value(ohm).
|
||||
description: |
|
||||
For pull down type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
|
||||
"MTK_PUPD_SET_R1R0_11" define in mt8186.
|
||||
For pull down type is RSEL, it can add RSEL define & resistance
|
||||
value(ohm) to set different resistance by identifying property
|
||||
"mediatek,rsel-resistance-in-si-unit".
|
||||
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
|
||||
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
|
||||
define in mt8186. It can also support resistance value(ohm)
|
||||
"75000" & "5000" in mt8186.
|
||||
An example of using RSEL define:
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
|
||||
bias-pull-down = <MTK_PULL_SET_RSEL_001>;
|
||||
}
|
||||
};
|
||||
};
|
||||
An example of using si unit resistance value(ohm):
|
||||
&pio {
|
||||
mediatek,rsel-resistance-in-si-unit;
|
||||
}
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
|
||||
bias-pull-down = <75000>;
|
||||
}
|
||||
};
|
||||
};
|
||||
|
||||
bias-pull-up:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt8186 pull up PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203]
|
||||
description: mt8186 pull up RSEL type define value.
|
||||
- enum: [1000, 5000, 10000, 75000]
|
||||
description: mt8186 pull up RSEL type si unit value(ohm).
|
||||
description: |
|
||||
For pull up type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
|
||||
"MTK_PUPD_SET_R1R0_11" define in mt8186.
|
||||
For pull up type is RSEL, it can add RSEL define & resistance
|
||||
value(ohm) to set different resistance by identifying property
|
||||
"mediatek,rsel-resistance-in-si-unit".
|
||||
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
|
||||
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
|
||||
define in mt8186. It can also support resistance value(ohm)
|
||||
"1000" & "5000" & "10000" & "75000" in mt8186.
|
||||
An example of using si unit resistance value(ohm):
|
||||
&pio {
|
||||
mediatek,rsel-resistance-in-si-unit;
|
||||
}
|
||||
pincontroller {
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
|
||||
bias-pull-up = <1000>;
|
||||
}
|
||||
};
|
||||
};
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/mt8186-pinfunc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt8186-pinctrl";
|
||||
reg = <0x10005000 0x1000>,
|
||||
<0x10002000 0x0200>,
|
||||
<0x10002200 0x0200>,
|
||||
<0x10002400 0x0200>,
|
||||
<0x10002600 0x0200>,
|
||||
<0x10002A00 0x0200>,
|
||||
<0x10002c00 0x0200>,
|
||||
<0x1000b000 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
|
||||
"iocfg_br", "iocfg_lm", "iocfg_rb",
|
||||
"iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 185>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
pio-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
spi0-pins {
|
||||
pins-spi {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
|
||||
<PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
|
||||
<PINMUX_GPIO2__FUNC_SPI0_MO_B>;
|
||||
bias-disable;
|
||||
};
|
||||
pins-spi-mi {
|
||||
pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
|
||||
<PINMUX_GPIO128__FUNC_SDA0>;
|
||||
bias-pull-up = <MTK_PULL_SET_RSEL_001>;
|
||||
mediatek,drive-strength-adv = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -98,7 +98,41 @@ patternProperties:
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
mediatek,drive-strength-adv:
|
||||
description: |
|
||||
Describe the specific driving setup property.
|
||||
For I2C pins, the existing generic driving setup can only support
|
||||
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
|
||||
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
|
||||
driving setup, the existing generic setup will be disabled.
|
||||
The specific driving setup is controlled by E1E0EN.
|
||||
When E1=0/E0=0, the strength is 0.125mA.
|
||||
When E1=0/E0=1, the strength is 0.25mA.
|
||||
When E1=1/E0=0, the strength is 0.5mA.
|
||||
When E1=1/E0=1, the strength is 1mA.
|
||||
EN is used to enable or disable the specific driving setup.
|
||||
Valid arguments are described as below:
|
||||
0: (E1, E0, EN) = (0, 0, 0)
|
||||
1: (E1, E0, EN) = (0, 0, 1)
|
||||
2: (E1, E0, EN) = (0, 1, 0)
|
||||
3: (E1, E0, EN) = (0, 1, 1)
|
||||
4: (E1, E0, EN) = (1, 0, 0)
|
||||
5: (E1, E0, EN) = (1, 0, 1)
|
||||
6: (E1, E0, EN) = (1, 1, 0)
|
||||
7: (E1, E0, EN) = (1, 1, 1)
|
||||
So the valid arguments are from 0 to 7.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7]
|
||||
|
||||
bias-pull-down:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt8195 pull down PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
description: mt8195 pull down RSEL type define value.
|
||||
- enum: [75000, 5000]
|
||||
description: mt8195 pull down RSEL type si unit value(ohm).
|
||||
description: |
|
||||
For pull down type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
@ -115,13 +149,6 @@ patternProperties:
|
||||
& "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
|
||||
define in mt8195. It can also support resistance value(ohm)
|
||||
"75000" & "5000" in mt8195.
|
||||
oneOf:
|
||||
- enum: [100, 101, 102, 103]
|
||||
- description: mt8195 pull down PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
- description: mt8195 pull down RSEL type define value.
|
||||
- enum: [75000, 5000]
|
||||
- description: mt8195 pull down RSEL type si unit value(ohm).
|
||||
|
||||
An example of using RSEL define:
|
||||
pincontroller {
|
||||
@ -146,6 +173,14 @@ patternProperties:
|
||||
};
|
||||
|
||||
bias-pull-up:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt8195 pull up PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
description: mt8195 pull up RSEL type define value.
|
||||
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
|
||||
description: mt8195 pull up RSEL type si unit value(ohm).
|
||||
description: |
|
||||
For pull up type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
@ -163,13 +198,6 @@ patternProperties:
|
||||
define in mt8195. It can also support resistance value(ohm)
|
||||
"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
|
||||
"75000" in mt8195.
|
||||
oneOf:
|
||||
- enum: [100, 101, 102, 103]
|
||||
- description: mt8195 pull up PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
- description: mt8195 pull up RSEL type define value.
|
||||
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
|
||||
- description: mt8195 pull up RSEL type si unit value(ohm).
|
||||
An example of using RSEL define:
|
||||
pincontroller {
|
||||
i2c0-pins {
|
||||
@ -268,4 +296,13 @@ examples:
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
|
||||
<PINMUX_GPIO9__FUNC_SCL0>;
|
||||
bias-disable;
|
||||
mediatek,drive-strength-adv = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -34,6 +34,8 @@ properties:
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
gpio-reserved-ranges: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
|
||||
@ -36,6 +36,7 @@ properties:
|
||||
- qcom,pm8350-gpio
|
||||
- qcom,pm8350b-gpio
|
||||
- qcom,pm8350c-gpio
|
||||
- qcom,pm8450-gpio
|
||||
- qcom,pm8916-gpio
|
||||
- qcom,pm8917-gpio
|
||||
- qcom,pm8921-gpio
|
||||
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
- qcom,pm8019-mpp
|
||||
- qcom,pm8038-mpp
|
||||
- qcom,pm8058-mpp
|
||||
- qcom,pm8226-mpp
|
||||
- qcom,pm8821-mpp
|
||||
- qcom,pm8841-mpp
|
||||
- qcom,pm8916-mpp
|
||||
|
||||
@ -0,0 +1,151 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SC8280XP TLMM block
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SC8280XP platform.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
|
||||
|
||||
'$defs':
|
||||
qcom-sc8280xp-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
|
||||
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
|
||||
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
|
||||
cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
|
||||
ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
|
||||
ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
|
||||
edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
|
||||
emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
|
||||
emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
|
||||
emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
|
||||
gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
|
||||
jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
|
||||
mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
|
||||
mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
|
||||
mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
|
||||
mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
|
||||
mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
|
||||
mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
|
||||
mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
|
||||
pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
|
||||
phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
|
||||
prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
|
||||
qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
|
||||
qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
|
||||
qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
|
||||
sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
|
||||
tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
|
||||
usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
|
||||
usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
|
||||
vsense_trigger ]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pinctrl@f100000 {
|
||||
compatible = "qcom,sc8280xp-tlmm";
|
||||
reg = <0x0f100000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 230>;
|
||||
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-subnodes-state {
|
||||
rx {
|
||||
pins = "gpio4";
|
||||
function = "qup14";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio5";
|
||||
function = "qup14";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -73,7 +73,6 @@ $defs:
|
||||
properties:
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description:
|
||||
The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins
|
||||
The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
|
||||
is not supported. There is no pinconf support.
|
||||
|
||||
properties:
|
||||
@ -29,12 +29,13 @@ patternProperties:
|
||||
properties:
|
||||
groups:
|
||||
description: Name of the pin group to use for the functions.
|
||||
enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
|
||||
pcie, sdhci]
|
||||
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
|
||||
uart1, uart2, uart3, wdt]
|
||||
function:
|
||||
description: The mux function to select
|
||||
enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
|
||||
mdio, nand1, nand2, sdhci]
|
||||
enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
|
||||
pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3,
|
||||
spi, uart1, uart2, uart3, wdt refclk, wdt rst]
|
||||
|
||||
required:
|
||||
- groups
|
||||
|
||||
@ -44,6 +44,7 @@ properties:
|
||||
- renesas,pfc-r8a77990 # R-Car E3
|
||||
- renesas,pfc-r8a77995 # R-Car D3
|
||||
- renesas,pfc-r8a779a0 # R-Car V3U
|
||||
- renesas,pfc-r8a779f0 # R-Car S4-8
|
||||
- renesas,pfc-sh73a0 # SH-Mobile AG5
|
||||
|
||||
reg:
|
||||
|
||||
@ -4,14 +4,14 @@
|
||||
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/G2L combined Pin and GPIO controller
|
||||
title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
|
||||
description:
|
||||
The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
|
||||
The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
|
||||
controller.
|
||||
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
|
||||
Each port features up to 8 pins, each of them configurable for GPIO function
|
||||
@ -20,8 +20,15 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g054-pinctrl # RZ/V2L
|
||||
- const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -76,6 +83,7 @@ additionalProperties:
|
||||
output-impedance-ohms:
|
||||
enum: [ 33, 50, 66, 100 ]
|
||||
power-source:
|
||||
description: I/O voltage in millivolt.
|
||||
enum: [ 1800, 2500, 3300 ]
|
||||
slew-rate: true
|
||||
gpio-hog: true
|
||||
|
||||
@ -56,6 +56,7 @@ properties:
|
||||
- samsung,exynos7885-pinctrl
|
||||
- samsung,exynos850-pinctrl
|
||||
- samsung,exynosautov9-pinctrl
|
||||
- tesla,fsd-pinctrl
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
|
||||
@ -0,0 +1,374 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) Sunplus Co., Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sunplus SP7021 Pin Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Dvorkin Dmitry <dvorkin@tibbo.com>
|
||||
- Wells Lu <wellslutw@gmail.com>
|
||||
|
||||
description: |
|
||||
The Sunplus SP7021 pin controller is used to control SoC pins. Please
|
||||
refer to pinctrl-bindings.txt in this directory for details of the common
|
||||
pinctrl bindings used by client devices.
|
||||
|
||||
SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
|
||||
are multiplexed with some special function pins. SP7021 has 3 types of
|
||||
special function pins:
|
||||
|
||||
(1) function-group pins:
|
||||
Ex 1 (SPI-NOR flash):
|
||||
If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87
|
||||
will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79
|
||||
and 81 will be pins of SPI-NOR flash.
|
||||
|
||||
Ex 2 (UART_0):
|
||||
If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and
|
||||
RX pins of UART_0 (UART channel 0).
|
||||
|
||||
Ex 3 (eMMC):
|
||||
If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77,
|
||||
78, 79, 80, 81 will be pins of an eMMC device.
|
||||
|
||||
Properties "function" and "groups" are used to select function-group
|
||||
pins.
|
||||
|
||||
(2) fully pin-mux (like phone exchange mux) pins:
|
||||
GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of
|
||||
SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.)
|
||||
can be routed to any pins of fully pin-mux pins.
|
||||
|
||||
Ex 1 (UART channel 1):
|
||||
If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be
|
||||
routed to GPIO 10 (3 - 1 + 8 = 10).
|
||||
If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be
|
||||
routed to GPIO 11 (4 - 1 + 8 = 11).
|
||||
If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will
|
||||
be routed to GPIO 12 (5 - 1 + 8 = 12).
|
||||
If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will
|
||||
be routed to GPIO 13 (6 - 1 + 8 = 13).
|
||||
|
||||
Ex 2 (I2C channel 0):
|
||||
If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will
|
||||
be routed to GPIO 27 (20 - 1 + 8 = 27).
|
||||
If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0
|
||||
will be routed to GPIO 28 (21 - 1 + 9 = 28).
|
||||
|
||||
Totally, SP7021 has 120 peripheral pins. The peripheral pins can be
|
||||
routed to any of 64 'fully pin-mux' pins.
|
||||
|
||||
(3) I/O processor pins
|
||||
SP7021 has a built-in I/O processor.
|
||||
Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor.
|
||||
|
||||
Vendor property "sunplus,pins" is used to select "fully pin-mux" pins,
|
||||
"I/O processor pins" and "digital GPIO" pins.
|
||||
|
||||
The device node of pin controller of Sunplus SP7021 has following
|
||||
properties.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sunplus,sp7021-pctl
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: the MOON2 registers
|
||||
- description: the GPIOXT registers
|
||||
- description: the FIRST registers
|
||||
- description: the MOON1 registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: moon2
|
||||
- const: gpioxt
|
||||
- const: first
|
||||
- const: moon1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pins or function-pins group available on the machine. Each subnode
|
||||
will list the pins it needs, and how they should be configured.
|
||||
|
||||
Pinctrl node's client devices use subnodes for desired pin
|
||||
configuration. Client device subnodes use below standard properties.
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
sunplus,pins:
|
||||
description: |
|
||||
Define 'sunplus,pins' which are used by pinctrl node's client
|
||||
device.
|
||||
|
||||
It consists of one or more integers which represents the config
|
||||
setting for corresponding pin. Each integer defines a individual
|
||||
pin in which:
|
||||
|
||||
Bit 32~24: defines GPIO number. Its range is 0 ~ 98.
|
||||
Bit 23~16: defines types: (1) fully pin-mux pins
|
||||
(2) IO processor pins
|
||||
(3) digital GPIO pins
|
||||
Bit 15~8: defines pins of peripherals (which are defined in
|
||||
'include/dt-binging/pinctrl/sppctl.h').
|
||||
Bit 7~0: defines types or initial-state of digital GPIO pins.
|
||||
|
||||
Please use macro SPPCTL_IOPAD to define the integers for pins.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
function:
|
||||
description: |
|
||||
Define pin-function which is used by pinctrl node's client device.
|
||||
The name should be one of string in the following enumeration.
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD,
|
||||
UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ]
|
||||
|
||||
groups:
|
||||
description: |
|
||||
Define pin-group in a specified pin-function.
|
||||
The name should be one of string in the following enumeration.
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2,
|
||||
SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1,
|
||||
HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ]
|
||||
|
||||
sunplus,zerofunc:
|
||||
description: |
|
||||
This is a vendor specific property. It is used to disable pins
|
||||
which are not used by pinctrl node's client device.
|
||||
Some pins may be enabled by boot-loader. We can use this
|
||||
property to disable them.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- SPI_FLASH
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- SPI_FLASH1
|
||||
- SPI_FLASH2
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- SPI_FLASH_4BIT
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- SPI_FLASH_4BIT1
|
||||
- SPI_FLASH_4BIT2
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- SPI_NAND
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- SPI_NAND
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- CARD0_EMMC
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- CARD0_EMMC
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- SD_CARD
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- SD_CARD
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- UA0
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- UA0
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- FPGA_IFX
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- FPGA_IFX
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- HDMI_TX
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- HDMI_TX1
|
||||
- HDMI_TX2
|
||||
- HDMI_TX3
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- LCDIF
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- LCDIF
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- USB0_OTG
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- USB0_OTG
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
enum:
|
||||
- USB1_OTG
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum:
|
||||
- USB1_OTG
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#gpio-cells"
|
||||
- gpio-controller
|
||||
- clocks
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/sppctl-sp7021.h>
|
||||
|
||||
pinctl@9c000100 {
|
||||
compatible = "sunplus,sp7021-pctl";
|
||||
reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
|
||||
<0x9c0032e4 0x1c>, <0x9c000080 0x20>;
|
||||
reg-names = "moon2", "gpioxt", "first", "moon1";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
clocks = <&clkc 0x83>;
|
||||
resets = <&rstc 0x73>;
|
||||
|
||||
uart0-pins {
|
||||
function = "UA0";
|
||||
groups = "UA0";
|
||||
};
|
||||
|
||||
spinand0-pins {
|
||||
function = "SPI_NAND";
|
||||
groups = "SPI_NAND";
|
||||
};
|
||||
|
||||
uart1-pins {
|
||||
sunplus,pins = <
|
||||
SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
|
||||
SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
|
||||
>;
|
||||
};
|
||||
|
||||
uart2-pins {
|
||||
sunplus,pins = <
|
||||
SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
|
||||
SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
|
||||
SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
|
||||
SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc-pins {
|
||||
function = "CARD0_EMMC";
|
||||
groups = "CARD0_EMMC";
|
||||
};
|
||||
|
||||
sdcard-pins {
|
||||
function = "SD_CARD";
|
||||
groups = "SD_CARD";
|
||||
sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
|
||||
};
|
||||
|
||||
hdmi_A_tx1-pins {
|
||||
function = "HDMI_TX";
|
||||
groups = "HDMI_TX1";
|
||||
};
|
||||
hdmi_A_tx2-pins {
|
||||
function = "HDMI_TX";
|
||||
groups = "HDMI_TX2";
|
||||
};
|
||||
hdmi_A_tx3-pins {
|
||||
function = "HDMI_TX";
|
||||
groups = "HDMI_TX3";
|
||||
};
|
||||
|
||||
ethernet-pins {
|
||||
sunplus,pins = <
|
||||
SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
|
||||
SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
|
||||
SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
|
||||
SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
|
||||
SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
|
||||
SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
|
||||
SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
|
||||
SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
|
||||
SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
|
||||
>;
|
||||
sunplus,zerofunc = <
|
||||
MUXF_L2SW_LED_FLASH0
|
||||
MUXF_L2SW_LED_ON0
|
||||
MUXF_L2SW_P0_MAC_RMII_RXER
|
||||
>;
|
||||
};
|
||||
};
|
||||
...
|
||||
19
MAINTAINERS
19
MAINTAINERS
@ -2383,6 +2383,7 @@ W: https://github.com/neuschaefer/wpcm450/wiki
|
||||
F: Documentation/devicetree/bindings/*/*wpcm*
|
||||
F: arch/arm/boot/dts/nuvoton-wpcm450*
|
||||
F: arch/arm/mach-npcm/wpcm450.c
|
||||
F: drivers/*/*/*wpcm*
|
||||
F: drivers/*/*wpcm*
|
||||
|
||||
ARM/NXP S32G ARCHITECTURE
|
||||
@ -3716,6 +3717,14 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
|
||||
F: drivers/net/ethernet/broadcom/bcm4908_enet.*
|
||||
F: drivers/net/ethernet/broadcom/unimac.h
|
||||
|
||||
BROADCOM BCM4908 PINMUX DRIVER
|
||||
M: Rafał Miłecki <rafal@milecki.pl>
|
||||
M: bcm-kernel-feedback-list@broadcom.com
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
|
||||
F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
|
||||
|
||||
BROADCOM BCM5301X ARM ARCHITECTURE
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
M: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
@ -15478,6 +15487,16 @@ M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
|
||||
S: Supported
|
||||
F: drivers/pinctrl/pinctrl-thunderbay.c
|
||||
|
||||
PIN CONTROLLER - SUNPLUS / TIBBO
|
||||
M: Dvorkin Dmitry <dvorkin@tibbo.com>
|
||||
M: Wells Lu <wellslutw@gmail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
W: https://sunplus.atlassian.net/wiki/spaces/doc/overview
|
||||
F: Documentation/devicetree/bindings/pinctrl/sunplus,*
|
||||
F: drivers/pinctrl/sunplus/
|
||||
F: include/dt-bindings/pinctrl/sppctl*.h
|
||||
|
||||
PKTCDVD DRIVER
|
||||
M: linux-block@vger.kernel.org
|
||||
S: Orphan
|
||||
|
||||
@ -527,6 +527,7 @@ source "drivers/pinctrl/samsung/Kconfig"
|
||||
source "drivers/pinctrl/spear/Kconfig"
|
||||
source "drivers/pinctrl/sprd/Kconfig"
|
||||
source "drivers/pinctrl/stm32/Kconfig"
|
||||
source "drivers/pinctrl/sunplus/Kconfig"
|
||||
source "drivers/pinctrl/sunxi/Kconfig"
|
||||
source "drivers/pinctrl/tegra/Kconfig"
|
||||
source "drivers/pinctrl/ti/Kconfig"
|
||||
|
||||
@ -62,7 +62,7 @@ obj-y += mediatek/
|
||||
obj-$(CONFIG_PINCTRL_MESON) += meson/
|
||||
obj-y += mvebu/
|
||||
obj-y += nomadik/
|
||||
obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
|
||||
obj-y += nuvoton/
|
||||
obj-$(CONFIG_PINCTRL_PXA) += pxa/
|
||||
obj-$(CONFIG_ARCH_QCOM) += qcom/
|
||||
obj-$(CONFIG_PINCTRL_RALINK) += ralink/
|
||||
@ -71,6 +71,7 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
|
||||
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
|
||||
obj-y += sprd/
|
||||
obj-$(CONFIG_PINCTRL_STM32) += stm32/
|
||||
obj-y += sunplus/
|
||||
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-y += ti/
|
||||
|
||||
@ -29,6 +29,20 @@ config PINCTRL_BCM2835
|
||||
help
|
||||
Say Y here to enable the Broadcom BCM2835 GPIO driver.
|
||||
|
||||
config PINCTRL_BCM4908
|
||||
tristate "Broadcom BCM4908 pinmux driver"
|
||||
depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
default ARCH_BCM4908
|
||||
help
|
||||
Driver for BCM4908 family SoCs with integrated pin controller.
|
||||
|
||||
If compiled as module it will be called pinctrl-bcm4908.
|
||||
|
||||
config PINCTRL_BCM63XX
|
||||
bool
|
||||
select PINMUX
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
|
||||
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
|
||||
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
|
||||
obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
|
||||
obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
|
||||
obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
|
||||
obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
|
||||
|
||||
563
drivers/pinctrl/bcm/pinctrl-bcm4908.c
Normal file
563
drivers/pinctrl/bcm/pinctrl-bcm4908.c
Normal file
@ -0,0 +1,563 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string_helpers.h>
|
||||
|
||||
#include "../core.h"
|
||||
#include "../pinmux.h"
|
||||
|
||||
#define BCM4908_NUM_PINS 86
|
||||
|
||||
#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
|
||||
#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
|
||||
#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
|
||||
#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
|
||||
#define BCM4908_TEST_PORT_COMMAND 0x0c
|
||||
#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
|
||||
|
||||
struct bcm4908_pinctrl {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct mutex mutex;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_desc pctldesc;
|
||||
};
|
||||
|
||||
/*
|
||||
* Groups
|
||||
*/
|
||||
|
||||
struct bcm4908_pinctrl_pin_setup {
|
||||
unsigned int number;
|
||||
unsigned int function;
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
|
||||
{ 0, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
|
||||
{ 1, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
|
||||
{ 2, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
|
||||
{ 3, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
|
||||
{ 4, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
|
||||
{ 5, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
|
||||
{ 6, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
|
||||
{ 7, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
|
||||
{ 8, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
|
||||
{ 9, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
|
||||
{ 10, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
|
||||
{ 11, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
|
||||
{ 12, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
|
||||
{ 13, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
|
||||
{ 14, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
|
||||
{ 15, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
|
||||
{ 16, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
|
||||
{ 17, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
|
||||
{ 18, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
|
||||
{ 19, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
|
||||
{ 20, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
|
||||
{ 21, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
|
||||
{ 22, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
|
||||
{ 23, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
|
||||
{ 24, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
|
||||
{ 25, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
|
||||
{ 26, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
|
||||
{ 27, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
|
||||
{ 28, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
|
||||
{ 29, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
|
||||
{ 30, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
|
||||
{ 31, 3 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
|
||||
{ 8, 2 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
|
||||
{ 9, 2 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
|
||||
{ 0, 2 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
|
||||
{ 1, 2 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
|
||||
{ 30, 2 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
|
||||
{ 10, 0 }, /* CTS */
|
||||
{ 11, 0 }, /* RTS */
|
||||
{ 12, 0 }, /* RXD */
|
||||
{ 13, 0 }, /* TXD */
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
|
||||
{ 18, 0 }, /* SDA */
|
||||
{ 19, 0 }, /* SCL */
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
|
||||
{ 22, 0 }, /* SDA */
|
||||
{ 23, 0 }, /* SCL */
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
|
||||
{ 27, 0 }, /* MCLK */
|
||||
{ 28, 0 }, /* LRCK */
|
||||
{ 29, 0 }, /* SDATA */
|
||||
{ 30, 0 }, /* SCLK */
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
|
||||
{ 32, 0 },
|
||||
{ 33, 0 },
|
||||
{ 34, 0 },
|
||||
{ 43, 0 },
|
||||
{ 44, 0 },
|
||||
{ 45, 0 },
|
||||
{ 56, 1 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
|
||||
{ 35, 0 },
|
||||
{ 36, 0 },
|
||||
{ 37, 0 },
|
||||
{ 38, 0 },
|
||||
{ 39, 0 },
|
||||
{ 40, 0 },
|
||||
{ 41, 0 },
|
||||
{ 42, 0 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
|
||||
{ 46, 0 },
|
||||
{ 47, 0 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
|
||||
{ 63, 0 },
|
||||
{ 64, 0 },
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
|
||||
{ 66, 0 },
|
||||
{ 67, 0 },
|
||||
};
|
||||
|
||||
struct bcm4908_pinctrl_grp {
|
||||
const char *name;
|
||||
const struct bcm4908_pinctrl_pin_setup *pins;
|
||||
const unsigned int num_pins;
|
||||
};
|
||||
|
||||
static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
|
||||
{ "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
|
||||
{ "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
|
||||
{ "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
|
||||
{ "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
|
||||
{ "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
|
||||
{ "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
|
||||
{ "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
|
||||
{ "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
|
||||
{ "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
|
||||
{ "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
|
||||
{ "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
|
||||
{ "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
|
||||
{ "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
|
||||
{ "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
|
||||
{ "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
|
||||
{ "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
|
||||
{ "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
|
||||
{ "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
|
||||
{ "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
|
||||
{ "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
|
||||
{ "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
|
||||
{ "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
|
||||
{ "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
|
||||
{ "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
|
||||
{ "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
|
||||
{ "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
|
||||
{ "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
|
||||
{ "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
|
||||
{ "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
|
||||
{ "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
|
||||
{ "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
|
||||
{ "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
|
||||
{ "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
|
||||
{ "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
|
||||
{ "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
|
||||
{ "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
|
||||
{ "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
|
||||
{ "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
|
||||
{ "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
|
||||
{ "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
|
||||
{ "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
|
||||
{ "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
|
||||
{ "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
|
||||
{ "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
|
||||
{ "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
|
||||
{ "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
|
||||
struct bcm4908_pinctrl_function {
|
||||
const char *name;
|
||||
const char * const *groups;
|
||||
const unsigned int num_groups;
|
||||
};
|
||||
|
||||
static const char * const led_0_groups[] = { "led_0_grp_a" };
|
||||
static const char * const led_1_groups[] = { "led_1_grp_a" };
|
||||
static const char * const led_2_groups[] = { "led_2_grp_a" };
|
||||
static const char * const led_3_groups[] = { "led_3_grp_a" };
|
||||
static const char * const led_4_groups[] = { "led_4_grp_a" };
|
||||
static const char * const led_5_groups[] = { "led_5_grp_a" };
|
||||
static const char * const led_6_groups[] = { "led_6_grp_a" };
|
||||
static const char * const led_7_groups[] = { "led_7_grp_a" };
|
||||
static const char * const led_8_groups[] = { "led_8_grp_a" };
|
||||
static const char * const led_9_groups[] = { "led_9_grp_a" };
|
||||
static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
|
||||
static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
|
||||
static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
|
||||
static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
|
||||
static const char * const led_14_groups[] = { "led_14_grp_a" };
|
||||
static const char * const led_15_groups[] = { "led_15_grp_a" };
|
||||
static const char * const led_16_groups[] = { "led_16_grp_a" };
|
||||
static const char * const led_17_groups[] = { "led_17_grp_a" };
|
||||
static const char * const led_18_groups[] = { "led_18_grp_a" };
|
||||
static const char * const led_19_groups[] = { "led_19_grp_a" };
|
||||
static const char * const led_20_groups[] = { "led_20_grp_a" };
|
||||
static const char * const led_21_groups[] = { "led_21_grp_a" };
|
||||
static const char * const led_22_groups[] = { "led_22_grp_a" };
|
||||
static const char * const led_23_groups[] = { "led_23_grp_a" };
|
||||
static const char * const led_24_groups[] = { "led_24_grp_a" };
|
||||
static const char * const led_25_groups[] = { "led_25_grp_a" };
|
||||
static const char * const led_26_groups[] = { "led_26_grp_a" };
|
||||
static const char * const led_27_groups[] = { "led_27_grp_a" };
|
||||
static const char * const led_28_groups[] = { "led_28_grp_a" };
|
||||
static const char * const led_29_groups[] = { "led_29_grp_a" };
|
||||
static const char * const led_30_groups[] = { "led_30_grp_a" };
|
||||
static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
|
||||
static const char * const hs_uart_groups[] = { "hs_uart_grp" };
|
||||
static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
|
||||
static const char * const i2s_groups[] = { "i2s_grp" };
|
||||
static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" };
|
||||
static const char * const nand_data_groups[] = { "nand_data_grp" };
|
||||
static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
|
||||
static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" };
|
||||
static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" };
|
||||
|
||||
static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
|
||||
{ "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
|
||||
{ "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
|
||||
{ "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
|
||||
{ "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
|
||||
{ "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
|
||||
{ "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
|
||||
{ "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
|
||||
{ "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
|
||||
{ "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
|
||||
{ "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
|
||||
{ "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
|
||||
{ "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
|
||||
{ "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
|
||||
{ "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
|
||||
{ "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
|
||||
{ "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
|
||||
{ "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
|
||||
{ "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
|
||||
{ "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
|
||||
{ "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
|
||||
{ "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
|
||||
{ "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
|
||||
{ "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
|
||||
{ "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
|
||||
{ "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
|
||||
{ "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
|
||||
{ "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
|
||||
{ "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
|
||||
{ "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
|
||||
{ "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
|
||||
{ "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
|
||||
{ "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
|
||||
{ "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
|
||||
{ "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
|
||||
{ "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
|
||||
{ "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
|
||||
{ "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
|
||||
{ "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
|
||||
{ "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
|
||||
{ "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
|
||||
};
|
||||
|
||||
/*
|
||||
* Groups code
|
||||
*/
|
||||
|
||||
static const struct pinctrl_ops bcm4908_pinctrl_ops = {
|
||||
.get_groups_count = pinctrl_generic_get_group_count,
|
||||
.get_group_name = pinctrl_generic_get_group_name,
|
||||
.get_group_pins = pinctrl_generic_get_group_pins,
|
||||
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
|
||||
.dt_free_map = pinconf_generic_dt_free_map,
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions code
|
||||
*/
|
||||
|
||||
static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
|
||||
unsigned int func_selector,
|
||||
unsigned int group_selector)
|
||||
{
|
||||
struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
const struct bcm4908_pinctrl_grp *group;
|
||||
struct group_desc *group_desc;
|
||||
int i;
|
||||
|
||||
group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
|
||||
if (!group_desc)
|
||||
return -EINVAL;
|
||||
group = group_desc->data;
|
||||
|
||||
mutex_lock(&bcm4908_pinctrl->mutex);
|
||||
for (i = 0; i < group->num_pins; i++) {
|
||||
u32 lsb = 0;
|
||||
|
||||
lsb |= group->pins[i].number;
|
||||
lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
|
||||
|
||||
writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
|
||||
writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
|
||||
writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
|
||||
bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
|
||||
}
|
||||
mutex_unlock(&bcm4908_pinctrl->mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
|
||||
.get_functions_count = pinmux_generic_get_function_count,
|
||||
.get_function_name = pinmux_generic_get_function_name,
|
||||
.get_function_groups = pinmux_generic_get_function_groups,
|
||||
.set_mux = bcm4908_pinctrl_set_mux,
|
||||
};
|
||||
|
||||
/*
|
||||
* Controller code
|
||||
*/
|
||||
|
||||
static struct pinctrl_desc bcm4908_pinctrl_desc = {
|
||||
.name = "bcm4908-pinctrl",
|
||||
.pctlops = &bcm4908_pinctrl_ops,
|
||||
.pmxops = &bcm4908_pinctrl_pmxops,
|
||||
};
|
||||
|
||||
static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
|
||||
{ .compatible = "brcm,bcm4908-pinctrl", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int bcm4908_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct bcm4908_pinctrl *bcm4908_pinctrl;
|
||||
struct pinctrl_desc *pctldesc;
|
||||
struct pinctrl_pin_desc *pins;
|
||||
char **pin_names;
|
||||
int i;
|
||||
|
||||
bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
|
||||
if (!bcm4908_pinctrl)
|
||||
return -ENOMEM;
|
||||
pctldesc = &bcm4908_pinctrl->pctldesc;
|
||||
platform_set_drvdata(pdev, bcm4908_pinctrl);
|
||||
|
||||
/* Set basic properties */
|
||||
|
||||
bcm4908_pinctrl->dev = dev;
|
||||
|
||||
bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(bcm4908_pinctrl->base))
|
||||
return PTR_ERR(bcm4908_pinctrl->base);
|
||||
|
||||
mutex_init(&bcm4908_pinctrl->mutex);
|
||||
|
||||
memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
|
||||
|
||||
/* Set pinctrl properties */
|
||||
|
||||
pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS);
|
||||
if (IS_ERR(pin_names))
|
||||
return PTR_ERR(pin_names);
|
||||
|
||||
pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins)
|
||||
return -ENOMEM;
|
||||
for (i = 0; i < BCM4908_NUM_PINS; i++) {
|
||||
pins[i].number = i;
|
||||
pins[i].name = pin_names[i];
|
||||
}
|
||||
pctldesc->pins = pins;
|
||||
pctldesc->npins = BCM4908_NUM_PINS;
|
||||
|
||||
/* Register */
|
||||
|
||||
bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
|
||||
if (IS_ERR(bcm4908_pinctrl->pctldev))
|
||||
return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
|
||||
"Failed to register pinctrl\n");
|
||||
|
||||
/* Groups */
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
|
||||
const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
|
||||
int *pins;
|
||||
int j;
|
||||
|
||||
pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins)
|
||||
return -ENOMEM;
|
||||
for (j = 0; j < group->num_pins; j++)
|
||||
pins[j] = group->pins[j].number;
|
||||
|
||||
pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
|
||||
pins, group->num_pins, (void *)group);
|
||||
}
|
||||
|
||||
/* Functions */
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
|
||||
const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
|
||||
|
||||
pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
|
||||
function->name,
|
||||
function->groups,
|
||||
function->num_groups, NULL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver bcm4908_pinctrl_driver = {
|
||||
.probe = bcm4908_pinctrl_probe,
|
||||
.driver = {
|
||||
.name = "bcm4908-pinctrl",
|
||||
.of_match_table = bcm4908_pinctrl_of_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(bcm4908_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Rafał Miłecki");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
|
||||
@ -233,6 +233,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
|
||||
pctrl->functions = krealloc(pctrl->functions,
|
||||
pctrl->nfunctions * sizeof(*pctrl->functions),
|
||||
GFP_KERNEL);
|
||||
if (!pctrl->functions)
|
||||
return -ENOMEM;
|
||||
|
||||
/* map functions to theirs groups */
|
||||
for (i = 0; i < pctrl->desc->ngroups; i++) {
|
||||
|
||||
@ -180,6 +180,13 @@ config PINCTRL_IMXRT1050
|
||||
help
|
||||
Say Y here to enable the imxrt1050 pinctrl driver
|
||||
|
||||
config PINCTRL_IMX93
|
||||
tristate "IMX93 pinctrl driver"
|
||||
depends on ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx93 pinctrl driver
|
||||
|
||||
config PINCTRL_VF610
|
||||
bool "Freescale Vybrid VF610 pinctrl driver"
|
||||
depends on SOC_VF610
|
||||
|
||||
@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
|
||||
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
|
||||
obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
|
||||
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
|
||||
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
||||
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
|
||||
|
||||
@ -661,7 +661,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
|
||||
func->name = np->name;
|
||||
func->num_group_names = of_get_child_count(np);
|
||||
if (func->num_group_names == 0) {
|
||||
dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
|
||||
dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
272
drivers/pinctrl/freescale/pinctrl-imx93.c
Normal file
272
drivers/pinctrl/freescale/pinctrl-imx93.c
Normal file
@ -0,0 +1,272 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx93_pads {
|
||||
IMX93_IOMUXC_DAP_TDI = 0,
|
||||
IMX93_IOMUXC_DAP_TMS_SWDIO = 1,
|
||||
IMX93_IOMUXC_DAP_TCLK_SWCLK = 2,
|
||||
IMX93_IOMUXC_DAP_TDO_TRACESWO = 3,
|
||||
IMX93_IOMUXC_GPIO_IO00 = 4,
|
||||
IMX93_IOMUXC_GPIO_IO01 = 5,
|
||||
IMX93_IOMUXC_GPIO_IO02 = 6,
|
||||
IMX93_IOMUXC_GPIO_IO03 = 7,
|
||||
IMX93_IOMUXC_GPIO_IO04 = 8,
|
||||
IMX93_IOMUXC_GPIO_IO05 = 9,
|
||||
IMX93_IOMUXC_GPIO_IO06 = 10,
|
||||
IMX93_IOMUXC_GPIO_IO07 = 11,
|
||||
IMX93_IOMUXC_GPIO_IO08 = 12,
|
||||
IMX93_IOMUXC_GPIO_IO09 = 13,
|
||||
IMX93_IOMUXC_GPIO_IO10 = 14,
|
||||
IMX93_IOMUXC_GPIO_IO11 = 15,
|
||||
IMX93_IOMUXC_GPIO_IO12 = 16,
|
||||
IMX93_IOMUXC_GPIO_IO13 = 17,
|
||||
IMX93_IOMUXC_GPIO_IO14 = 18,
|
||||
IMX93_IOMUXC_GPIO_IO15 = 19,
|
||||
IMX93_IOMUXC_GPIO_IO16 = 20,
|
||||
IMX93_IOMUXC_GPIO_IO17 = 21,
|
||||
IMX93_IOMUXC_GPIO_IO18 = 22,
|
||||
IMX93_IOMUXC_GPIO_IO19 = 23,
|
||||
IMX93_IOMUXC_GPIO_IO20 = 24,
|
||||
IMX93_IOMUXC_GPIO_IO21 = 25,
|
||||
IMX93_IOMUXC_GPIO_IO22 = 26,
|
||||
IMX93_IOMUXC_GPIO_IO23 = 27,
|
||||
IMX93_IOMUXC_GPIO_IO24 = 28,
|
||||
IMX93_IOMUXC_GPIO_IO25 = 29,
|
||||
IMX93_IOMUXC_GPIO_IO26 = 30,
|
||||
IMX93_IOMUXC_GPIO_IO27 = 31,
|
||||
IMX93_IOMUXC_GPIO_IO28 = 32,
|
||||
IMX93_IOMUXC_GPIO_IO29 = 33,
|
||||
IMX93_IOMUXC_CCM_CLKO1 = 34,
|
||||
IMX93_IOMUXC_CCM_CLKO2 = 35,
|
||||
IMX93_IOMUXC_CCM_CLKO3 = 36,
|
||||
IMX93_IOMUXC_CCM_CLKO4 = 37,
|
||||
IMX93_IOMUXC_ENET1_MDC = 38,
|
||||
IMX93_IOMUXC_ENET1_MDIO = 39,
|
||||
IMX93_IOMUXC_ENET1_TD3 = 40,
|
||||
IMX93_IOMUXC_ENET1_TD2 = 41,
|
||||
IMX93_IOMUXC_ENET1_TD1 = 42,
|
||||
IMX93_IOMUXC_ENET1_TD0 = 43,
|
||||
IMX93_IOMUXC_ENET1_TX_CTL = 44,
|
||||
IMX93_IOMUXC_ENET1_TXC = 45,
|
||||
IMX93_IOMUXC_ENET1_RX_CTL = 46,
|
||||
IMX93_IOMUXC_ENET1_RXC = 47,
|
||||
IMX93_IOMUXC_ENET1_RD0 = 48,
|
||||
IMX93_IOMUXC_ENET1_RD1 = 49,
|
||||
IMX93_IOMUXC_ENET1_RD2 = 50,
|
||||
IMX93_IOMUXC_ENET1_RD3 = 51,
|
||||
IMX93_IOMUXC_ENET2_MDC = 52,
|
||||
IMX93_IOMUXC_ENET2_MDIO = 53,
|
||||
IMX93_IOMUXC_ENET2_TD3 = 54,
|
||||
IMX93_IOMUXC_ENET2_TD2 = 55,
|
||||
IMX93_IOMUXC_ENET2_TD1 = 56,
|
||||
IMX93_IOMUXC_ENET2_TD0 = 57,
|
||||
IMX93_IOMUXC_ENET2_TX_CTL = 58,
|
||||
IMX93_IOMUXC_ENET2_TXC = 59,
|
||||
IMX93_IOMUXC_ENET2_RX_CTL = 60,
|
||||
IMX93_IOMUXC_ENET2_RXC = 61,
|
||||
IMX93_IOMUXC_ENET2_RD0 = 62,
|
||||
IMX93_IOMUXC_ENET2_RD1 = 63,
|
||||
IMX93_IOMUXC_ENET2_RD2 = 64,
|
||||
IMX93_IOMUXC_ENET2_RD3 = 65,
|
||||
IMX93_IOMUXC_SD1_CLK = 66,
|
||||
IMX93_IOMUXC_SD1_CMD = 67,
|
||||
IMX93_IOMUXC_SD1_DATA0 = 68,
|
||||
IMX93_IOMUXC_SD1_DATA1 = 69,
|
||||
IMX93_IOMUXC_SD1_DATA2 = 70,
|
||||
IMX93_IOMUXC_SD1_DATA3 = 71,
|
||||
IMX93_IOMUXC_SD1_DATA4 = 72,
|
||||
IMX93_IOMUXC_SD1_DATA5 = 73,
|
||||
IMX93_IOMUXC_SD1_DATA6 = 74,
|
||||
IMX93_IOMUXC_SD1_DATA7 = 75,
|
||||
IMX93_IOMUXC_SD1_STROBE = 76,
|
||||
IMX93_IOMUXC_SD2_VSELECT = 77,
|
||||
IMX93_IOMUXC_SD3_CLK = 78,
|
||||
IMX93_IOMUXC_SD3_CMD = 79,
|
||||
IMX93_IOMUXC_SD3_DATA0 = 80,
|
||||
IMX93_IOMUXC_SD3_DATA1 = 81,
|
||||
IMX93_IOMUXC_SD3_DATA2 = 82,
|
||||
IMX93_IOMUXC_SD3_DATA3 = 83,
|
||||
IMX93_IOMUXC_SD2_CD_B = 84,
|
||||
IMX93_IOMUXC_SD2_CLK = 85,
|
||||
IMX93_IOMUXC_SD2_CMD = 86,
|
||||
IMX93_IOMUXC_SD2_DATA0 = 87,
|
||||
IMX93_IOMUXC_SD2_DATA1 = 88,
|
||||
IMX93_IOMUXC_SD2_DATA2 = 89,
|
||||
IMX93_IOMUXC_SD2_DATA3 = 90,
|
||||
IMX93_IOMUXC_SD2_RESET_B = 91,
|
||||
IMX93_IOMUXC_I2C1_SCL = 92,
|
||||
IMX93_IOMUXC_I2C1_SDA = 93,
|
||||
IMX93_IOMUXC_I2C2_SCL = 94,
|
||||
IMX93_IOMUXC_I2C2_SDA = 95,
|
||||
IMX93_IOMUXC_UART1_RXD = 96,
|
||||
IMX93_IOMUXC_UART1_TXD = 97,
|
||||
IMX93_IOMUXC_UART2_RXD = 98,
|
||||
IMX93_IOMUXC_UART2_TXD = 99,
|
||||
IMX93_IOMUXC_PDM_CLK = 100,
|
||||
IMX93_IOMUXC_PDM_BIT_STREAM0 = 101,
|
||||
IMX93_IOMUXC_PDM_BIT_STREAM1 = 102,
|
||||
IMX93_IOMUXC_SAI1_TXFS = 103,
|
||||
IMX93_IOMUXC_SAI1_TXC = 104,
|
||||
IMX93_IOMUXC_SAI1_TXD0 = 105,
|
||||
IMX93_IOMUXC_SAI1_RXD0 = 106,
|
||||
IMX93_IOMUXC_WDOG_ANY = 107,
|
||||
};
|
||||
|
||||
/* Pad names for the pinmux subsystem */
|
||||
static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0),
|
||||
IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY),
|
||||
};
|
||||
|
||||
static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {
|
||||
.pins = imx93_pinctrl_pads,
|
||||
.npins = ARRAY_SIZE(imx93_pinctrl_pads),
|
||||
.gpr_compatible = "fsl,imx93-iomuxc-gpr",
|
||||
};
|
||||
|
||||
static const struct of_device_id imx93_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imx93-iomuxc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int imx93_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imx93_pinctrl_info);
|
||||
}
|
||||
|
||||
static struct platform_driver imx93_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx93-pinctrl",
|
||||
.of_match_table = imx93_pinctrl_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = imx93_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init imx93_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx93_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx93_pinctrl_init);
|
||||
|
||||
MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Intel Alder Lake PCH pinctrl/GPIO driver
|
||||
*
|
||||
* Copyright (C) 2020, Intel Corporation
|
||||
* Copyright (C) 2020, 2022 Intel Corporation
|
||||
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
*/
|
||||
|
||||
@ -42,6 +42,319 @@
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
/* Alder Lake-N */
|
||||
static const struct pinctrl_pin_desc adln_pins[] = {
|
||||
/* GPP_B */
|
||||
PINCTRL_PIN(0, "CORE_VID_0"),
|
||||
PINCTRL_PIN(1, "CORE_VID_1"),
|
||||
PINCTRL_PIN(2, "GPPC_B_2"),
|
||||
PINCTRL_PIN(3, "GPPC_B_3"),
|
||||
PINCTRL_PIN(4, "GPPC_B_4"),
|
||||
PINCTRL_PIN(5, "GPPC_B_5"),
|
||||
PINCTRL_PIN(6, "GPPC_B_6"),
|
||||
PINCTRL_PIN(7, "GPPC_B_7"),
|
||||
PINCTRL_PIN(8, "GPPC_B_8"),
|
||||
PINCTRL_PIN(9, "GPPC_B_9"),
|
||||
PINCTRL_PIN(10, "GPPC_B_10"),
|
||||
PINCTRL_PIN(11, "GPPC_B_11"),
|
||||
PINCTRL_PIN(12, "SLP_S0B"),
|
||||
PINCTRL_PIN(13, "PLTRSTB"),
|
||||
PINCTRL_PIN(14, "GPPC_B_14"),
|
||||
PINCTRL_PIN(15, "GPPC_B_15"),
|
||||
PINCTRL_PIN(16, "GPPC_B_16"),
|
||||
PINCTRL_PIN(17, "GPPC_B_17"),
|
||||
PINCTRL_PIN(18, "GPPC_B_18"),
|
||||
PINCTRL_PIN(19, "GPPC_B_19"),
|
||||
PINCTRL_PIN(20, "GPPC_B_20"),
|
||||
PINCTRL_PIN(21, "GPPC_B_21"),
|
||||
PINCTRL_PIN(22, "GPPC_B_22"),
|
||||
PINCTRL_PIN(23, "GPPC_B_23"),
|
||||
PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
|
||||
/* GPP_T */
|
||||
PINCTRL_PIN(26, "GPPC_T_0"),
|
||||
PINCTRL_PIN(27, "GPPC_T_1"),
|
||||
PINCTRL_PIN(28, "FUSA_DIAGTEST_EN"),
|
||||
PINCTRL_PIN(29, "FUSA_DIAGTEST_MODE"),
|
||||
PINCTRL_PIN(30, "GPPC_T_4"),
|
||||
PINCTRL_PIN(31, "GPPC_T_5"),
|
||||
PINCTRL_PIN(32, "GPPC_T_6"),
|
||||
PINCTRL_PIN(33, "GPPC_T_7"),
|
||||
PINCTRL_PIN(34, "GPPC_T_8"),
|
||||
PINCTRL_PIN(35, "GPPC_T_9"),
|
||||
PINCTRL_PIN(36, "GPPC_T_10"),
|
||||
PINCTRL_PIN(37, "GPPC_T_11"),
|
||||
PINCTRL_PIN(38, "GPPC_T_12"),
|
||||
PINCTRL_PIN(39, "GPPC_T_13"),
|
||||
PINCTRL_PIN(40, "GPPC_T_14"),
|
||||
PINCTRL_PIN(41, "GPPC_T_15"),
|
||||
/* GPP_A */
|
||||
PINCTRL_PIN(42, "ESPI_IO_0"),
|
||||
PINCTRL_PIN(43, "ESPI_IO_1"),
|
||||
PINCTRL_PIN(44, "ESPI_IO_2"),
|
||||
PINCTRL_PIN(45, "ESPI_IO_3"),
|
||||
PINCTRL_PIN(46, "ESPI_CS0B"),
|
||||
PINCTRL_PIN(47, "ESPI_ALERT0B"),
|
||||
PINCTRL_PIN(48, "ESPI_ALERT1B"),
|
||||
PINCTRL_PIN(49, "GPPC_A_7"),
|
||||
PINCTRL_PIN(50, "GPPC_A_8"),
|
||||
PINCTRL_PIN(51, "ESPI_CLK"),
|
||||
PINCTRL_PIN(52, "ESPI_RESETB"),
|
||||
PINCTRL_PIN(53, "GPPC_A_11"),
|
||||
PINCTRL_PIN(54, "GPPC_A_12"),
|
||||
PINCTRL_PIN(55, "GPPC_A_13"),
|
||||
PINCTRL_PIN(56, "GPPC_A_14"),
|
||||
PINCTRL_PIN(57, "GPPC_A_15"),
|
||||
PINCTRL_PIN(58, "GPPC_A_16"),
|
||||
PINCTRL_PIN(59, "GPPC_A_17"),
|
||||
PINCTRL_PIN(60, "GPPC_A_18"),
|
||||
PINCTRL_PIN(61, "GPPC_A_19"),
|
||||
PINCTRL_PIN(62, "GPPC_A_20"),
|
||||
PINCTRL_PIN(63, "GPPC_A_21"),
|
||||
PINCTRL_PIN(64, "GPPC_A_22"),
|
||||
PINCTRL_PIN(65, "ESPI_CS1B"),
|
||||
PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
|
||||
/* GPP_S */
|
||||
PINCTRL_PIN(67, "GPP_S_0"),
|
||||
PINCTRL_PIN(68, "GPP_S_1"),
|
||||
PINCTRL_PIN(69, "GPP_S_2"),
|
||||
PINCTRL_PIN(70, "GPP_S_3"),
|
||||
PINCTRL_PIN(71, "GPP_S_4"),
|
||||
PINCTRL_PIN(72, "GPP_S_5"),
|
||||
PINCTRL_PIN(73, "GPP_S_6"),
|
||||
PINCTRL_PIN(74, "GPP_S_7"),
|
||||
/* GPP_I */
|
||||
PINCTRL_PIN(75, "GPP_F_0_CNV_BRI_DT_UART0_RTSB"),
|
||||
PINCTRL_PIN(76, "GPP_F_1_CNV_BRI_RSP_UART0_RXD"),
|
||||
PINCTRL_PIN(77, "GPP_F_2_CNV_RGI_DT_UART0_TXD"),
|
||||
PINCTRL_PIN(78, "GPP_F_3_CNV_RGI_RSP_UART0_CTSB"),
|
||||
PINCTRL_PIN(79, "GPP_F_4_CNV_RF_RESET_B"),
|
||||
PINCTRL_PIN(80, "GPP_F_5_MODEM_CLKREQ"),
|
||||
PINCTRL_PIN(81, "GPP_F_6_CNV_PA_BLANKING"),
|
||||
PINCTRL_PIN(82, "GPP_F_7_EMMC_CMD"),
|
||||
PINCTRL_PIN(83, "GPP_F_8_EMMC_DATA0"),
|
||||
PINCTRL_PIN(84, "GPP_F_9_EMMC_DATA1"),
|
||||
PINCTRL_PIN(85, "GPP_F_10_EMMC_DATA2"),
|
||||
PINCTRL_PIN(86, "GPP_F_11_EMMC_DATA3"),
|
||||
PINCTRL_PIN(87, "GPP_F_12_EMMC_DATA4"),
|
||||
PINCTRL_PIN(88, "GPP_F_13_EMMC_DATA5"),
|
||||
PINCTRL_PIN(89, "GPP_F_14_EMMC_DATA6"),
|
||||
PINCTRL_PIN(90, "GPP_F_15_EMMC_DATA7"),
|
||||
PINCTRL_PIN(91, "GPP_F_16_EMMC_RCLK"),
|
||||
PINCTRL_PIN(92, "GPP_F_17_EMMC_CLK"),
|
||||
PINCTRL_PIN(93, "GPP_F_18_EMMC_RESETB"),
|
||||
PINCTRL_PIN(94, "GPP_F_19_A4WP_PRESENT"),
|
||||
/* GPP_H */
|
||||
PINCTRL_PIN(95, "GPPC_H_0"),
|
||||
PINCTRL_PIN(96, "GPPC_H_1"),
|
||||
PINCTRL_PIN(97, "GPPC_H_2"),
|
||||
PINCTRL_PIN(98, "GPPC_H_3"),
|
||||
PINCTRL_PIN(99, "GPPC_H_4"),
|
||||
PINCTRL_PIN(100, "GPPC_H_5"),
|
||||
PINCTRL_PIN(101, "GPPC_H_6"),
|
||||
PINCTRL_PIN(102, "GPPC_H_7"),
|
||||
PINCTRL_PIN(103, "GPPC_H_8"),
|
||||
PINCTRL_PIN(104, "GPPC_H_9"),
|
||||
PINCTRL_PIN(105, "GPPC_H_10"),
|
||||
PINCTRL_PIN(106, "GPPC_H_11"),
|
||||
PINCTRL_PIN(107, "I2C7_SDA"),
|
||||
PINCTRL_PIN(108, "I2C7_SCL"),
|
||||
PINCTRL_PIN(109, "GPPC_H_14"),
|
||||
PINCTRL_PIN(110, "GPPC_H_15"),
|
||||
PINCTRL_PIN(111, "GPPC_H_16"),
|
||||
PINCTRL_PIN(112, "GPPC_H_17"),
|
||||
PINCTRL_PIN(113, "CPU_C10_GATEB"),
|
||||
PINCTRL_PIN(114, "GPPC_H_19"),
|
||||
PINCTRL_PIN(115, "GPPC_H_20"),
|
||||
PINCTRL_PIN(116, "GPPC_H_21"),
|
||||
PINCTRL_PIN(117, "GPPC_H_22"),
|
||||
PINCTRL_PIN(118, "GPPC_H_23"),
|
||||
/* GPP_D */
|
||||
PINCTRL_PIN(119, "GPPC_D_0"),
|
||||
PINCTRL_PIN(120, "GPPC_D_1"),
|
||||
PINCTRL_PIN(121, "GPPC_D_2"),
|
||||
PINCTRL_PIN(122, "GPPC_D_3"),
|
||||
PINCTRL_PIN(123, "GPPC_D_4"),
|
||||
PINCTRL_PIN(124, "GPPC_D_5"),
|
||||
PINCTRL_PIN(125, "GPPC_D_6"),
|
||||
PINCTRL_PIN(126, "GPPC_D_7"),
|
||||
PINCTRL_PIN(127, "GPPC_D_8"),
|
||||
PINCTRL_PIN(128, "BSSB_LS2_RX"),
|
||||
PINCTRL_PIN(129, "BSSB_LS2_TX"),
|
||||
PINCTRL_PIN(130, "BSSB_LS3_RX"),
|
||||
PINCTRL_PIN(131, "BSSB_LS3_TX"),
|
||||
PINCTRL_PIN(132, "GPPC_D_13"),
|
||||
PINCTRL_PIN(133, "GPPC_D_14"),
|
||||
PINCTRL_PIN(134, "GPPC_D_15"),
|
||||
PINCTRL_PIN(135, "GPPC_D_16"),
|
||||
PINCTRL_PIN(136, "GPPC_D_17"),
|
||||
PINCTRL_PIN(137, "GPPC_D_18"),
|
||||
PINCTRL_PIN(138, "GPPC_D_19"),
|
||||
PINCTRL_PIN(139, "GSPI2_CLK_LOOPBK"),
|
||||
/* vGPIO */
|
||||
PINCTRL_PIN(140, "CNV_BTEN"),
|
||||
PINCTRL_PIN(141, "CNV_BT_HOST_WAKEB"),
|
||||
PINCTRL_PIN(142, "CNV_BT_IF_SELECT"),
|
||||
PINCTRL_PIN(143, "vCNV_BT_UART_TXD"),
|
||||
PINCTRL_PIN(144, "vCNV_BT_UART_RXD"),
|
||||
PINCTRL_PIN(145, "vCNV_BT_UART_CTS_B"),
|
||||
PINCTRL_PIN(146, "vCNV_BT_UART_RTS_B"),
|
||||
PINCTRL_PIN(147, "vCNV_MFUART1_TXD"),
|
||||
PINCTRL_PIN(148, "vCNV_MFUART1_RXD"),
|
||||
PINCTRL_PIN(149, "vCNV_MFUART1_CTS_B"),
|
||||
PINCTRL_PIN(150, "vCNV_MFUART1_RTS_B"),
|
||||
PINCTRL_PIN(151, "vUART0_TXD"),
|
||||
PINCTRL_PIN(152, "vUART0_RXD"),
|
||||
PINCTRL_PIN(153, "vUART0_CTS_B"),
|
||||
PINCTRL_PIN(154, "vUART0_RTS_B"),
|
||||
PINCTRL_PIN(155, "vISH_UART0_TXD"),
|
||||
PINCTRL_PIN(156, "vISH_UART0_RXD"),
|
||||
PINCTRL_PIN(157, "vISH_UART0_CTS_B"),
|
||||
PINCTRL_PIN(158, "vISH_UART0_RTS_B"),
|
||||
PINCTRL_PIN(159, "vCNV_BT_I2S_BCLK"),
|
||||
PINCTRL_PIN(160, "vCNV_BT_I2S_WS_SYNC"),
|
||||
PINCTRL_PIN(161, "vCNV_BT_I2S_SDO"),
|
||||
PINCTRL_PIN(162, "vCNV_BT_I2S_SDI"),
|
||||
PINCTRL_PIN(163, "vI2S2_SCLK"),
|
||||
PINCTRL_PIN(164, "vI2S2_SFRM"),
|
||||
PINCTRL_PIN(165, "vI2S2_TXD"),
|
||||
PINCTRL_PIN(166, "vI2S2_RXD"),
|
||||
PINCTRL_PIN(167, "THC0_WOT_INT"),
|
||||
PINCTRL_PIN(168, "THC1_WOT_INT"),
|
||||
/* GPP_C */
|
||||
PINCTRL_PIN(169, "SMBCLK"),
|
||||
PINCTRL_PIN(170, "SMBDATA"),
|
||||
PINCTRL_PIN(171, "SMBALERTB"),
|
||||
PINCTRL_PIN(172, "SML0CLK"),
|
||||
PINCTRL_PIN(173, "SML0DATA"),
|
||||
PINCTRL_PIN(174, "GPPC_C_5"),
|
||||
PINCTRL_PIN(175, "GPPC_C_6"),
|
||||
PINCTRL_PIN(176, "GPPC_C_7"),
|
||||
PINCTRL_PIN(177, "GPPC_C_8"),
|
||||
PINCTRL_PIN(178, "GPPC_C_9"),
|
||||
PINCTRL_PIN(179, "GPPC_C_10"),
|
||||
PINCTRL_PIN(180, "GPPC_C_11"),
|
||||
PINCTRL_PIN(181, "GPPC_C_12"),
|
||||
PINCTRL_PIN(182, "GPPC_C_13"),
|
||||
PINCTRL_PIN(183, "GPPC_C_14"),
|
||||
PINCTRL_PIN(184, "GPPC_C_15"),
|
||||
PINCTRL_PIN(185, "GPPC_C_16"),
|
||||
PINCTRL_PIN(186, "GPPC_C_17"),
|
||||
PINCTRL_PIN(187, "GPPC_C_18"),
|
||||
PINCTRL_PIN(188, "GPPC_C_19"),
|
||||
PINCTRL_PIN(189, "GPPC_C_20"),
|
||||
PINCTRL_PIN(190, "GPPC_C_21"),
|
||||
PINCTRL_PIN(191, "GPPC_C_22"),
|
||||
PINCTRL_PIN(192, "GPPC_C_23"),
|
||||
/* GPP_F */
|
||||
PINCTRL_PIN(193, "CNV_BRI_DT"),
|
||||
PINCTRL_PIN(194, "CNV_BRI_RSP"),
|
||||
PINCTRL_PIN(195, "CNV_RGI_DT"),
|
||||
PINCTRL_PIN(196, "CNV_RGI_RSP"),
|
||||
PINCTRL_PIN(197, "CNV_RF_RESET_B"),
|
||||
PINCTRL_PIN(198, "MODEM_CLKREQ"),
|
||||
PINCTRL_PIN(199, "GPPC_F_6"),
|
||||
PINCTRL_PIN(200, "GPPC_F_7"),
|
||||
PINCTRL_PIN(201, "GPPC_F_8"),
|
||||
PINCTRL_PIN(202, "BOOTMPC"),
|
||||
PINCTRL_PIN(203, "GPPC_F_10"),
|
||||
PINCTRL_PIN(204, "GPPC_F_11"),
|
||||
PINCTRL_PIN(205, "GPPC_F_12"),
|
||||
PINCTRL_PIN(206, "GPPC_F_13"),
|
||||
PINCTRL_PIN(207, "GPPC_F_14"),
|
||||
PINCTRL_PIN(208, "GPPC_F_15"),
|
||||
PINCTRL_PIN(209, "GPPC_F_16"),
|
||||
PINCTRL_PIN(210, "GPPC_F_17"),
|
||||
PINCTRL_PIN(211, "GPPC_F_18"),
|
||||
PINCTRL_PIN(212, "GPPC_F_19"),
|
||||
PINCTRL_PIN(213, "EXT_PWR_GATEB"),
|
||||
PINCTRL_PIN(214, "EXT_PWR_GATE2B"),
|
||||
PINCTRL_PIN(215, "GPPC_F_22"),
|
||||
PINCTRL_PIN(216, "GPPC_F_23"),
|
||||
PINCTRL_PIN(217, "GPPF_CLK_LOOPBACK"),
|
||||
/* HVCMOS */
|
||||
PINCTRL_PIN(218, "L_BKLTEN"),
|
||||
PINCTRL_PIN(219, "L_BKLTCTL"),
|
||||
PINCTRL_PIN(220, "L_VDDEN"),
|
||||
PINCTRL_PIN(221, "SYS_PWROK"),
|
||||
PINCTRL_PIN(222, "SYS_RESETB"),
|
||||
PINCTRL_PIN(223, "MLK_RSTB"),
|
||||
/* GPP_E */
|
||||
PINCTRL_PIN(224, "GPPC_E_0"),
|
||||
PINCTRL_PIN(225, "GPPC_E_1"),
|
||||
PINCTRL_PIN(226, "GPPC_E_2"),
|
||||
PINCTRL_PIN(227, "GPPC_E_3"),
|
||||
PINCTRL_PIN(228, "GPPC_E_4"),
|
||||
PINCTRL_PIN(229, "GPPC_E_5"),
|
||||
PINCTRL_PIN(230, "GPPC_E_6"),
|
||||
PINCTRL_PIN(231, "GPPC_E_7"),
|
||||
PINCTRL_PIN(232, "GPPC_E_8"),
|
||||
PINCTRL_PIN(233, "GPPC_E_9"),
|
||||
PINCTRL_PIN(234, "GPPC_E_10"),
|
||||
PINCTRL_PIN(235, "GPPC_E_11"),
|
||||
PINCTRL_PIN(236, "GPPC_E_12"),
|
||||
PINCTRL_PIN(237, "GPPC_E_13"),
|
||||
PINCTRL_PIN(238, "GPPC_E_14"),
|
||||
PINCTRL_PIN(239, "FIVR_DIGPB_0"),
|
||||
PINCTRL_PIN(240, "FIVR_DIGPB_1"),
|
||||
PINCTRL_PIN(241, "GPPC_E_17"),
|
||||
PINCTRL_PIN(242, "BSSB_LS0_RX"),
|
||||
PINCTRL_PIN(243, "BSSB_LS0_TX"),
|
||||
PINCTRL_PIN(244, "BSSB_LS1_RX"),
|
||||
PINCTRL_PIN(245, "BSSB_LS1_TX"),
|
||||
PINCTRL_PIN(246, "DNX_FORCE_RELOAD"),
|
||||
PINCTRL_PIN(247, "GPPC_E_23"),
|
||||
PINCTRL_PIN(248, "GPPE_CLK_LOOPBACK"),
|
||||
/* GPP_R */
|
||||
PINCTRL_PIN(249, "HDA_BCLK"),
|
||||
PINCTRL_PIN(250, "HDA_SYNC"),
|
||||
PINCTRL_PIN(251, "HDA_SDO"),
|
||||
PINCTRL_PIN(252, "HDA_SDI_0"),
|
||||
PINCTRL_PIN(253, "HDA_RSTB"),
|
||||
PINCTRL_PIN(254, "GPP_R_5"),
|
||||
PINCTRL_PIN(255, "GPP_R_6"),
|
||||
PINCTRL_PIN(256, "GPP_R_7"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup adln_community0_gpps[] = {
|
||||
ADL_GPP(0, 0, 25, 0), /* GPP_B */
|
||||
ADL_GPP(1, 26, 41, 32), /* GPP_T */
|
||||
ADL_GPP(2, 42, 66, 64), /* GPP_A */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup adln_community1_gpps[] = {
|
||||
ADL_GPP(0, 67, 74, 96), /* GPP_S */
|
||||
ADL_GPP(1, 75, 94, 128), /* GPP_I */
|
||||
ADL_GPP(2, 95, 118, 160), /* GPP_H */
|
||||
ADL_GPP(3, 119, 139, 192), /* GPP_D */
|
||||
ADL_GPP(4, 140, 168, 224), /* vGPIO */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup adln_community4_gpps[] = {
|
||||
ADL_GPP(0, 169, 192, 256), /* GPP_C */
|
||||
ADL_GPP(1, 193, 217, 288), /* GPP_F */
|
||||
ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
|
||||
ADL_GPP(3, 224, 248, 320), /* GPP_E */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup adln_community5_gpps[] = {
|
||||
ADL_GPP(0, 249, 256, 352), /* GPP_R */
|
||||
};
|
||||
|
||||
static const struct intel_community adln_communities[] = {
|
||||
ADL_COMMUNITY(0, 0, 66, adln_community0_gpps),
|
||||
ADL_COMMUNITY(1, 67, 168, adln_community1_gpps),
|
||||
ADL_COMMUNITY(2, 169, 248, adln_community4_gpps),
|
||||
ADL_COMMUNITY(3, 249, 256, adln_community5_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data adln_soc_data = {
|
||||
.pins = adln_pins,
|
||||
.npins = ARRAY_SIZE(adln_pins),
|
||||
.communities = adln_communities,
|
||||
.ncommunities = ARRAY_SIZE(adln_communities),
|
||||
};
|
||||
|
||||
/* Alder Lake-S */
|
||||
static const struct pinctrl_pin_desc adls_pins[] = {
|
||||
/* GPP_I */
|
||||
@ -416,6 +729,8 @@ static const struct intel_pinctrl_soc_data adls_soc_data = {
|
||||
|
||||
static const struct acpi_device_id adl_pinctrl_acpi_match[] = {
|
||||
{ "INTC1056", (kernel_ulong_t)&adls_soc_data },
|
||||
{ "INTC1057", (kernel_ulong_t)&adln_soc_data },
|
||||
{ "INTC1085", (kernel_ulong_t)&adls_soc_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
#define BYT_VAL_REG 0x008
|
||||
#define BYT_DFT_REG 0x00c
|
||||
#define BYT_INT_STAT_REG 0x800
|
||||
#define BYT_DIRECT_IRQ_REG 0x980
|
||||
#define BYT_DEBOUNCE_REG 0x9d0
|
||||
|
||||
/* BYT_CONF0_REG register bits */
|
||||
@ -1475,6 +1476,51 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
|
||||
chip->irq_eoi(data);
|
||||
}
|
||||
|
||||
static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
|
||||
{
|
||||
int direct_irq, ioapic_direct_irq_base;
|
||||
u8 *match, direct_irq_mux[16];
|
||||
u32 trig;
|
||||
|
||||
memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
|
||||
sizeof(direct_irq_mux));
|
||||
match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
|
||||
if (!match) {
|
||||
dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
|
||||
return false;
|
||||
}
|
||||
|
||||
direct_irq = match - direct_irq_mux;
|
||||
/* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
|
||||
ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
|
||||
dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
|
||||
direct_irq, direct_irq + ioapic_direct_irq_base);
|
||||
|
||||
/*
|
||||
* Testing has shown that the way direct IRQs work is that the combination of the
|
||||
* direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
|
||||
* trigger block, which normally sets the status flag in the IRQ status reg at
|
||||
* 0x800, to one of the IO-APIC pins according to the mux registers.
|
||||
*
|
||||
* This means that:
|
||||
* 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
|
||||
* 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
|
||||
* passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
|
||||
* selecting edge mode operation then on the first edge the IO-APIC pin goes
|
||||
* high, but since no write-to-clear write will be done to the IRQ status reg
|
||||
* at 0x800, the detected edge condition will never get cleared.
|
||||
*/
|
||||
trig = conf0 & BYT_TRIG_MASK;
|
||||
if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
|
||||
trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
|
||||
dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
|
||||
pin, conf0);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void byt_init_irq_valid_mask(struct gpio_chip *chip,
|
||||
unsigned long *valid_mask,
|
||||
unsigned int ngpios)
|
||||
@ -1502,8 +1548,13 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
|
||||
|
||||
value = readl(reg);
|
||||
if (value & BYT_DIRECT_IRQ_EN) {
|
||||
clear_bit(i, valid_mask);
|
||||
dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
|
||||
if (byt_direct_irq_sanity_check(vg, i, value)) {
|
||||
clear_bit(i, valid_mask);
|
||||
} else {
|
||||
value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
|
||||
BYT_TRIG_NEG | BYT_TRIG_LVL);
|
||||
writel(value, reg);
|
||||
}
|
||||
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
|
||||
byt_gpio_clear_triggering(vg, i);
|
||||
dev_dbg(vg->dev, "disabling GPIO %d\n", i);
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Intel Ice Lake PCH pinctrl/GPIO driver
|
||||
*
|
||||
* Copyright (C) 2018, Intel Corporation
|
||||
* Copyright (C) 2018, 2022 Intel Corporation
|
||||
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
* Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
*/
|
||||
@ -19,7 +19,8 @@
|
||||
#define ICL_PADCFGLOCK 0x080
|
||||
#define ICL_HOSTSW_OWN 0x0b0
|
||||
#define ICL_GPI_IS 0x100
|
||||
#define ICL_GPI_IE 0x110
|
||||
#define ICL_LP_GPI_IE 0x110
|
||||
#define ICL_N_GPI_IE 0x120
|
||||
|
||||
#define ICL_GPP(r, s, e, g) \
|
||||
{ \
|
||||
@ -29,20 +30,26 @@
|
||||
.gpio_base = (g), \
|
||||
}
|
||||
|
||||
#define ICL_COMMUNITY(b, s, e, g) \
|
||||
#define ICL_COMMUNITY(b, s, e, ie, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = ICL_PAD_OWN, \
|
||||
.padcfglock_offset = ICL_PADCFGLOCK, \
|
||||
.hostown_offset = ICL_HOSTSW_OWN, \
|
||||
.is_offset = ICL_GPI_IS, \
|
||||
.ie_offset = ICL_GPI_IE, \
|
||||
.ie_offset = (ie), \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
#define ICL_LP_COMMUNITY(b, s, e, g) \
|
||||
ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g)
|
||||
|
||||
#define ICL_N_COMMUNITY(b, s, e, g) \
|
||||
ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g)
|
||||
|
||||
/* Ice Lake-LP */
|
||||
static const struct pinctrl_pin_desc icllp_pins[] = {
|
||||
/* GPP_G */
|
||||
@ -329,10 +336,10 @@ static const struct intel_padgroup icllp_community5_gpps[] = {
|
||||
};
|
||||
|
||||
static const struct intel_community icllp_communities[] = {
|
||||
ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),
|
||||
ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),
|
||||
ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),
|
||||
ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),
|
||||
ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps),
|
||||
ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps),
|
||||
ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps),
|
||||
ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps),
|
||||
};
|
||||
|
||||
static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
|
||||
@ -403,10 +410,278 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = {
|
||||
.ncommunities = ARRAY_SIZE(icllp_communities),
|
||||
};
|
||||
|
||||
/* Ice Lake-N */
|
||||
static const struct pinctrl_pin_desc icln_pins[] = {
|
||||
/* SPI */
|
||||
PINCTRL_PIN(0, "SPI0_IO_2"),
|
||||
PINCTRL_PIN(1, "SPI0_IO_3"),
|
||||
PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
|
||||
PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
|
||||
PINCTRL_PIN(4, "SPI0_TPM_CSB"),
|
||||
PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
|
||||
PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
|
||||
PINCTRL_PIN(7, "SPI0_CLK"),
|
||||
PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"),
|
||||
/* GPP_B */
|
||||
PINCTRL_PIN(9, "CORE_VID_0"),
|
||||
PINCTRL_PIN(10, "CORE_VID_1"),
|
||||
PINCTRL_PIN(11, "VRALERTB"),
|
||||
PINCTRL_PIN(12, "CPU_GP_2"),
|
||||
PINCTRL_PIN(13, "CPU_GP_3"),
|
||||
PINCTRL_PIN(14, "SRCCLKREQB_0"),
|
||||
PINCTRL_PIN(15, "SRCCLKREQB_1"),
|
||||
PINCTRL_PIN(16, "SRCCLKREQB_2"),
|
||||
PINCTRL_PIN(17, "SRCCLKREQB_3"),
|
||||
PINCTRL_PIN(18, "SRCCLKREQB_4"),
|
||||
PINCTRL_PIN(19, "SRCCLKREQB_5"),
|
||||
PINCTRL_PIN(20, "EXT_PWR_GATEB"),
|
||||
PINCTRL_PIN(21, "SLP_S0B"),
|
||||
PINCTRL_PIN(22, "PLTRSTB"),
|
||||
PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"),
|
||||
PINCTRL_PIN(24, "GSPI0_CS0B"),
|
||||
PINCTRL_PIN(25, "GSPI0_CLK"),
|
||||
PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"),
|
||||
PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"),
|
||||
PINCTRL_PIN(28, "GSPI1_CS0B"),
|
||||
PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"),
|
||||
PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"),
|
||||
PINCTRL_PIN(31, "GSPI1_MOSI"),
|
||||
PINCTRL_PIN(32, "GSPI1_CS1B"),
|
||||
PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"),
|
||||
/* GPP_A */
|
||||
PINCTRL_PIN(35, "ESPI_IO_0"),
|
||||
PINCTRL_PIN(36, "ESPI_IO_1"),
|
||||
PINCTRL_PIN(37, "ESPI_IO_2"),
|
||||
PINCTRL_PIN(38, "ESPI_IO_3"),
|
||||
PINCTRL_PIN(39, "ESPI_CSB"),
|
||||
PINCTRL_PIN(40, "ESPI_CLK"),
|
||||
PINCTRL_PIN(41, "ESPI_RESETB"),
|
||||
PINCTRL_PIN(42, "SMBCLK"),
|
||||
PINCTRL_PIN(43, "SMBDATA"),
|
||||
PINCTRL_PIN(44, "SMBALERTB"),
|
||||
PINCTRL_PIN(45, "CPU_GP_0"),
|
||||
PINCTRL_PIN(46, "CPU_GP_1"),
|
||||
PINCTRL_PIN(47, "USB2_OCB_1"),
|
||||
PINCTRL_PIN(48, "USB2_OCB_2"),
|
||||
PINCTRL_PIN(49, "USB2_OCB_3"),
|
||||
PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"),
|
||||
PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"),
|
||||
PINCTRL_PIN(52, "DDSP_HPD_C"),
|
||||
PINCTRL_PIN(53, "USB2_OCB_0"),
|
||||
PINCTRL_PIN(54, "PCHHOTB"),
|
||||
PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"),
|
||||
/* GPP_S */
|
||||
PINCTRL_PIN(56, "SNDW1_CLK"),
|
||||
PINCTRL_PIN(57, "SNDW1_DATA"),
|
||||
PINCTRL_PIN(58, "SNDW2_CLK"),
|
||||
PINCTRL_PIN(59, "SNDW2_DATA"),
|
||||
PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"),
|
||||
PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"),
|
||||
PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"),
|
||||
PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"),
|
||||
/* GPP_R */
|
||||
PINCTRL_PIN(64, "HDA_BCLK"),
|
||||
PINCTRL_PIN(65, "HDA_SYNC"),
|
||||
PINCTRL_PIN(66, "HDA_SDO"),
|
||||
PINCTRL_PIN(67, "HDA_SDI_0"),
|
||||
PINCTRL_PIN(68, "HDA_RSTB"),
|
||||
PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"),
|
||||
PINCTRL_PIN(70, "I2S1_SFRM"),
|
||||
PINCTRL_PIN(71, "I2S1_TXD"),
|
||||
/* GPP_H */
|
||||
PINCTRL_PIN(72, "GPPC_H_0"),
|
||||
PINCTRL_PIN(73, "CNV_RF_RESET_B"),
|
||||
PINCTRL_PIN(74, "MODEM_CLKREQ"),
|
||||
PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"),
|
||||
PINCTRL_PIN(76, "I2C2_SDA"),
|
||||
PINCTRL_PIN(77, "I2C2_SCL"),
|
||||
PINCTRL_PIN(78, "I2C3_SDA"),
|
||||
PINCTRL_PIN(79, "I2C3_SCL"),
|
||||
PINCTRL_PIN(80, "I2C4_SDA"),
|
||||
PINCTRL_PIN(81, "I2C4_SCL"),
|
||||
PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"),
|
||||
PINCTRL_PIN(83, "I2S2_SCLK"),
|
||||
PINCTRL_PIN(84, "CNV_RF_RESET_B"),
|
||||
PINCTRL_PIN(85, "MODEM_CLKREQ"),
|
||||
PINCTRL_PIN(86, "I2S2_RXD"),
|
||||
PINCTRL_PIN(87, "I2S1_SCLK"),
|
||||
PINCTRL_PIN(88, "GPPC_H_16"),
|
||||
PINCTRL_PIN(89, "GPPC_H_17"),
|
||||
PINCTRL_PIN(90, "GPPC_H_18"),
|
||||
PINCTRL_PIN(91, "GPPC_H_19"),
|
||||
PINCTRL_PIN(92, "GPPC_H_20"),
|
||||
PINCTRL_PIN(93, "GPPC_H_21"),
|
||||
PINCTRL_PIN(94, "GPPC_H_22"),
|
||||
PINCTRL_PIN(95, "GPPC_H_23"),
|
||||
/* GPP_D */
|
||||
PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"),
|
||||
PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"),
|
||||
PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"),
|
||||
PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"),
|
||||
PINCTRL_PIN(100, "ISH_I2C0_SDA"),
|
||||
PINCTRL_PIN(101, "ISH_I2C0_SCL"),
|
||||
PINCTRL_PIN(102, "ISH_I2C1_SDA"),
|
||||
PINCTRL_PIN(103, "ISH_I2C1_SCL"),
|
||||
PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"),
|
||||
PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"),
|
||||
PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"),
|
||||
PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"),
|
||||
PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"),
|
||||
PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"),
|
||||
PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"),
|
||||
PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"),
|
||||
PINCTRL_PIN(112, "SPI1_IO_2"),
|
||||
PINCTRL_PIN(113, "SPI1_IO_3"),
|
||||
PINCTRL_PIN(114, "I2S_MCLK"),
|
||||
PINCTRL_PIN(115, "CNV_MFUART2_RXD"),
|
||||
PINCTRL_PIN(116, "CNV_MFUART2_TXD"),
|
||||
PINCTRL_PIN(117, "CNV_PA_BLANKING"),
|
||||
PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"),
|
||||
PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"),
|
||||
PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"),
|
||||
/* vGPIO */
|
||||
PINCTRL_PIN(122, "CNV_BTEN"),
|
||||
PINCTRL_PIN(123, "CNV_WCEN"),
|
||||
PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"),
|
||||
PINCTRL_PIN(125, "CNV_BT_IF_SELECT"),
|
||||
PINCTRL_PIN(126, "vCNV_BT_UART_TXD"),
|
||||
PINCTRL_PIN(127, "vCNV_BT_UART_RXD"),
|
||||
PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"),
|
||||
PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"),
|
||||
PINCTRL_PIN(130, "vCNV_MFUART1_TXD"),
|
||||
PINCTRL_PIN(131, "vCNV_MFUART1_RXD"),
|
||||
PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"),
|
||||
PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"),
|
||||
PINCTRL_PIN(134, "vUART0_TXD"),
|
||||
PINCTRL_PIN(135, "vUART0_RXD"),
|
||||
PINCTRL_PIN(136, "vUART0_CTS_B"),
|
||||
PINCTRL_PIN(137, "vUART0_RTS_B"),
|
||||
PINCTRL_PIN(138, "vISH_UART0_TXD"),
|
||||
PINCTRL_PIN(139, "vISH_UART0_RXD"),
|
||||
PINCTRL_PIN(140, "vISH_UART0_CTS_B"),
|
||||
PINCTRL_PIN(141, "vISH_UART0_RTS_B"),
|
||||
PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"),
|
||||
PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"),
|
||||
PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"),
|
||||
PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"),
|
||||
PINCTRL_PIN(146, "vI2S2_SCLK"),
|
||||
PINCTRL_PIN(147, "vI2S2_SFRM"),
|
||||
PINCTRL_PIN(148, "vI2S2_TXD"),
|
||||
PINCTRL_PIN(149, "vI2S2_RXD"),
|
||||
PINCTRL_PIN(150, "vSD3_CD_B"),
|
||||
/* GPP_C */
|
||||
PINCTRL_PIN(151, "GPPC_C_0"),
|
||||
PINCTRL_PIN(152, "GPPC_C_1"),
|
||||
PINCTRL_PIN(153, "GPPC_C_2"),
|
||||
PINCTRL_PIN(154, "GPPC_C_3"),
|
||||
PINCTRL_PIN(155, "GPPC_C_4"),
|
||||
PINCTRL_PIN(156, "GPPC_C_5"),
|
||||
PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"),
|
||||
PINCTRL_PIN(158, "SUSACKB"),
|
||||
PINCTRL_PIN(159, "UART0_RXD"),
|
||||
PINCTRL_PIN(160, "UART0_TXD"),
|
||||
PINCTRL_PIN(161, "UART0_RTSB"),
|
||||
PINCTRL_PIN(162, "UART0_CTSB"),
|
||||
PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"),
|
||||
PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"),
|
||||
PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"),
|
||||
PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"),
|
||||
PINCTRL_PIN(167, "I2C0_SDA"),
|
||||
PINCTRL_PIN(168, "I2C0_SCL"),
|
||||
PINCTRL_PIN(169, "I2C1_SDA"),
|
||||
PINCTRL_PIN(170, "I2C1_SCL"),
|
||||
PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"),
|
||||
PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"),
|
||||
PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"),
|
||||
PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"),
|
||||
/* HVCMOS */
|
||||
PINCTRL_PIN(175, "L_BKLTEN"),
|
||||
PINCTRL_PIN(176, "L_BKLTCTL"),
|
||||
PINCTRL_PIN(177, "L_VDDEN"),
|
||||
PINCTRL_PIN(178, "SYS_PWROK"),
|
||||
PINCTRL_PIN(179, "SYS_RESETB"),
|
||||
PINCTRL_PIN(180, "MLK_RSTB"),
|
||||
/* GPP_E */
|
||||
PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"),
|
||||
PINCTRL_PIN(182, "ISH_GP_1"),
|
||||
PINCTRL_PIN(183, "IMGCLKOUT_1"),
|
||||
PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"),
|
||||
PINCTRL_PIN(185, "IMGCLKOUT_2"),
|
||||
PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"),
|
||||
PINCTRL_PIN(187, "IMGCLKOUT_3"),
|
||||
PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"),
|
||||
PINCTRL_PIN(189, "FIVR_DIGPB_0"),
|
||||
PINCTRL_PIN(190, "SML0CLK"),
|
||||
PINCTRL_PIN(191, "SML0DATA"),
|
||||
PINCTRL_PIN(192, "BSSB_LS3_RX"),
|
||||
PINCTRL_PIN(193, "BSSB_LS3_TX"),
|
||||
PINCTRL_PIN(194, "BSSB_LS0_RX"),
|
||||
PINCTRL_PIN(195, "BSSB_LS0_TX"),
|
||||
PINCTRL_PIN(196, "BSSB_LS1_RX"),
|
||||
PINCTRL_PIN(197, "BSSB_LS1_TX"),
|
||||
PINCTRL_PIN(198, "BSSB_LS2_RX"),
|
||||
PINCTRL_PIN(199, "BSSB_LS2_TX"),
|
||||
PINCTRL_PIN(200, "FIVR_DIGPB_1"),
|
||||
PINCTRL_PIN(201, "CNV_BRI_DT"),
|
||||
PINCTRL_PIN(202, "CNV_BRI_RSP"),
|
||||
PINCTRL_PIN(203, "CNV_RGI_DT"),
|
||||
PINCTRL_PIN(204, "CNV_RGI_RSP"),
|
||||
/* GPP_G */
|
||||
PINCTRL_PIN(205, "SD3_CMD"),
|
||||
PINCTRL_PIN(206, "SD3_D0"),
|
||||
PINCTRL_PIN(207, "SD3_D1"),
|
||||
PINCTRL_PIN(208, "SD3_D2"),
|
||||
PINCTRL_PIN(209, "SD3_D3"),
|
||||
PINCTRL_PIN(210, "SD3_CDB"),
|
||||
PINCTRL_PIN(211, "SD3_CLK"),
|
||||
PINCTRL_PIN(212, "SD3_WP"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup icln_community0_gpps[] = {
|
||||
ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
|
||||
ICL_GPP(1, 9, 34, 32), /* GPP_B */
|
||||
ICL_GPP(2, 35, 55, 64), /* GPP_A */
|
||||
ICL_GPP(3, 56, 63, 96), /* GPP_S */
|
||||
ICL_GPP(4, 64, 71, 128), /* GPP_R */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup icln_community1_gpps[] = {
|
||||
ICL_GPP(0, 72, 95, 160), /* GPP_H */
|
||||
ICL_GPP(1, 96, 121, 192), /* GPP_D */
|
||||
ICL_GPP(2, 122, 150, 224), /* vGPIO */
|
||||
ICL_GPP(3, 151, 174, 256), /* GPP_C */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup icln_community4_gpps[] = {
|
||||
ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
|
||||
ICL_GPP(1, 181, 204, 288), /* GPP_E */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup icln_community5_gpps[] = {
|
||||
ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
|
||||
};
|
||||
|
||||
static const struct intel_community icln_communities[] = {
|
||||
ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps),
|
||||
ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps),
|
||||
ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps),
|
||||
ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data icln_soc_data = {
|
||||
.pins = icln_pins,
|
||||
.npins = ARRAY_SIZE(icln_pins),
|
||||
.communities = icln_communities,
|
||||
.ncommunities = ARRAY_SIZE(icln_communities),
|
||||
};
|
||||
|
||||
static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
|
||||
|
||||
static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
|
||||
{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
|
||||
{ "INT34C3", (kernel_ulong_t)&icln_soc_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
|
||||
|
||||
@ -147,6 +147,13 @@ config PINCTRL_MT8183
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT8186
|
||||
bool "Mediatek MT8186 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT8192
|
||||
bool "Mediatek MT8192 pin control"
|
||||
depends on OF
|
||||
|
||||
@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
|
||||
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
|
||||
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
|
||||
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
|
||||
obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
|
||||
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
|
||||
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
|
||||
obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
|
||||
|
||||
@ -605,6 +605,7 @@ static int mtk_build_functions(struct mtk_pinctrl *hw)
|
||||
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct mtk_pin_soc *soc)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct pinctrl_pin_desc *pins;
|
||||
struct mtk_pinctrl *hw;
|
||||
int err, i;
|
||||
@ -616,11 +617,9 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
|
||||
hw->soc = soc;
|
||||
hw->dev = &pdev->dev;
|
||||
|
||||
if (!hw->soc->nbase_names) {
|
||||
dev_err(&pdev->dev,
|
||||
if (!hw->soc->nbase_names)
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"SoC should be assigned at least one register base\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
|
||||
sizeof(*hw->base), GFP_KERNEL);
|
||||
@ -665,17 +664,13 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
|
||||
|
||||
/* Setup groups descriptions per SoC types */
|
||||
err = mtk_build_groups(hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to build groups\n");
|
||||
return err;
|
||||
}
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "Failed to build groups\n");
|
||||
|
||||
/* Setup functions descriptions per SoC types */
|
||||
err = mtk_build_functions(hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to build functions\n");
|
||||
return err;
|
||||
}
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "Failed to build functions\n");
|
||||
|
||||
/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
|
||||
* until all groups and functions are being added one.
|
||||
@ -691,10 +686,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
|
||||
|
||||
/* Build gpiochip should be after pinctrl_enable is done */
|
||||
err = mtk_build_gpiochip(hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
|
||||
return err;
|
||||
}
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
|
||||
|
||||
platform_set_drvdata(pdev, hw);
|
||||
|
||||
|
||||
@ -270,13 +270,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
|
||||
MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
|
||||
};
|
||||
|
||||
static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
{
|
||||
return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
|
||||
ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
|
||||
}
|
||||
|
||||
static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
|
||||
MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
|
||||
@ -436,18 +429,6 @@ static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
|
||||
};
|
||||
|
||||
static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, int value, enum pin_config_param arg)
|
||||
{
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
|
||||
ARRAY_SIZE(mt2701_ies_set), pin, align, value);
|
||||
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
|
||||
ARRAY_SIZE(mt2701_smt_set), pin, align, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
|
||||
MTK_PINMUX_SPEC(22, 0xb10, 3),
|
||||
MTK_PINMUX_SPEC(23, 0xb10, 4),
|
||||
@ -508,8 +489,14 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
|
||||
.n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
|
||||
.pin_drv_grp = mt2701_pin_drv,
|
||||
.n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
|
||||
.spec_pull_set = mt2701_spec_pull_set,
|
||||
.spec_ies_smt_set = mt2701_ies_smt_set,
|
||||
.spec_ies = mt2701_ies_set,
|
||||
.n_spec_ies = ARRAY_SIZE(mt2701_ies_set),
|
||||
.spec_pupd = mt2701_spec_pupd,
|
||||
.n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd),
|
||||
.spec_smt = mt2701_smt_set,
|
||||
.n_spec_smt = ARRAY_SIZE(mt2701_smt_set),
|
||||
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
|
||||
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
|
||||
.spec_pinmux_set = mt2701_spec_pinmux_set,
|
||||
.spec_dir_set = mt2701_spec_dir_set,
|
||||
.dir_offset = 0x0000,
|
||||
@ -534,20 +521,15 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
|
||||
},
|
||||
};
|
||||
|
||||
static int mt2701_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id mt2701_pctrl_match[] = {
|
||||
{ .compatible = "mediatek,mt2701-pinctrl", },
|
||||
{ .compatible = "mediatek,mt7623-pinctrl", },
|
||||
{ .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data },
|
||||
{ .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
|
||||
|
||||
static struct platform_driver mtk_pinctrl_driver = {
|
||||
.probe = mt2701_pinctrl_probe,
|
||||
.probe = mtk_pctrl_common_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-mt2701-pinctrl",
|
||||
.of_match_table = mt2701_pctrl_match,
|
||||
|
||||
@ -81,16 +81,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
|
||||
MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
|
||||
};
|
||||
|
||||
static int mt2712_spec_pull_set(struct regmap *regmap,
|
||||
unsigned int pin,
|
||||
unsigned char align,
|
||||
bool isup,
|
||||
unsigned int r1r0)
|
||||
{
|
||||
return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
|
||||
ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
|
||||
}
|
||||
|
||||
static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
|
||||
MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
|
||||
@ -285,19 +275,6 @@ static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
|
||||
};
|
||||
|
||||
static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align,
|
||||
int value, enum pin_config_param arg)
|
||||
{
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
|
||||
ARRAY_SIZE(mt2712_ies_set), pin, align, value);
|
||||
if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
|
||||
ARRAY_SIZE(mt2712_smt_set), pin, align, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
|
||||
/* 0E4E8SR 4/8/12/16 */
|
||||
MTK_DRV_GRP(4, 16, 1, 2, 4),
|
||||
@ -563,8 +540,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
|
||||
.n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
|
||||
.pin_drv_grp = mt2712_pin_drv,
|
||||
.n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
|
||||
.spec_pull_set = mt2712_spec_pull_set,
|
||||
.spec_ies_smt_set = mt2712_ies_smt_set,
|
||||
.spec_ies = mt2712_ies_set,
|
||||
.n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
|
||||
.spec_pupd = mt2712_spec_pupd,
|
||||
.n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
|
||||
.spec_smt = mt2712_smt_set,
|
||||
.n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
|
||||
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
|
||||
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
|
||||
.dir_offset = 0x0000,
|
||||
.pullen_offset = 0x0100,
|
||||
.pullsel_offset = 0x0200,
|
||||
@ -587,21 +570,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
|
||||
},
|
||||
};
|
||||
|
||||
static int mt2712_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id mt2712_pctrl_match[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt2712-pinctrl",
|
||||
},
|
||||
{ .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
|
||||
|
||||
static struct platform_driver mtk_pinctrl_driver = {
|
||||
.probe = mt2712_pinctrl_probe,
|
||||
.probe = mtk_pctrl_common_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-mt2712-pinctrl",
|
||||
.of_match_table = mt2712_pctrl_match,
|
||||
|
||||
@ -1082,21 +1082,16 @@ static const struct mtk_pin_soc mt6765_data = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mt6765_pinctrl_of_match[] = {
|
||||
{ .compatible = "mediatek,mt6765-pinctrl", },
|
||||
{ .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int mt6765_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_paris_pinctrl_probe(pdev, &mt6765_data);
|
||||
}
|
||||
|
||||
static struct platform_driver mt6765_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mt6765-pinctrl",
|
||||
.of_match_table = mt6765_pinctrl_of_match,
|
||||
},
|
||||
.probe = mt6765_pinctrl_probe,
|
||||
.probe = mtk_paris_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init mt6765_pinctrl_init(void)
|
||||
|
||||
@ -758,21 +758,16 @@ static const struct mtk_pin_soc mt6779_data = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mt6779_pinctrl_of_match[] = {
|
||||
{ .compatible = "mediatek,mt6779-pinctrl", },
|
||||
{ .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int mt6779_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_paris_pinctrl_probe(pdev, &mt6779_data);
|
||||
}
|
||||
|
||||
static struct platform_driver mt6779_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mt6779-pinctrl",
|
||||
.of_match_table = mt6779_pinctrl_of_match,
|
||||
},
|
||||
.probe = mt6779_pinctrl_probe,
|
||||
.probe = mtk_paris_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init mt6779_pinctrl_init(void)
|
||||
|
||||
@ -58,21 +58,16 @@ static const struct mtk_pin_soc mt6797_data = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mt6797_pinctrl_of_match[] = {
|
||||
{ .compatible = "mediatek,mt6797-pinctrl", },
|
||||
{ .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int mt6797_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
|
||||
}
|
||||
|
||||
static struct platform_driver mt6797_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mt6797-pinctrl",
|
||||
.of_match_table = mt6797_pinctrl_of_match,
|
||||
},
|
||||
.probe = mt6797_pinctrl_probe,
|
||||
.probe = mtk_paris_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init mt6797_pinctrl_init(void)
|
||||
|
||||
@ -172,13 +172,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
|
||||
MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
|
||||
};
|
||||
|
||||
static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
{
|
||||
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd,
|
||||
ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
|
||||
}
|
||||
|
||||
static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
|
||||
MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
|
||||
@ -259,19 +252,6 @@ static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
|
||||
};
|
||||
|
||||
static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, int value, enum pin_config_param arg)
|
||||
{
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
|
||||
ARRAY_SIZE(mt8127_ies_set), pin, align, value);
|
||||
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
|
||||
ARRAY_SIZE(mt8127_smt_set), pin, align, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
|
||||
.pins = mtk_pins_mt8127,
|
||||
.npins = ARRAY_SIZE(mtk_pins_mt8127),
|
||||
@ -279,8 +259,14 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
|
||||
.n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
|
||||
.pin_drv_grp = mt8127_pin_drv,
|
||||
.n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
|
||||
.spec_pull_set = mt8127_spec_pull_set,
|
||||
.spec_ies_smt_set = mt8127_ies_smt_set,
|
||||
.spec_ies = mt8127_ies_set,
|
||||
.n_spec_ies = ARRAY_SIZE(mt8127_ies_set),
|
||||
.spec_pupd = mt8127_spec_pupd,
|
||||
.n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd),
|
||||
.spec_smt = mt8127_smt_set,
|
||||
.n_spec_smt = ARRAY_SIZE(mt8127_smt_set),
|
||||
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
|
||||
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
|
||||
.dir_offset = 0x0000,
|
||||
.pullen_offset = 0x0100,
|
||||
.pullsel_offset = 0x0200,
|
||||
@ -303,18 +289,13 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
|
||||
},
|
||||
};
|
||||
|
||||
static int mt8127_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id mt8127_pctrl_match[] = {
|
||||
{ .compatible = "mediatek,mt8127-pinctrl", },
|
||||
{ .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver mtk_pinctrl_driver = {
|
||||
.probe = mt8127_pinctrl_probe,
|
||||
.probe = mtk_pctrl_common_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-mt8127-pinctrl",
|
||||
.of_match_table = mt8127_pctrl_match,
|
||||
|
||||
@ -230,12 +230,14 @@ static const struct mtk_spec_pull_set spec_pupd[] = {
|
||||
SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
|
||||
};
|
||||
|
||||
static int spec_pull_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
static int spec_pull_set(struct regmap *regmap,
|
||||
const struct mtk_pinctrl_devdata *devdata,
|
||||
unsigned int pin, bool isup, unsigned int r1r0)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int reg_pupd, reg_set_r0, reg_set_r1;
|
||||
unsigned int reg_rst_r0, reg_rst_r1;
|
||||
unsigned char align = devdata->port_align;
|
||||
bool find = false;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
|
||||
@ -316,20 +318,13 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
|
||||
},
|
||||
};
|
||||
|
||||
static int mt8135_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id mt8135_pctrl_match[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8135-pinctrl",
|
||||
},
|
||||
{ .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver mtk_pinctrl_driver = {
|
||||
.probe = mt8135_pinctrl_probe,
|
||||
.probe = mtk_pctrl_common_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-mt8135-pinctrl",
|
||||
.of_match_table = mt8135_pctrl_match,
|
||||
|
||||
@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
|
||||
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
|
||||
};
|
||||
|
||||
static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
{
|
||||
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd,
|
||||
ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0);
|
||||
}
|
||||
|
||||
static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
|
||||
MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
|
||||
@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
|
||||
};
|
||||
|
||||
static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, int value, enum pin_config_param arg)
|
||||
{
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set,
|
||||
ARRAY_SIZE(mt8167_ies_set), pin, align, value);
|
||||
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set,
|
||||
ARRAY_SIZE(mt8167_smt_set), pin, align, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
|
||||
.pins = mtk_pins_mt8167,
|
||||
.npins = ARRAY_SIZE(mtk_pins_mt8167),
|
||||
@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
|
||||
.n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
|
||||
.pin_drv_grp = mt8167_pin_drv,
|
||||
.n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
|
||||
.spec_pull_set = mt8167_spec_pull_set,
|
||||
.spec_ies_smt_set = mt8167_ies_smt_set,
|
||||
.spec_ies = mt8167_ies_set,
|
||||
.n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
|
||||
.spec_pupd = mt8167_spec_pupd,
|
||||
.n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
|
||||
.spec_smt = mt8167_smt_set,
|
||||
.n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
|
||||
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
|
||||
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
|
||||
.dir_offset = 0x0000,
|
||||
.pullen_offset = 0x0500,
|
||||
.pullsel_offset = 0x0600,
|
||||
@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
|
||||
},
|
||||
};
|
||||
|
||||
static int mt8167_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id mt8167_pctrl_match[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8167-pinctrl",
|
||||
},
|
||||
{ .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
|
||||
{}
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
|
||||
|
||||
static struct platform_driver mtk_pinctrl_driver = {
|
||||
.probe = mt8167_pinctrl_probe,
|
||||
.probe = mtk_pctrl_common_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-mt8167-pinctrl",
|
||||
.of_match_table = mt8167_pctrl_match,
|
||||
|
||||
@ -61,13 +61,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
|
||||
MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
|
||||
};
|
||||
|
||||
static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
{
|
||||
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
|
||||
ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
|
||||
}
|
||||
|
||||
static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
|
||||
MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
|
||||
@ -174,18 +167,6 @@ static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
|
||||
};
|
||||
|
||||
static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, int value, enum pin_config_param arg)
|
||||
{
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
|
||||
ARRAY_SIZE(mt8173_ies_set), pin, align, value);
|
||||
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
|
||||
ARRAY_SIZE(mt8173_smt_set), pin, align, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
|
||||
/* 0E4E8SR 4/8/12/16 */
|
||||
MTK_DRV_GRP(4, 16, 1, 2, 4),
|
||||
@ -319,8 +300,14 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
|
||||
.n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
|
||||
.pin_drv_grp = mt8173_pin_drv,
|
||||
.n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
|
||||
.spec_pull_set = mt8173_spec_pull_set,
|
||||
.spec_ies_smt_set = mt8173_ies_smt_set,
|
||||
.spec_ies = mt8173_ies_set,
|
||||
.n_spec_ies = ARRAY_SIZE(mt8173_ies_set),
|
||||
.spec_pupd = mt8173_spec_pupd,
|
||||
.n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd),
|
||||
.spec_smt = mt8173_smt_set,
|
||||
.n_spec_smt = ARRAY_SIZE(mt8173_smt_set),
|
||||
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
|
||||
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
|
||||
.dir_offset = 0x0000,
|
||||
.pullen_offset = 0x0100,
|
||||
.pullsel_offset = 0x0200,
|
||||
|
||||
@ -567,22 +567,17 @@ static const struct mtk_pin_soc mt8183_data = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mt8183_pinctrl_of_match[] = {
|
||||
{ .compatible = "mediatek,mt8183-pinctrl", },
|
||||
{ .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int mt8183_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_paris_pinctrl_probe(pdev, &mt8183_data);
|
||||
}
|
||||
|
||||
static struct platform_driver mt8183_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mt8183-pinctrl",
|
||||
.of_match_table = mt8183_pinctrl_of_match,
|
||||
.pm = &mtk_paris_pinctrl_pm_ops,
|
||||
},
|
||||
.probe = mt8183_pinctrl_probe,
|
||||
.probe = mtk_paris_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init mt8183_pinctrl_init(void)
|
||||
|
||||
1267
drivers/pinctrl/mediatek/pinctrl-mt8186.c
Normal file
1267
drivers/pinctrl/mediatek/pinctrl-mt8186.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1381,22 +1381,17 @@ static const struct mtk_pin_soc mt8192_data = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mt8192_pinctrl_of_match[] = {
|
||||
{ .compatible = "mediatek,mt8192-pinctrl", },
|
||||
{ .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int mt8192_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_paris_pinctrl_probe(pdev, &mt8192_data);
|
||||
}
|
||||
|
||||
static struct platform_driver mt8192_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mt8192-pinctrl",
|
||||
.of_match_table = mt8192_pinctrl_of_match,
|
||||
.pm = &mtk_paris_pinctrl_pm_ops,
|
||||
},
|
||||
.probe = mt8192_pinctrl_probe,
|
||||
.probe = mtk_paris_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init mt8192_pinctrl_init(void)
|
||||
|
||||
@ -959,22 +959,17 @@ static const struct mtk_pin_soc mt8195_data = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mt8195_pinctrl_of_match[] = {
|
||||
{ .compatible = "mediatek,mt8195-pinctrl", },
|
||||
{ .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int mt8195_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_paris_pinctrl_probe(pdev, &mt8195_data);
|
||||
}
|
||||
|
||||
static struct platform_driver mt8195_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mt8195-pinctrl",
|
||||
.of_match_table = mt8195_pinctrl_of_match,
|
||||
.pm = &mtk_paris_pinctrl_pm_ops,
|
||||
},
|
||||
.probe = mt8195_pinctrl_probe,
|
||||
.probe = mtk_paris_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init mt8195_pinctrl_init(void)
|
||||
|
||||
@ -416,25 +416,6 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22),
|
||||
};
|
||||
|
||||
static int mt8365_spec_pull_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
{
|
||||
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8365_spec_pupd,
|
||||
ARRAY_SIZE(mt8365_spec_pupd), pin, align, isup, r1r0);
|
||||
}
|
||||
|
||||
static int mt8365_ies_smt_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, int value, enum pin_config_param arg)
|
||||
{
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_ies_set,
|
||||
ARRAY_SIZE(mt8365_ies_set), pin, align, value);
|
||||
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_smt_set,
|
||||
ARRAY_SIZE(mt8365_smt_set), pin, align, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
|
||||
.pins = mtk_pins_mt8365,
|
||||
.npins = ARRAY_SIZE(mtk_pins_mt8365),
|
||||
@ -442,8 +423,14 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
|
||||
.n_grp_cls = ARRAY_SIZE(mt8365_drv_grp),
|
||||
.pin_drv_grp = mt8365_pin_drv,
|
||||
.n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv),
|
||||
.spec_pull_set = mt8365_spec_pull_set,
|
||||
.spec_ies_smt_set = mt8365_ies_smt_set,
|
||||
.spec_ies = mt8365_ies_set,
|
||||
.n_spec_ies = ARRAY_SIZE(mt8365_ies_set),
|
||||
.spec_smt = mt8365_smt_set,
|
||||
.n_spec_smt = ARRAY_SIZE(mt8365_smt_set),
|
||||
.spec_pupd = mt8365_spec_pupd,
|
||||
.n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd),
|
||||
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
|
||||
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
|
||||
.dir_offset = 0x0140,
|
||||
.dout_offset = 0x00A0,
|
||||
.din_offset = 0x0000,
|
||||
@ -469,20 +456,13 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
|
||||
},
|
||||
};
|
||||
|
||||
static int mtk_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_pctrl_init(pdev, &mt8365_pinctrl_data, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id mt8365_pctrl_match[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8365-pinctrl",
|
||||
},
|
||||
{ .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver mtk_pinctrl_driver = {
|
||||
.probe = mtk_pinctrl_probe,
|
||||
.probe = mtk_pctrl_common_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-mt8365-pinctrl",
|
||||
.of_match_table = mt8365_pctrl_match,
|
||||
|
||||
@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
|
||||
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
|
||||
};
|
||||
|
||||
static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
{
|
||||
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
|
||||
ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
|
||||
}
|
||||
|
||||
static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
|
||||
MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
|
||||
@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
|
||||
MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
|
||||
};
|
||||
|
||||
static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
|
||||
unsigned char align, int value, enum pin_config_param arg)
|
||||
{
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
|
||||
ARRAY_SIZE(mt8516_ies_set), pin, align, value);
|
||||
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
|
||||
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
|
||||
ARRAY_SIZE(mt8516_smt_set), pin, align, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
|
||||
.pins = mtk_pins_mt8516,
|
||||
.npins = ARRAY_SIZE(mtk_pins_mt8516),
|
||||
@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
|
||||
.n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
|
||||
.pin_drv_grp = mt8516_pin_drv,
|
||||
.n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
|
||||
.spec_pull_set = mt8516_spec_pull_set,
|
||||
.spec_ies_smt_set = mt8516_ies_smt_set,
|
||||
.spec_ies = mt8516_ies_set,
|
||||
.n_spec_ies = ARRAY_SIZE(mt8516_ies_set),
|
||||
.spec_pupd = mt8516_spec_pupd,
|
||||
.n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd),
|
||||
.spec_smt = mt8516_smt_set,
|
||||
.n_spec_smt = ARRAY_SIZE(mt8516_smt_set),
|
||||
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
|
||||
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
|
||||
.dir_offset = 0x0000,
|
||||
.pullen_offset = 0x0500,
|
||||
.pullsel_offset = 0x0600,
|
||||
@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
|
||||
},
|
||||
};
|
||||
|
||||
static int mt8516_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id mt8516_pctrl_match[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8516-pinctrl",
|
||||
},
|
||||
{ .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data },
|
||||
{}
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
|
||||
|
||||
static struct platform_driver mtk_pinctrl_driver = {
|
||||
.probe = mt8516_pinctrl_probe,
|
||||
.probe = mtk_pctrl_common_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-mt8516-pinctrl",
|
||||
.of_match_table = mt8516_pctrl_match,
|
||||
|
||||
@ -131,7 +131,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
|
||||
*/
|
||||
if (pctl->devdata->spec_ies_smt_set) {
|
||||
return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
|
||||
pin, pctl->devdata->port_align, value, arg);
|
||||
pctl->devdata, pin, value, arg);
|
||||
}
|
||||
|
||||
if (arg == PIN_CONFIG_INPUT_ENABLE)
|
||||
@ -151,10 +151,27 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
|
||||
}
|
||||
|
||||
int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
|
||||
const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
|
||||
unsigned int pin, unsigned char align, int value)
|
||||
const struct mtk_pinctrl_devdata *devdata,
|
||||
unsigned int pin, int value, enum pin_config_param arg)
|
||||
{
|
||||
unsigned int i, reg_addr, bit;
|
||||
const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL;
|
||||
unsigned int i, info_num, reg_addr, bit;
|
||||
|
||||
switch (arg) {
|
||||
case PIN_CONFIG_INPUT_ENABLE:
|
||||
ies_smt_infos = devdata->spec_ies;
|
||||
info_num = devdata->n_spec_ies;
|
||||
break;
|
||||
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
|
||||
ies_smt_infos = devdata->spec_smt;
|
||||
info_num = devdata->n_spec_smt;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (!ies_smt_infos)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < info_num; i++) {
|
||||
if (pin >= ies_smt_infos[i].start &&
|
||||
@ -167,9 +184,9 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
|
||||
return -EINVAL;
|
||||
|
||||
if (value)
|
||||
reg_addr = ies_smt_infos[i].offset + align;
|
||||
reg_addr = ies_smt_infos[i].offset + devdata->port_align;
|
||||
else
|
||||
reg_addr = ies_smt_infos[i].offset + (align << 1);
|
||||
reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1);
|
||||
|
||||
bit = BIT(ies_smt_infos[i].bit);
|
||||
regmap_write(regmap, reg_addr, bit);
|
||||
@ -222,9 +239,8 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
|
||||
}
|
||||
|
||||
int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
|
||||
const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
|
||||
unsigned int info_num, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0)
|
||||
const struct mtk_pinctrl_devdata *devdata,
|
||||
unsigned int pin, bool isup, unsigned int r1r0)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int reg_pupd, reg_set, reg_rst;
|
||||
@ -232,8 +248,11 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
|
||||
const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
|
||||
bool find = false;
|
||||
|
||||
for (i = 0; i < info_num; i++) {
|
||||
if (pin == pupd_infos[i].pin) {
|
||||
if (!devdata->spec_pupd)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < devdata->n_spec_pupd; i++) {
|
||||
if (pin == devdata->spec_pupd[i].pin) {
|
||||
find = true;
|
||||
break;
|
||||
}
|
||||
@ -242,9 +261,9 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
|
||||
if (!find)
|
||||
return -EINVAL;
|
||||
|
||||
spec_pupd_pin = pupd_infos + i;
|
||||
reg_set = spec_pupd_pin->offset + align;
|
||||
reg_rst = spec_pupd_pin->offset + (align << 1);
|
||||
spec_pupd_pin = devdata->spec_pupd + i;
|
||||
reg_set = spec_pupd_pin->offset + devdata->port_align;
|
||||
reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1);
|
||||
|
||||
if (isup)
|
||||
reg_pupd = reg_rst;
|
||||
@ -298,7 +317,8 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
|
||||
*/
|
||||
r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
|
||||
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
|
||||
pin, pctl->devdata->port_align, isup, r1r0);
|
||||
pctl->devdata, pin, isup,
|
||||
r1r0);
|
||||
if (!ret)
|
||||
return 0;
|
||||
}
|
||||
@ -1013,10 +1033,12 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
|
||||
return mtk_eint_do_init(pctl->eint);
|
||||
}
|
||||
|
||||
/* This is used as a common probe function */
|
||||
int mtk_pctrl_init(struct platform_device *pdev,
|
||||
const struct mtk_pinctrl_devdata *data,
|
||||
struct regmap *regmap)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct pinctrl_pin_desc *pins;
|
||||
struct mtk_pinctrl *pctl;
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
@ -1030,37 +1052,35 @@ int mtk_pctrl_init(struct platform_device *pdev,
|
||||
platform_set_drvdata(pdev, pctl);
|
||||
|
||||
prop = of_find_property(np, "pins-are-numbered", NULL);
|
||||
if (!prop) {
|
||||
dev_err(&pdev->dev, "only support pins-are-numbered format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!prop)
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"only support pins-are-numbered format\n");
|
||||
|
||||
node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
|
||||
if (node) {
|
||||
pctl->regmap1 = syscon_node_to_regmap(node);
|
||||
of_node_put(node);
|
||||
if (IS_ERR(pctl->regmap1))
|
||||
return PTR_ERR(pctl->regmap1);
|
||||
} else if (regmap) {
|
||||
pctl->regmap1 = regmap;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
|
||||
return -EINVAL;
|
||||
return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n");
|
||||
}
|
||||
|
||||
/* Only 8135 has two base addr, other SoCs have only one. */
|
||||
node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
|
||||
if (node) {
|
||||
pctl->regmap2 = syscon_node_to_regmap(node);
|
||||
of_node_put(node);
|
||||
if (IS_ERR(pctl->regmap2))
|
||||
return PTR_ERR(pctl->regmap2);
|
||||
}
|
||||
|
||||
pctl->devdata = data;
|
||||
ret = mtk_pctrl_build_state(pdev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "build state failed: %d\n", ret);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "build state failed\n");
|
||||
|
||||
pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
|
||||
GFP_KERNEL);
|
||||
@ -1081,10 +1101,9 @@ int mtk_pctrl_init(struct platform_device *pdev,
|
||||
|
||||
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
|
||||
pctl);
|
||||
if (IS_ERR(pctl->pctl_dev)) {
|
||||
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
|
||||
return PTR_ERR(pctl->pctl_dev);
|
||||
}
|
||||
if (IS_ERR(pctl->pctl_dev))
|
||||
return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev),
|
||||
"Couldn't register pinctrl driver\n");
|
||||
|
||||
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
|
||||
if (!pctl->chip)
|
||||
@ -1118,3 +1137,14 @@ chip_error:
|
||||
gpiochip_remove(pctl->chip);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mtk_pctrl_common_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct mtk_pinctrl_devdata *data = device_get_match_data(dev);
|
||||
|
||||
if (!data)
|
||||
return -ENODEV;
|
||||
|
||||
return mtk_pctrl_init(pdev, data, NULL);
|
||||
}
|
||||
|
||||
@ -193,6 +193,12 @@ struct mtk_eint_offsets {
|
||||
*
|
||||
* @grp_desc: The driving group info.
|
||||
* @pin_drv_grp: The driving group for all pins.
|
||||
* @spec_ies: Special pin setting for input enable
|
||||
* @n_spec_ies: Number of entries in spec_ies
|
||||
* @spec_pupd: Special pull up/down setting
|
||||
* @n_spec_pupd: Number of entries in spec_pupd
|
||||
* @spec_smt: Special pin setting for schmitt
|
||||
* @n_spec_smt: Number of entries in spec_smt
|
||||
* @spec_pull_set: Each SoC may have special pins for pull up/down setting,
|
||||
* these pins' pull setting are very different, they have separate pull
|
||||
* up/down bit, R0 and R1 resistor bit, so they need special pull setting.
|
||||
@ -231,10 +237,18 @@ struct mtk_pinctrl_devdata {
|
||||
unsigned int n_grp_cls;
|
||||
const struct mtk_pin_drv_grp *pin_drv_grp;
|
||||
unsigned int n_pin_drv_grps;
|
||||
int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int arg);
|
||||
int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
|
||||
unsigned char align, int value, enum pin_config_param arg);
|
||||
const struct mtk_pin_ies_smt_set *spec_ies;
|
||||
unsigned int n_spec_ies;
|
||||
const struct mtk_pin_spec_pupd_set_samereg *spec_pupd;
|
||||
unsigned int n_spec_pupd;
|
||||
const struct mtk_pin_ies_smt_set *spec_smt;
|
||||
unsigned int n_spec_smt;
|
||||
int (*spec_pull_set)(struct regmap *regmap,
|
||||
const struct mtk_pinctrl_devdata *devdata,
|
||||
unsigned int pin, bool isup, unsigned int r1r0);
|
||||
int (*spec_ies_smt_set)(struct regmap *reg,
|
||||
const struct mtk_pinctrl_devdata *devdata,
|
||||
unsigned int pin, int value, enum pin_config_param arg);
|
||||
void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
|
||||
unsigned int mode);
|
||||
void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
|
||||
@ -277,14 +291,15 @@ int mtk_pctrl_init(struct platform_device *pdev,
|
||||
const struct mtk_pinctrl_devdata *data,
|
||||
struct regmap *regmap);
|
||||
|
||||
int mtk_pctrl_common_probe(struct platform_device *pdev);
|
||||
|
||||
int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
|
||||
const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
|
||||
unsigned int info_num, unsigned int pin,
|
||||
unsigned char align, bool isup, unsigned int r1r0);
|
||||
const struct mtk_pinctrl_devdata *devdata,
|
||||
unsigned int pin, bool isup, unsigned int r1r0);
|
||||
|
||||
int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
|
||||
const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
|
||||
unsigned int pin, unsigned char align, int value);
|
||||
const struct mtk_pinctrl_devdata *devdata,
|
||||
unsigned int pin, int value, enum pin_config_param arg);
|
||||
|
||||
extern const struct dev_pm_ops mtk_eint_pm_ops;
|
||||
|
||||
|
||||
2186
drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
Normal file
2186
drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -48,6 +48,53 @@ static const char * const mtk_gpio_functions[] = {
|
||||
"func12", "func13", "func14", "func15",
|
||||
};
|
||||
|
||||
/*
|
||||
* This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
|
||||
* and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
|
||||
*
|
||||
* The custom value encodes three hardware bits as follows:
|
||||
*
|
||||
* | Bits |
|
||||
* | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA)
|
||||
* ------------------------------------------------
|
||||
* | x | x | 0 | disabled, use standard drive strength
|
||||
* -------------------------------------
|
||||
* | 0 | 0 | 1 | 125 uA
|
||||
* | 0 | 1 | 1 | 250 uA
|
||||
* | 1 | 0 | 1 | 500 uA
|
||||
* | 1 | 1 | 1 | 1000 uA
|
||||
*/
|
||||
static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
|
||||
|
||||
static int mtk_drv_adv_to_uA(int val)
|
||||
{
|
||||
/* This should never happen. */
|
||||
if (WARN_ON_ONCE(val < 0 || val > 7))
|
||||
return -EINVAL;
|
||||
|
||||
/* Bit 0 simply enables this hardware part */
|
||||
if (!(val & BIT(0)))
|
||||
return -EINVAL;
|
||||
|
||||
return mtk_drv_adv_uA[(val >> 1)];
|
||||
}
|
||||
|
||||
static int mtk_drv_uA_to_adv(int val)
|
||||
{
|
||||
switch (val) {
|
||||
case 125:
|
||||
return 0x1;
|
||||
case 250:
|
||||
return 0x3;
|
||||
case 500:
|
||||
return 0x5;
|
||||
case 1000:
|
||||
return 0x7;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int pin)
|
||||
@ -79,41 +126,34 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
{
|
||||
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
||||
u32 param = pinconf_to_config_param(*config);
|
||||
int pullup, err, reg, ret = 1;
|
||||
int pullup, reg, err = -ENOTSUPP, ret = 1;
|
||||
const struct mtk_pin_desc *desc;
|
||||
|
||||
if (pin >= hw->soc->npins) {
|
||||
err = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
if (pin >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
||||
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
if (hw->soc->bias_get_combo) {
|
||||
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
|
||||
if (err)
|
||||
goto out;
|
||||
if (param == PIN_CONFIG_BIAS_DISABLE) {
|
||||
if (ret == MTK_PUPD_SET_R1R0_00)
|
||||
ret = MTK_DISABLE;
|
||||
} else if (param == PIN_CONFIG_BIAS_PULL_UP) {
|
||||
/* When desire to get pull-up value, return
|
||||
* error if current setting is pull-down
|
||||
*/
|
||||
if (!pullup)
|
||||
err = -EINVAL;
|
||||
} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
|
||||
/* When desire to get pull-down value, return
|
||||
* error if current setting is pull-up
|
||||
*/
|
||||
if (pullup)
|
||||
err = -EINVAL;
|
||||
}
|
||||
} else {
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->bias_get_combo)
|
||||
break;
|
||||
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
|
||||
if (err)
|
||||
break;
|
||||
if (ret == MTK_PUPD_SET_R1R0_00)
|
||||
ret = MTK_DISABLE;
|
||||
if (param == PIN_CONFIG_BIAS_DISABLE) {
|
||||
if (ret != MTK_DISABLE)
|
||||
err = -EINVAL;
|
||||
} else if (param == PIN_CONFIG_BIAS_PULL_UP) {
|
||||
if (!pullup || ret == MTK_DISABLE)
|
||||
err = -EINVAL;
|
||||
} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
|
||||
if (pullup || ret == MTK_DISABLE)
|
||||
err = -EINVAL;
|
||||
}
|
||||
break;
|
||||
case PIN_CONFIG_SLEW_RATE:
|
||||
@ -123,7 +163,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
case PIN_CONFIG_OUTPUT_ENABLE:
|
||||
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
|
||||
if (err)
|
||||
goto out;
|
||||
break;
|
||||
/* CONFIG Current direction return value
|
||||
* ------------- ----------------- ----------------------
|
||||
* OUTPUT_ENABLE output 1 (= HW value)
|
||||
@ -138,23 +178,48 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
|
||||
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
|
||||
if (err)
|
||||
goto out;
|
||||
break;
|
||||
/* return error when in output mode
|
||||
* because schmitt trigger only work in input mode
|
||||
*/
|
||||
if (ret) {
|
||||
err = -EINVAL;
|
||||
goto out;
|
||||
break;
|
||||
}
|
||||
|
||||
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
|
||||
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
if (hw->soc->drive_get)
|
||||
err = hw->soc->drive_get(hw, desc, &ret);
|
||||
else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->drive_get)
|
||||
break;
|
||||
|
||||
if (hw->soc->adv_drive_get) {
|
||||
err = hw->soc->adv_drive_get(hw, desc, &ret);
|
||||
if (!err) {
|
||||
err = mtk_drv_adv_to_uA(ret);
|
||||
if (err > 0) {
|
||||
/* PIN_CONFIG_DRIVE_STRENGTH_UA used */
|
||||
err = -EINVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
err = hw->soc->drive_get(hw, desc, &ret);
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH_UA:
|
||||
if (!hw->soc->adv_drive_get)
|
||||
break;
|
||||
|
||||
err = hw->soc->adv_drive_get(hw, desc, &ret);
|
||||
if (err)
|
||||
break;
|
||||
err = mtk_drv_adv_to_uA(ret);
|
||||
if (err < 0)
|
||||
break;
|
||||
|
||||
ret = err;
|
||||
err = 0;
|
||||
break;
|
||||
case MTK_PIN_CONFIG_TDSEL:
|
||||
case MTK_PIN_CONFIG_RDSEL:
|
||||
@ -164,23 +229,18 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
break;
|
||||
case MTK_PIN_CONFIG_PU_ADV:
|
||||
case MTK_PIN_CONFIG_PD_ADV:
|
||||
if (hw->soc->adv_pull_get) {
|
||||
pullup = param == MTK_PIN_CONFIG_PU_ADV;
|
||||
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
|
||||
} else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->adv_pull_get)
|
||||
break;
|
||||
pullup = param == MTK_PIN_CONFIG_PU_ADV;
|
||||
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
|
||||
break;
|
||||
case MTK_PIN_CONFIG_DRV_ADV:
|
||||
if (hw->soc->adv_drive_get)
|
||||
err = hw->soc->adv_drive_get(hw, desc, &ret);
|
||||
else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->adv_drive_get)
|
||||
break;
|
||||
err = hw->soc->adv_drive_get(hw, desc, &ret);
|
||||
break;
|
||||
default:
|
||||
err = -ENOTSUPP;
|
||||
}
|
||||
|
||||
out:
|
||||
if (!err)
|
||||
*config = pinconf_to_config_packed(param, ret);
|
||||
|
||||
@ -188,38 +248,33 @@ out:
|
||||
}
|
||||
|
||||
static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
enum pin_config_param param,
|
||||
enum pin_config_param arg)
|
||||
enum pin_config_param param, u32 arg)
|
||||
{
|
||||
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct mtk_pin_desc *desc;
|
||||
int err = 0;
|
||||
int err = -ENOTSUPP;
|
||||
u32 reg;
|
||||
|
||||
if (pin >= hw->soc->npins) {
|
||||
err = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
if (pin >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
||||
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
|
||||
|
||||
switch ((u32)param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
if (hw->soc->bias_set_combo)
|
||||
err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
|
||||
else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->bias_set_combo)
|
||||
break;
|
||||
err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
if (hw->soc->bias_set_combo)
|
||||
err = hw->soc->bias_set_combo(hw, desc, 1, arg);
|
||||
else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->bias_set_combo)
|
||||
break;
|
||||
err = hw->soc->bias_set_combo(hw, desc, 1, arg);
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
if (hw->soc->bias_set_combo)
|
||||
err = hw->soc->bias_set_combo(hw, desc, 0, arg);
|
||||
else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->bias_set_combo)
|
||||
break;
|
||||
err = hw->soc->bias_set_combo(hw, desc, 0, arg);
|
||||
break;
|
||||
case PIN_CONFIG_OUTPUT_ENABLE:
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
|
||||
@ -228,7 +283,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
* does not have SMT control
|
||||
*/
|
||||
if (err != -ENOTSUPP)
|
||||
goto err;
|
||||
break;
|
||||
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
|
||||
MTK_OUTPUT);
|
||||
@ -237,7 +292,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
/* regard all non-zero value as enable */
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
|
||||
if (err)
|
||||
goto err;
|
||||
break;
|
||||
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
|
||||
MTK_INPUT);
|
||||
@ -250,7 +305,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
|
||||
arg);
|
||||
if (err)
|
||||
goto err;
|
||||
break;
|
||||
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
|
||||
MTK_OUTPUT);
|
||||
@ -262,15 +317,23 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
*/
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
|
||||
if (err)
|
||||
goto err;
|
||||
break;
|
||||
|
||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
if (hw->soc->drive_set)
|
||||
err = hw->soc->drive_set(hw, desc, arg);
|
||||
else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->drive_set)
|
||||
break;
|
||||
err = hw->soc->drive_set(hw, desc, arg);
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH_UA:
|
||||
if (!hw->soc->adv_drive_set)
|
||||
break;
|
||||
|
||||
err = mtk_drv_uA_to_adv(arg);
|
||||
if (err < 0)
|
||||
break;
|
||||
err = hw->soc->adv_drive_set(hw, desc, err);
|
||||
break;
|
||||
case MTK_PIN_CONFIG_TDSEL:
|
||||
case MTK_PIN_CONFIG_RDSEL:
|
||||
@ -280,26 +343,19 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
break;
|
||||
case MTK_PIN_CONFIG_PU_ADV:
|
||||
case MTK_PIN_CONFIG_PD_ADV:
|
||||
if (hw->soc->adv_pull_set) {
|
||||
bool pullup;
|
||||
|
||||
pullup = param == MTK_PIN_CONFIG_PU_ADV;
|
||||
err = hw->soc->adv_pull_set(hw, desc, pullup,
|
||||
arg);
|
||||
} else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->adv_pull_set)
|
||||
break;
|
||||
err = hw->soc->adv_pull_set(hw, desc,
|
||||
(param == MTK_PIN_CONFIG_PU_ADV),
|
||||
arg);
|
||||
break;
|
||||
case MTK_PIN_CONFIG_DRV_ADV:
|
||||
if (hw->soc->adv_drive_set)
|
||||
err = hw->soc->adv_drive_set(hw, desc, arg);
|
||||
else
|
||||
err = -ENOTSUPP;
|
||||
if (!hw->soc->adv_drive_set)
|
||||
break;
|
||||
err = hw->soc->adv_drive_set(hw, desc, arg);
|
||||
break;
|
||||
default:
|
||||
err = -ENOTSUPP;
|
||||
}
|
||||
|
||||
err:
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -586,6 +642,9 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
|
||||
if (gpio >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
||||
if (mtk_is_virt_gpio(hw, gpio))
|
||||
return -EINVAL;
|
||||
|
||||
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
||||
pinmux = mtk_pctrl_get_pinmux(hw, gpio);
|
||||
if (pinmux >= hw->soc->nfuncs)
|
||||
@ -639,14 +698,10 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
|
||||
pullen,
|
||||
pullup);
|
||||
|
||||
if (r1 != -1) {
|
||||
len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n",
|
||||
r1, r0);
|
||||
} else if (rsel != -1) {
|
||||
len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel);
|
||||
} else {
|
||||
len += scnprintf(buf + len, buf_len - len, "\n");
|
||||
}
|
||||
if (r1 != -1)
|
||||
len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
|
||||
else if (rsel != -1)
|
||||
len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
|
||||
|
||||
return len;
|
||||
}
|
||||
@ -737,10 +792,10 @@ static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct mtk_pinctrl_group *grp = &hw->groups[group];
|
||||
|
||||
*config = hw->groups[group].config;
|
||||
|
||||
return 0;
|
||||
/* One pin per group only */
|
||||
return mtk_pinconf_get(pctldev, grp->pin, config);
|
||||
}
|
||||
|
||||
static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
|
||||
@ -748,6 +803,8 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
|
||||
{
|
||||
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct mtk_pinctrl_group *grp = &hw->groups[group];
|
||||
bool drive_strength_uA_found = false;
|
||||
bool adv_drve_strength_found = false;
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < num_configs; i++) {
|
||||
@ -757,9 +814,21 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
grp->config = configs[i];
|
||||
if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
|
||||
drive_strength_uA_found = true;
|
||||
if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
|
||||
adv_drve_strength_found = true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable advanced drive strength mode if drive-strength-microamp
|
||||
* is not set. However, mediatek,drive-strength-adv takes precedence
|
||||
* as its value can explicitly request the mode be enabled or not.
|
||||
*/
|
||||
if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
|
||||
!adv_drve_strength_found)
|
||||
hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -952,9 +1021,9 @@ static int mtk_pctrl_build_state(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mtk_paris_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct mtk_pin_soc *soc)
|
||||
int mtk_paris_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct pinctrl_pin_desc *pins;
|
||||
struct mtk_pinctrl *hw;
|
||||
int err, i;
|
||||
@ -964,14 +1033,16 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, hw);
|
||||
hw->soc = soc;
|
||||
|
||||
hw->soc = device_get_match_data(dev);
|
||||
if (!hw->soc)
|
||||
return -ENOENT;
|
||||
|
||||
hw->dev = &pdev->dev;
|
||||
|
||||
if (!hw->soc->nbase_names) {
|
||||
dev_err(&pdev->dev,
|
||||
if (!hw->soc->nbase_names)
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"SoC should be assigned at least one register base\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
|
||||
sizeof(*hw->base), GFP_KERNEL);
|
||||
@ -988,7 +1059,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
|
||||
hw->nbase = hw->soc->nbase_names;
|
||||
|
||||
if (of_find_property(hw->dev->of_node,
|
||||
"mediatek,rsel_resistance_in_si_unit", NULL))
|
||||
"mediatek,rsel-resistance-in-si-unit", NULL))
|
||||
hw->rsel_si_unit = true;
|
||||
else
|
||||
hw->rsel_si_unit = false;
|
||||
@ -996,10 +1067,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
|
||||
spin_lock_init(&hw->lock);
|
||||
|
||||
err = mtk_pctrl_build_state(pdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "build state failed: %d\n", err);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "build state failed\n");
|
||||
|
||||
/* Copy from internal struct mtk_pin_desc to register to the core */
|
||||
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
|
||||
@ -1037,10 +1106,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
|
||||
|
||||
/* Build gpiochip should be after pinctrl_enable is done */
|
||||
err = mtk_build_gpiochip(hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
|
||||
return err;
|
||||
}
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
|
||||
|
||||
platform_set_drvdata(pdev, hw);
|
||||
|
||||
|
||||
@ -57,8 +57,7 @@
|
||||
id##_funcs, \
|
||||
}
|
||||
|
||||
int mtk_paris_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct mtk_pin_soc *soc);
|
||||
int mtk_paris_pinctrl_probe(struct platform_device *pdev);
|
||||
|
||||
ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
|
||||
unsigned int gpio, char *buf, unsigned int bufLen);
|
||||
|
||||
@ -61,4 +61,10 @@ config PINCTRL_MESON_A1
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
|
||||
config PINCTRL_MESON_S4
|
||||
tristate "Meson s4 Soc pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
|
||||
endif
|
||||
|
||||
@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
|
||||
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
|
||||
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
|
||||
obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
|
||||
obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o
|
||||
|
||||
@ -283,6 +283,8 @@ static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 };
|
||||
static const unsigned int pwm_e_pins[] = { GPIOX_16 };
|
||||
|
||||
/* pwm_f */
|
||||
static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 };
|
||||
static const unsigned int pwm_f_a_pins[] = { GPIOA_11 };
|
||||
static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
|
||||
static const unsigned int pwm_f_h_pins[] = { GPIOH_5 };
|
||||
|
||||
@ -618,6 +620,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = {
|
||||
GROUP(tdm_c_dout2_z, 4),
|
||||
GROUP(tdm_c_dout3_z, 4),
|
||||
GROUP(mclk1_z, 4),
|
||||
GROUP(pwm_f_z, 5),
|
||||
|
||||
/* bank GPIOX */
|
||||
GROUP(sdio_d0, 1),
|
||||
@ -768,6 +771,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = {
|
||||
GROUP(tdm_c_dout3_a, 2),
|
||||
GROUP(mclk0_a, 1),
|
||||
GROUP(mclk1_a, 2),
|
||||
GROUP(pwm_f_a, 3),
|
||||
};
|
||||
|
||||
/* uart_ao_a */
|
||||
@ -1069,7 +1073,7 @@ static const char * const pwm_e_groups[] = {
|
||||
};
|
||||
|
||||
static const char * const pwm_f_groups[] = {
|
||||
"pwm_f_x", "pwm_f_h",
|
||||
"pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h",
|
||||
};
|
||||
|
||||
static const char * const cec_ao_a_h_groups[] = {
|
||||
|
||||
1232
drivers/pinctrl/meson/pinctrl-meson-s4.c
Normal file
1232
drivers/pinctrl/meson/pinctrl-meson-s4.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1883,8 +1883,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
prcm_np = of_parse_phandle(np, "prcm", 0);
|
||||
if (prcm_np)
|
||||
if (prcm_np) {
|
||||
npct->prcm_base = of_iomap(prcm_np, 0);
|
||||
of_node_put(prcm_np);
|
||||
}
|
||||
if (!npct->prcm_base) {
|
||||
if (version == PINCTRL_NMK_STN8815) {
|
||||
dev_info(&pdev->dev,
|
||||
|
||||
@ -1,4 +1,24 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
config PINCTRL_WPCM450
|
||||
tristate "Pinctrl and GPIO driver for Nuvoton WPCM450"
|
||||
depends on ARCH_WPCM450 || COMPILE_TEST
|
||||
depends on OF
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GPIOLIB
|
||||
select GPIO_GENERIC
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Say Y or M here to enable pin controller and GPIO support for
|
||||
the Nuvoton WPCM450 SoC. This is strongly recommended when
|
||||
building a kernel that will run on this chip.
|
||||
|
||||
If this driver is compiled as a module, it will be named
|
||||
pinctrl-wpcm450.
|
||||
|
||||
config PINCTRL_NPCM7XX
|
||||
bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX"
|
||||
depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# Nuvoton pinctrl support
|
||||
|
||||
obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o
|
||||
obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
|
||||
|
||||
@ -216,7 +216,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc)
|
||||
struct gpio_chip *gc;
|
||||
struct irq_chip *chip;
|
||||
struct npcm7xx_gpio *bank;
|
||||
u32 sts, en, bit;
|
||||
unsigned long sts, en, bit;
|
||||
|
||||
gc = irq_desc_get_handler_data(desc);
|
||||
bank = gpiochip_get_data(gc);
|
||||
@ -225,11 +225,11 @@ static void npcmgpio_irq_handler(struct irq_desc *desc)
|
||||
chained_irq_enter(chip, desc);
|
||||
sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
|
||||
en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
|
||||
dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts,
|
||||
dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,
|
||||
en);
|
||||
|
||||
sts &= en;
|
||||
for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
|
||||
for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK)
|
||||
generic_handle_domain_irq(gc->irq.domain, bit);
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
@ -894,7 +894,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = {
|
||||
};
|
||||
|
||||
#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
|
||||
[a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
|
||||
[a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
|
||||
.fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
|
||||
.fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
|
||||
.flag = k }
|
||||
@ -904,7 +904,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = {
|
||||
#define DRIVE_STRENGTH_HI_SHIFT 12
|
||||
#define DRIVE_STRENGTH_MASK 0x0000FF00
|
||||
|
||||
#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
|
||||
#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
|
||||
((hi) << DRIVE_STRENGTH_HI_SHIFT))
|
||||
#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
|
||||
#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
|
||||
@ -924,31 +924,31 @@ struct npcm7xx_pincfg {
|
||||
static const struct npcm7xx_pincfg pincfg[] = {
|
||||
/* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
|
||||
NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
|
||||
@ -964,12 +964,12 @@ static const struct npcm7xx_pincfg pincfg[] = {
|
||||
NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO),
|
||||
NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
|
||||
NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
|
||||
NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
|
||||
NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
|
||||
NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
|
||||
NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
|
||||
NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
|
||||
NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
|
||||
NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
|
||||
@ -979,8 +979,8 @@ static const struct npcm7xx_pincfg pincfg[] = {
|
||||
NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
|
||||
NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
|
||||
NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
|
||||
NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
|
||||
NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
|
||||
@ -1003,19 +1003,19 @@ static const struct npcm7xx_pincfg pincfg[] = {
|
||||
NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
|
||||
NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
|
||||
NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
|
||||
NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
|
||||
NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
|
||||
@ -1061,34 +1061,34 @@ static const struct npcm7xx_pincfg pincfg[] = {
|
||||
NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
|
||||
NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
|
||||
NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
|
||||
NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
|
||||
NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
|
||||
NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
|
||||
@ -1101,25 +1101,25 @@ static const struct npcm7xx_pincfg pincfg[] = {
|
||||
NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)),
|
||||
NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
|
||||
NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),
|
||||
NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
|
||||
|
||||
NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
|
||||
NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
|
||||
NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
|
||||
@ -1130,11 +1130,11 @@ static const struct npcm7xx_pincfg pincfg[] = {
|
||||
NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
|
||||
@ -1146,20 +1146,20 @@ static const struct npcm7xx_pincfg pincfg[] = {
|
||||
NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
|
||||
NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
|
||||
NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
|
||||
NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
|
||||
|
||||
NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
|
||||
NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)),
|
||||
NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
|
||||
NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
|
||||
NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
|
||||
NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
|
||||
NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
|
||||
NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
|
||||
@ -1560,7 +1560,7 @@ static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(npcm7xx_groups));
|
||||
dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));
|
||||
return ARRAY_SIZE(npcm7xx_groups);
|
||||
}
|
||||
|
||||
|
||||
1151
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
Normal file
1151
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -30,10 +30,10 @@ static const struct pin_config_item conf_items[] = {
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "ohms", true),
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
|
||||
"input bias pull to pin specific state", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),
|
||||
"input bias pull to pin specific state", "ohms", true),
|
||||
PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "ohms", true),
|
||||
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),
|
||||
|
||||
@ -1045,7 +1045,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
|
||||
const char **group_names;
|
||||
const struct of_device_id *match;
|
||||
int i, ret;
|
||||
struct resource *res;
|
||||
struct atmel_pioctrl *atmel_pioctrl;
|
||||
const struct atmel_pioctrl_data *atmel_pioctrl_data;
|
||||
|
||||
@ -1164,16 +1163,15 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
|
||||
|
||||
/* There is one controller but each bank has its own irq line. */
|
||||
for (i = 0; i < atmel_pioctrl->nbanks; i++) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
|
||||
if (!res) {
|
||||
dev_err(dev, "missing irq resource for group %c\n",
|
||||
ret = platform_get_irq(pdev, i);
|
||||
if (ret < 0) {
|
||||
dev_dbg(dev, "missing irq resource for group %c\n",
|
||||
'A' + i);
|
||||
return -EINVAL;
|
||||
return ret;
|
||||
}
|
||||
atmel_pioctrl->irqs[i] = res->start;
|
||||
irq_set_chained_handler_and_data(res->start,
|
||||
atmel_gpio_irq_handler, atmel_pioctrl);
|
||||
dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
|
||||
atmel_pioctrl->irqs[i] = ret;
|
||||
irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);
|
||||
dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
|
||||
}
|
||||
|
||||
atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
|
||||
|
||||
@ -119,6 +119,8 @@ struct ingenic_chip_info {
|
||||
unsigned int num_functions;
|
||||
|
||||
const u32 *pull_ups, *pull_downs;
|
||||
|
||||
const struct regmap_access_table *access_table;
|
||||
};
|
||||
|
||||
struct ingenic_pinctrl {
|
||||
@ -2179,6 +2181,17 @@ static const struct function_desc x1000_functions[] = {
|
||||
{ "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
|
||||
};
|
||||
|
||||
static const struct regmap_range x1000_access_ranges[] = {
|
||||
regmap_reg_range(0x000, 0x400 - 4),
|
||||
regmap_reg_range(0x700, 0x800 - 4),
|
||||
};
|
||||
|
||||
/* shared with X1500 */
|
||||
static const struct regmap_access_table x1000_access_table = {
|
||||
.yes_ranges = x1000_access_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info x1000_chip_info = {
|
||||
.num_chips = 4,
|
||||
.reg_offset = 0x100,
|
||||
@ -2189,6 +2202,7 @@ static const struct ingenic_chip_info x1000_chip_info = {
|
||||
.num_functions = ARRAY_SIZE(x1000_functions),
|
||||
.pull_ups = x1000_pull_ups,
|
||||
.pull_downs = x1000_pull_downs,
|
||||
.access_table = &x1000_access_table,
|
||||
};
|
||||
|
||||
static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
|
||||
@ -2300,6 +2314,7 @@ static const struct ingenic_chip_info x1500_chip_info = {
|
||||
.num_functions = ARRAY_SIZE(x1500_functions),
|
||||
.pull_ups = x1000_pull_ups,
|
||||
.pull_downs = x1000_pull_downs,
|
||||
.access_table = &x1000_access_table,
|
||||
};
|
||||
|
||||
static const u32 x1830_pull_ups[4] = {
|
||||
@ -2506,6 +2521,16 @@ static const struct function_desc x1830_functions[] = {
|
||||
{ "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
|
||||
};
|
||||
|
||||
static const struct regmap_range x1830_access_ranges[] = {
|
||||
regmap_reg_range(0x0000, 0x4000 - 4),
|
||||
regmap_reg_range(0x7000, 0x8000 - 4),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table x1830_access_table = {
|
||||
.yes_ranges = x1830_access_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info x1830_chip_info = {
|
||||
.num_chips = 4,
|
||||
.reg_offset = 0x1000,
|
||||
@ -2516,6 +2541,7 @@ static const struct ingenic_chip_info x1830_chip_info = {
|
||||
.num_functions = ARRAY_SIZE(x1830_functions),
|
||||
.pull_ups = x1830_pull_ups,
|
||||
.pull_downs = x1830_pull_downs,
|
||||
.access_table = &x1830_access_table,
|
||||
};
|
||||
|
||||
static const u32 x2000_pull_ups[5] = {
|
||||
@ -2969,6 +2995,17 @@ static const struct function_desc x2000_functions[] = {
|
||||
{ "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
|
||||
};
|
||||
|
||||
static const struct regmap_range x2000_access_ranges[] = {
|
||||
regmap_reg_range(0x000, 0x500 - 4),
|
||||
regmap_reg_range(0x700, 0x800 - 4),
|
||||
};
|
||||
|
||||
/* shared with X2100 */
|
||||
static const struct regmap_access_table x2000_access_table = {
|
||||
.yes_ranges = x2000_access_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
|
||||
};
|
||||
|
||||
static const struct ingenic_chip_info x2000_chip_info = {
|
||||
.num_chips = 5,
|
||||
.reg_offset = 0x100,
|
||||
@ -2979,6 +3016,7 @@ static const struct ingenic_chip_info x2000_chip_info = {
|
||||
.num_functions = ARRAY_SIZE(x2000_functions),
|
||||
.pull_ups = x2000_pull_ups,
|
||||
.pull_downs = x2000_pull_downs,
|
||||
.access_table = &x2000_access_table,
|
||||
};
|
||||
|
||||
static const u32 x2100_pull_ups[5] = {
|
||||
@ -3189,6 +3227,7 @@ static const struct ingenic_chip_info x2100_chip_info = {
|
||||
.num_functions = ARRAY_SIZE(x2100_functions),
|
||||
.pull_ups = x2100_pull_ups,
|
||||
.pull_downs = x2100_pull_downs,
|
||||
.access_table = &x2000_access_table,
|
||||
};
|
||||
|
||||
static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
|
||||
@ -4168,7 +4207,12 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(base);
|
||||
|
||||
regmap_config = ingenic_pinctrl_regmap_config;
|
||||
regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset;
|
||||
if (chip_info->access_table) {
|
||||
regmap_config.rd_table = chip_info->access_table;
|
||||
regmap_config.wr_table = chip_info->access_table;
|
||||
} else {
|
||||
regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
|
||||
}
|
||||
|
||||
jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config);
|
||||
if (IS_ERR(jzpc->map)) {
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <linux/property.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "pinconf.h"
|
||||
@ -63,11 +64,13 @@ struct sgpio_properties {
|
||||
#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
|
||||
|
||||
#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
|
||||
#define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
|
||||
#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
|
||||
#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
|
||||
#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
|
||||
|
||||
#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
|
||||
#define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
|
||||
#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
|
||||
#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
|
||||
#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
|
||||
@ -116,6 +119,9 @@ struct sgpio_priv {
|
||||
u32 clock;
|
||||
struct regmap *regs;
|
||||
const struct sgpio_properties *properties;
|
||||
spinlock_t lock;
|
||||
/* protects the config register and single shot mode */
|
||||
struct mutex poll_lock;
|
||||
};
|
||||
|
||||
struct sgpio_port_addr {
|
||||
@ -166,12 +172,11 @@ static void sgpio_writel(struct sgpio_priv *priv,
|
||||
static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
|
||||
u32 rno, u32 off, u32 clear, u32 set)
|
||||
{
|
||||
u32 val = sgpio_readl(priv, rno, off);
|
||||
u32 addr = sgpio_get_addr(priv, rno, off);
|
||||
int ret;
|
||||
|
||||
val &= ~clear;
|
||||
val |= set;
|
||||
|
||||
sgpio_writel(priv, val, rno, off);
|
||||
ret = regmap_update_bits(priv->regs, addr, clear | set, set);
|
||||
WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
|
||||
}
|
||||
|
||||
static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
|
||||
@ -224,12 +229,64 @@ static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
|
||||
sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
|
||||
}
|
||||
|
||||
static void sgpio_output_set(struct sgpio_priv *priv,
|
||||
struct sgpio_port_addr *addr,
|
||||
int value)
|
||||
static int sgpio_single_shot(struct sgpio_priv *priv)
|
||||
{
|
||||
u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
|
||||
int ret, ret2;
|
||||
u32 ctrl;
|
||||
unsigned int single_shot;
|
||||
unsigned int auto_repeat;
|
||||
|
||||
switch (priv->properties->arch) {
|
||||
case SGPIO_ARCH_LUTON:
|
||||
/* not supported for now */
|
||||
return 0;
|
||||
case SGPIO_ARCH_OCELOT:
|
||||
single_shot = SGPIO_OCELOT_SINGLE_SHOT;
|
||||
auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
|
||||
break;
|
||||
case SGPIO_ARCH_SPARX5:
|
||||
single_shot = SGPIO_SPARX5_SINGLE_SHOT;
|
||||
auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Trigger immediate burst. This only works when auto repeat is turned
|
||||
* off. Otherwise, the single shot bit will never be cleared by the
|
||||
* hardware. Measurements showed that an update might take as long as
|
||||
* the burst gap. On a LAN9668 this is about 50ms for the largest
|
||||
* setting.
|
||||
* After the manual burst, reenable the auto repeat mode again.
|
||||
*/
|
||||
mutex_lock(&priv->poll_lock);
|
||||
ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
|
||||
single_shot);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
|
||||
!(ctrl & single_shot), 100, 60000);
|
||||
|
||||
/* reenable auto repeat mode even if there was an error */
|
||||
ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
|
||||
out:
|
||||
mutex_unlock(&priv->poll_lock);
|
||||
|
||||
return ret ?: ret2;
|
||||
}
|
||||
|
||||
static int sgpio_output_set(struct sgpio_priv *priv,
|
||||
struct sgpio_port_addr *addr,
|
||||
int value)
|
||||
{
|
||||
unsigned int bit = SGPIO_SRC_BITS * addr->bit;
|
||||
u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
|
||||
bool changed;
|
||||
u32 clr, set;
|
||||
int ret;
|
||||
|
||||
switch (priv->properties->arch) {
|
||||
case SGPIO_ARCH_LUTON:
|
||||
@ -245,9 +302,21 @@ static void sgpio_output_set(struct sgpio_priv *priv,
|
||||
set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
return -EINVAL;
|
||||
}
|
||||
sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);
|
||||
|
||||
ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
|
||||
&changed);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (changed) {
|
||||
ret = sgpio_single_shot(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sgpio_output_get(struct sgpio_priv *priv,
|
||||
@ -333,7 +402,7 @@ static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
case PIN_CONFIG_OUTPUT:
|
||||
if (bank->is_input)
|
||||
return -EINVAL;
|
||||
sgpio_output_set(priv, &addr, arg);
|
||||
err = sgpio_output_set(priv, &addr, arg);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -473,9 +542,7 @@ static int microchip_sgpio_direction_output(struct gpio_chip *gc,
|
||||
|
||||
sgpio_pin_to_addr(priv, gpio, &addr);
|
||||
|
||||
sgpio_output_set(priv, &addr, value);
|
||||
|
||||
return 0;
|
||||
return sgpio_output_set(priv, &addr, value);
|
||||
}
|
||||
|
||||
static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
|
||||
@ -575,10 +642,13 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,
|
||||
struct sgpio_bank *bank = gpiochip_get_data(chip);
|
||||
unsigned int gpio = irqd_to_hwirq(data);
|
||||
struct sgpio_port_addr addr;
|
||||
unsigned long flags;
|
||||
u32 ena;
|
||||
|
||||
sgpio_pin_to_addr(bank->priv, gpio, &addr);
|
||||
|
||||
spin_lock_irqsave(&bank->priv->lock, flags);
|
||||
|
||||
/* Disable interrupt while changing type */
|
||||
ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
|
||||
sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
|
||||
@ -595,6 +665,8 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,
|
||||
|
||||
/* Possibly re-enable interrupts */
|
||||
sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
|
||||
|
||||
spin_unlock_irqrestore(&bank->priv->lock, flags);
|
||||
}
|
||||
|
||||
static void microchip_sgpio_irq_setreg(struct irq_data *data,
|
||||
@ -626,7 +698,14 @@ static void microchip_sgpio_irq_unmask(struct irq_data *data)
|
||||
|
||||
static void microchip_sgpio_irq_ack(struct irq_data *data)
|
||||
{
|
||||
microchip_sgpio_irq_setreg(data, REG_INT_ACK, false);
|
||||
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
|
||||
struct sgpio_bank *bank = gpiochip_get_data(chip);
|
||||
unsigned int gpio = irqd_to_hwirq(data);
|
||||
struct sgpio_port_addr addr;
|
||||
|
||||
sgpio_pin_to_addr(bank->priv, gpio, &addr);
|
||||
|
||||
sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
|
||||
}
|
||||
|
||||
static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
|
||||
@ -774,6 +853,7 @@ static int microchip_sgpio_register_bank(struct device *dev,
|
||||
gc->of_gpio_n_cells = 3;
|
||||
gc->base = -1;
|
||||
gc->ngpio = ngpios;
|
||||
gc->can_sleep = !bank->is_input;
|
||||
|
||||
if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
|
||||
int irq = fwnode_irq_get(fwnode, 0);
|
||||
@ -833,6 +913,8 @@ static int microchip_sgpio_probe(struct platform_device *pdev)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = dev;
|
||||
spin_lock_init(&priv->lock);
|
||||
mutex_init(&priv->poll_lock);
|
||||
|
||||
reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
|
||||
if (IS_ERR(reset))
|
||||
|
||||
@ -695,6 +695,98 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = {
|
||||
JAGUAR2_PIN(63),
|
||||
};
|
||||
|
||||
#define SERVALT_P(p, f0, f1, f2) \
|
||||
static struct ocelot_pin_caps servalt_pin_##p = { \
|
||||
.pin = p, \
|
||||
.functions = { \
|
||||
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
|
||||
}, \
|
||||
}
|
||||
|
||||
SERVALT_P(0, SG0, NONE, NONE);
|
||||
SERVALT_P(1, SG0, NONE, NONE);
|
||||
SERVALT_P(2, SG0, NONE, NONE);
|
||||
SERVALT_P(3, SG0, NONE, NONE);
|
||||
SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
|
||||
SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
|
||||
SERVALT_P(6, UART, NONE, NONE);
|
||||
SERVALT_P(7, UART, NONE, NONE);
|
||||
SERVALT_P(8, SI, SFP, TWI_SCL_M);
|
||||
SERVALT_P(9, PCI_WAKE, SFP, SI);
|
||||
SERVALT_P(10, PTP0, SFP, TWI_SCL_M);
|
||||
SERVALT_P(11, PTP1, SFP, TWI_SCL_M);
|
||||
SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
|
||||
SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
|
||||
SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
|
||||
SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
|
||||
SERVALT_P(16, TACHO, SFP, SI);
|
||||
SERVALT_P(17, PWM, NONE, TWI_SCL_M);
|
||||
SERVALT_P(18, PTP2, SFP, SI);
|
||||
SERVALT_P(19, PTP3, SFP, SI);
|
||||
SERVALT_P(20, UART2, SFP, SI);
|
||||
SERVALT_P(21, UART2, NONE, NONE);
|
||||
SERVALT_P(22, MIIM, SFP, TWI2);
|
||||
SERVALT_P(23, MIIM, SFP, TWI2);
|
||||
SERVALT_P(24, TWI, NONE, NONE);
|
||||
SERVALT_P(25, TWI, SFP, TWI_SCL_M);
|
||||
SERVALT_P(26, TWI_SCL_M, SFP, SI);
|
||||
SERVALT_P(27, TWI_SCL_M, SFP, SI);
|
||||
SERVALT_P(28, TWI_SCL_M, SFP, SI);
|
||||
SERVALT_P(29, TWI_SCL_M, NONE, NONE);
|
||||
SERVALT_P(30, TWI_SCL_M, NONE, NONE);
|
||||
SERVALT_P(31, TWI_SCL_M, NONE, NONE);
|
||||
SERVALT_P(32, TWI_SCL_M, NONE, NONE);
|
||||
SERVALT_P(33, RCVRD_CLK, NONE, NONE);
|
||||
SERVALT_P(34, RCVRD_CLK, NONE, NONE);
|
||||
SERVALT_P(35, RCVRD_CLK, NONE, NONE);
|
||||
SERVALT_P(36, RCVRD_CLK, NONE, NONE);
|
||||
|
||||
#define SERVALT_PIN(n) { \
|
||||
.number = n, \
|
||||
.name = "GPIO_"#n, \
|
||||
.drv_data = &servalt_pin_##n \
|
||||
}
|
||||
|
||||
static const struct pinctrl_pin_desc servalt_pins[] = {
|
||||
SERVALT_PIN(0),
|
||||
SERVALT_PIN(1),
|
||||
SERVALT_PIN(2),
|
||||
SERVALT_PIN(3),
|
||||
SERVALT_PIN(4),
|
||||
SERVALT_PIN(5),
|
||||
SERVALT_PIN(6),
|
||||
SERVALT_PIN(7),
|
||||
SERVALT_PIN(8),
|
||||
SERVALT_PIN(9),
|
||||
SERVALT_PIN(10),
|
||||
SERVALT_PIN(11),
|
||||
SERVALT_PIN(12),
|
||||
SERVALT_PIN(13),
|
||||
SERVALT_PIN(14),
|
||||
SERVALT_PIN(15),
|
||||
SERVALT_PIN(16),
|
||||
SERVALT_PIN(17),
|
||||
SERVALT_PIN(18),
|
||||
SERVALT_PIN(19),
|
||||
SERVALT_PIN(20),
|
||||
SERVALT_PIN(21),
|
||||
SERVALT_PIN(22),
|
||||
SERVALT_PIN(23),
|
||||
SERVALT_PIN(24),
|
||||
SERVALT_PIN(25),
|
||||
SERVALT_PIN(26),
|
||||
SERVALT_PIN(27),
|
||||
SERVALT_PIN(28),
|
||||
SERVALT_PIN(29),
|
||||
SERVALT_PIN(30),
|
||||
SERVALT_PIN(31),
|
||||
SERVALT_PIN(32),
|
||||
SERVALT_PIN(33),
|
||||
SERVALT_PIN(34),
|
||||
SERVALT_PIN(35),
|
||||
SERVALT_PIN(36),
|
||||
};
|
||||
|
||||
#define SPARX5_P(p, f0, f1, f2) \
|
||||
static struct ocelot_pin_caps sparx5_pin_##p = { \
|
||||
.pin = p, \
|
||||
@ -1497,6 +1589,15 @@ static struct pinctrl_desc jaguar2_desc = {
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc servalt_desc = {
|
||||
.name = "servalt-pinctrl",
|
||||
.pins = servalt_pins,
|
||||
.npins = ARRAY_SIZE(servalt_pins),
|
||||
.pctlops = &ocelot_pctl_ops,
|
||||
.pmxops = &ocelot_pmx_ops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc sparx5_desc = {
|
||||
.name = "sparx5-pinctrl",
|
||||
.pins = sparx5_pins,
|
||||
@ -1750,8 +1851,8 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
|
||||
gc->base = -1;
|
||||
gc->label = "ocelot-gpio";
|
||||
|
||||
irq = irq_of_parse_and_map(gc->of_node, 0);
|
||||
if (irq) {
|
||||
irq = platform_get_irq_optional(pdev, 0);
|
||||
if (irq > 0) {
|
||||
girq = &gc->irq;
|
||||
girq->chip = &ocelot_irqchip;
|
||||
girq->parent_handler = ocelot_irq_handler;
|
||||
@ -1774,6 +1875,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = {
|
||||
{ .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
|
||||
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
|
||||
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
|
||||
{ .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
|
||||
{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
|
||||
{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
|
||||
{},
|
||||
@ -1788,9 +1890,10 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 32,
|
||||
.name = "pincfg",
|
||||
};
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(base)) {
|
||||
dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
|
||||
return NULL;
|
||||
|
||||
@ -2693,6 +2693,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
|
||||
node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
if (node) {
|
||||
info->regmap_base = syscon_node_to_regmap(node);
|
||||
of_node_put(node);
|
||||
if (IS_ERR(info->regmap_base))
|
||||
return PTR_ERR(info->regmap_base);
|
||||
} else {
|
||||
@ -2725,6 +2726,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
|
||||
node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||
if (node) {
|
||||
info->regmap_pmu = syscon_node_to_regmap(node);
|
||||
of_node_put(node);
|
||||
if (IS_ERR(info->regmap_pmu))
|
||||
return PTR_ERR(info->regmap_pmu);
|
||||
}
|
||||
|
||||
@ -1026,7 +1026,7 @@ static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
|
||||
break;
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
};
|
||||
}
|
||||
|
||||
starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
|
||||
return 0;
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -1210,8 +1211,4 @@ static struct platform_driver zynq_pinctrl_driver = {
|
||||
.probe = zynq_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init zynq_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&zynq_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(zynq_pinctrl_init);
|
||||
module_platform_driver(zynq_pinctrl_driver);
|
||||
|
||||
@ -504,7 +504,7 @@ static const struct pxa_desc_pin pxa27x_pins[] = {
|
||||
|
||||
static int pxa27x_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret, i;
|
||||
int i;
|
||||
void __iomem *base_af[8];
|
||||
void __iomem *base_dir[4];
|
||||
void __iomem *base_sleep[4];
|
||||
@ -532,9 +532,8 @@ static int pxa27x_pinctrl_probe(struct platform_device *pdev)
|
||||
for (i = 0; i < ARRAY_SIZE(base_sleep); i++)
|
||||
base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i;
|
||||
|
||||
ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins),
|
||||
return pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins),
|
||||
base_af, base_dir, base_sleep);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id pxa27x_pinctrl_match[] = {
|
||||
|
||||
@ -248,6 +248,15 @@ config PINCTRL_SC8180X
|
||||
Qualcomm Technologies Inc TLMM block found on the Qualcomm
|
||||
Technologies Inc SC8180x platform.
|
||||
|
||||
config PINCTRL_SC8280XP
|
||||
tristate "Qualcomm Technologies Inc SC8280xp pin controller driver"
|
||||
depends on OF
|
||||
depends on PINCTRL_MSM
|
||||
help
|
||||
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
|
||||
Qualcomm Technologies Inc TLMM block found on the Qualcomm
|
||||
Technologies Inc SC8280xp platform.
|
||||
|
||||
config PINCTRL_SDM660
|
||||
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
|
||||
depends on OF
|
||||
|
||||
@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
|
||||
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
|
||||
obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
|
||||
obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
|
||||
obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
|
||||
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
|
||||
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
|
||||
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
|
||||
|
||||
@ -615,6 +615,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
|
||||
int drive;
|
||||
int pull;
|
||||
int val;
|
||||
int egpio_enable;
|
||||
u32 ctl_reg, io_reg;
|
||||
|
||||
static const char * const pulls_keeper[] = {
|
||||
@ -641,12 +642,20 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
|
||||
func = (ctl_reg >> g->mux_bit) & 7;
|
||||
drive = (ctl_reg >> g->drv_bit) & 7;
|
||||
pull = (ctl_reg >> g->pull_bit) & 3;
|
||||
egpio_enable = 0;
|
||||
if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
|
||||
egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
|
||||
|
||||
if (is_out)
|
||||
val = !!(io_reg & BIT(g->out_bit));
|
||||
else
|
||||
val = !!(io_reg & BIT(g->in_bit));
|
||||
|
||||
if (egpio_enable) {
|
||||
seq_printf(s, " %-8s: egpio\n", g->name);
|
||||
return;
|
||||
}
|
||||
|
||||
seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
|
||||
seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
|
||||
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
|
||||
@ -1168,7 +1177,7 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d,
|
||||
if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
|
||||
return irq_chip_set_affinity_parent(d, dest, force);
|
||||
|
||||
return 0;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
|
||||
@ -1179,7 +1188,7 @@ static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
|
||||
if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
|
||||
return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
|
||||
|
||||
return 0;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void msm_gpio_irq_handler(struct irq_desc *desc)
|
||||
|
||||
@ -1083,6 +1083,16 @@ static const struct msm_pingroup qcm2290_groups[] = {
|
||||
[133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0),
|
||||
};
|
||||
|
||||
static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = {
|
||||
{ 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 },
|
||||
{ 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 },
|
||||
{ 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 },
|
||||
{ 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 },
|
||||
{ 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 },
|
||||
{ 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 },
|
||||
{ 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 },
|
||||
};
|
||||
|
||||
static const struct msm_pinctrl_soc_data qcm2290_pinctrl = {
|
||||
.pins = qcm2290_pins,
|
||||
.npins = ARRAY_SIZE(qcm2290_pins),
|
||||
@ -1091,6 +1101,8 @@ static const struct msm_pinctrl_soc_data qcm2290_pinctrl = {
|
||||
.groups = qcm2290_groups,
|
||||
.ngroups = ARRAY_SIZE(qcm2290_groups),
|
||||
.ngpios = 127,
|
||||
.wakeirq_map = qcm2290_mpm_map,
|
||||
.nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map),
|
||||
};
|
||||
|
||||
static int qcm2290_pinctrl_probe(struct platform_device *pdev)
|
||||
|
||||
@ -1622,8 +1622,8 @@ static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = {
|
||||
};
|
||||
|
||||
/*
|
||||
* ACPI DSDT has one single memory resource for TLMM, which voilates the
|
||||
* hardware layout of 3 sepearte tiles. Let's split the memory resource into
|
||||
* ACPI DSDT has one single memory resource for TLMM, which violates the
|
||||
* hardware layout of 3 separate tiles. Let's split the memory resource into
|
||||
* 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the
|
||||
* same way as for DT probe.
|
||||
*/
|
||||
|
||||
1953
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
Normal file
1953
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
//SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
@ -46,6 +46,8 @@
|
||||
.mux_bit = 2, \
|
||||
.pull_bit = 0, \
|
||||
.drv_bit = 6, \
|
||||
.egpio_enable = 12, \
|
||||
.egpio_present = 11, \
|
||||
.oe_bit = 9, \
|
||||
.in_bit = 0, \
|
||||
.out_bit = 1, \
|
||||
@ -567,6 +569,7 @@ enum sm8450_functions {
|
||||
msm_mux_ddr_pxi2,
|
||||
msm_mux_ddr_pxi3,
|
||||
msm_mux_dp_hot,
|
||||
msm_mux_egpio,
|
||||
msm_mux_gcc_gp1,
|
||||
msm_mux_gcc_gp2,
|
||||
msm_mux_gcc_gp3,
|
||||
@ -719,6 +722,17 @@ static const char * const gpio_groups[] = {
|
||||
"gpio207", "gpio208", "gpio209",
|
||||
};
|
||||
|
||||
static const char * const egpio_groups[] = {
|
||||
"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
|
||||
"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
|
||||
"gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
|
||||
"gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
|
||||
"gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
|
||||
"gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
|
||||
"gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
|
||||
"gpio207", "gpio208", "gpio209",
|
||||
};
|
||||
|
||||
static const char * const aon_cam_groups[] = {
|
||||
"gpio108",
|
||||
};
|
||||
@ -1285,6 +1299,7 @@ static const struct msm_function sm8450_functions[] = {
|
||||
FUNCTION(ddr_pxi2),
|
||||
FUNCTION(ddr_pxi3),
|
||||
FUNCTION(dp_hot),
|
||||
FUNCTION(egpio),
|
||||
FUNCTION(gcc_gp1),
|
||||
FUNCTION(gcc_gp2),
|
||||
FUNCTION(gcc_gp3),
|
||||
@ -1571,51 +1586,51 @@ static const struct msm_pingroup sm8450_groups[] = {
|
||||
[162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _),
|
||||
[163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _),
|
||||
[164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _),
|
||||
[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _),
|
||||
[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _),
|
||||
[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),
|
||||
[168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
|
||||
[169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
|
||||
[170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
|
||||
[171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),
|
||||
[172] = PINGROUP(172, _, _, _, _, _, _, _, _, _),
|
||||
[173] = PINGROUP(173, _, _, _, _, _, _, _, _, _),
|
||||
[174] = PINGROUP(174, _, _, _, _, _, _, _, _, _),
|
||||
[175] = PINGROUP(175, _, _, _, _, _, _, _, _, _),
|
||||
[176] = PINGROUP(176, _, _, _, _, _, _, _, _, _),
|
||||
[177] = PINGROUP(177, _, _, _, _, _, _, _, _, _),
|
||||
[178] = PINGROUP(178, _, _, _, _, _, _, _, _, _),
|
||||
[179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),
|
||||
[180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),
|
||||
[181] = PINGROUP(181, _, _, _, _, _, _, _, _, _),
|
||||
[182] = PINGROUP(182, _, _, _, _, _, _, _, _, _),
|
||||
[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _),
|
||||
[184] = PINGROUP(184, _, _, _, _, _, _, _, _, _),
|
||||
[185] = PINGROUP(185, _, _, _, _, _, _, _, _, _),
|
||||
[186] = PINGROUP(186, _, _, _, _, _, _, _, _, _),
|
||||
[187] = PINGROUP(187, _, _, _, _, _, _, _, _, _),
|
||||
[188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _),
|
||||
[191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _),
|
||||
[192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _),
|
||||
[203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _),
|
||||
[204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _),
|
||||
[205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _),
|
||||
[206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _),
|
||||
[207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _),
|
||||
[208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _),
|
||||
[209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _),
|
||||
[165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio),
|
||||
[166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio),
|
||||
[167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio),
|
||||
[168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio),
|
||||
[169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio),
|
||||
[170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio),
|
||||
[171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio),
|
||||
[172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio),
|
||||
[173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio),
|
||||
[174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio),
|
||||
[175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio),
|
||||
[176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio),
|
||||
[177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio),
|
||||
[178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio),
|
||||
[179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio),
|
||||
[180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio),
|
||||
[181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio),
|
||||
[182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio),
|
||||
[183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio),
|
||||
[184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio),
|
||||
[185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio),
|
||||
[186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio),
|
||||
[187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio),
|
||||
[188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio),
|
||||
[191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio),
|
||||
[192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio),
|
||||
[203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio),
|
||||
[204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio),
|
||||
[205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio),
|
||||
[206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio),
|
||||
[207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio),
|
||||
[208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio),
|
||||
[209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio),
|
||||
[210] = UFS_RESET(ufs_reset, 0xde000),
|
||||
[211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6),
|
||||
[212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3),
|
||||
@ -1651,6 +1666,7 @@ static const struct msm_pinctrl_soc_data sm8450_tlmm = {
|
||||
.ngpios = 211,
|
||||
.wakeirq_map = sm8450_pdc_map,
|
||||
.nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map),
|
||||
.egpio_func = 9,
|
||||
};
|
||||
|
||||
static int sm8450_tlmm_probe(struct platform_device *pdev)
|
||||
|
||||
@ -1164,6 +1164,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
|
||||
{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
|
||||
{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
|
||||
{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
|
||||
{ .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
|
||||
{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
|
||||
{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
|
||||
/* pm8950 has 8 GPIOs with holes on 3 */
|
||||
|
||||
@ -961,6 +961,7 @@ static int pmic_mpp_remove(struct platform_device *pdev)
|
||||
|
||||
static const struct of_device_id pmic_mpp_of_match[] = {
|
||||
{ .compatible = "qcom,pm8019-mpp", .data = (void *) 6 },
|
||||
{ .compatible = "qcom,pm8226-mpp", .data = (void *) 8 },
|
||||
{ .compatible = "qcom,pm8841-mpp", .data = (void *) 4 },
|
||||
{ .compatible = "qcom,pm8916-mpp", .data = (void *) 4 },
|
||||
{ .compatible = "qcom,pm8941-mpp", .data = (void *) 8 },
|
||||
|
||||
@ -37,7 +37,9 @@ config PINCTRL_RENESAS
|
||||
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
|
||||
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
|
||||
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
|
||||
select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
|
||||
select PINCTRL_RZG2L if ARCH_R9A07G044
|
||||
select PINCTRL_RZG2L if ARCH_R9A07G054
|
||||
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
|
||||
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
|
||||
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
|
||||
@ -132,6 +134,10 @@ config PINCTRL_PFC_R8A77961
|
||||
bool "pin control support for R-Car M3-W+" if COMPILE_TEST
|
||||
select PINCTRL_SH_PFC
|
||||
|
||||
config PINCTRL_PFC_R8A779F0
|
||||
bool "pin control support for R-Car S4-8" if COMPILE_TEST
|
||||
select PINCTRL_SH_PFC
|
||||
|
||||
config PINCTRL_PFC_R8A7792
|
||||
bool "pin control support for R-Car V2H" if COMPILE_TEST
|
||||
select PINCTRL_SH_PFC
|
||||
@ -178,14 +184,15 @@ config PINCTRL_RZA2
|
||||
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
|
||||
|
||||
config PINCTRL_RZG2L
|
||||
bool "pin control support for RZ/G2L" if COMPILE_TEST
|
||||
bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST
|
||||
depends on OF
|
||||
select GPIOLIB
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
|
||||
This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L}
|
||||
platforms.
|
||||
|
||||
config PINCTRL_PFC_R8A77470
|
||||
bool "pin control support for RZ/G1C" if COMPILE_TEST
|
||||
|
||||
@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
|
||||
|
||||
@ -636,6 +636,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
|
||||
.data = &r8a779a0_pinmux_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A779F0
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a779f0",
|
||||
.data = &r8a779f0_pinmux_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH73A0
|
||||
{
|
||||
.compatible = "renesas,pfc-sh73a0",
|
||||
@ -741,10 +747,13 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
|
||||
|
||||
#ifdef DEBUG
|
||||
#define SH_PFC_MAX_REGS 300
|
||||
#define SH_PFC_MAX_ENUMS 3000
|
||||
#define SH_PFC_MAX_ENUMS 5000
|
||||
|
||||
static unsigned int sh_pfc_errors __initdata;
|
||||
static unsigned int sh_pfc_warnings __initdata;
|
||||
static bool sh_pfc_bias_done __initdata;
|
||||
static bool sh_pfc_drive_done __initdata;
|
||||
static bool sh_pfc_power_done __initdata;
|
||||
static struct {
|
||||
u32 reg;
|
||||
u32 bits;
|
||||
@ -758,6 +767,15 @@ static u32 sh_pfc_num_enums __initdata;
|
||||
pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
|
||||
sh_pfc_errors++; \
|
||||
} while (0)
|
||||
|
||||
#define sh_pfc_err_once(type, fmt, ...) \
|
||||
do { \
|
||||
if (!sh_pfc_ ## type ## _done) { \
|
||||
sh_pfc_ ## type ## _done = true; \
|
||||
sh_pfc_err(fmt, ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define sh_pfc_warn(fmt, ...) \
|
||||
do { \
|
||||
pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
|
||||
@ -777,10 +795,7 @@ static bool __init is0s(const u16 *enum_ids, unsigned int n)
|
||||
|
||||
static bool __init same_name(const char *a, const char *b)
|
||||
{
|
||||
if (!a || !b)
|
||||
return false;
|
||||
|
||||
return !strcmp(a, b);
|
||||
return a && b && !strcmp(a, b);
|
||||
}
|
||||
|
||||
static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
|
||||
@ -839,21 +854,22 @@ static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
|
||||
u32 reg, unsigned int pin)
|
||||
static const struct sh_pfc_pin __init *sh_pfc_find_pin(
|
||||
const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
|
||||
{
|
||||
const char *drvname = info->name;
|
||||
unsigned int i;
|
||||
|
||||
if (pin == SH_PFC_PIN_NONE)
|
||||
return;
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < info->nr_pins; i++) {
|
||||
if (pin == info->pins[i].pin)
|
||||
return;
|
||||
return &info->pins[i];
|
||||
}
|
||||
|
||||
sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __init sh_pfc_check_cfg_reg(const char *drvname,
|
||||
@ -865,7 +881,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname,
|
||||
GENMASK(cfg_reg->reg_width - 1, 0));
|
||||
|
||||
if (cfg_reg->field_width) {
|
||||
n = cfg_reg->reg_width / cfg_reg->field_width;
|
||||
fw = cfg_reg->field_width;
|
||||
n = (cfg_reg->reg_width / fw) << fw;
|
||||
/* Skip field checks (done at build time) */
|
||||
goto check_enum_ids;
|
||||
}
|
||||
@ -893,6 +910,8 @@ check_enum_ids:
|
||||
static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
|
||||
const struct pinmux_drive_reg *drive)
|
||||
{
|
||||
const char *drvname = info->name;
|
||||
const struct sh_pfc_pin *pin;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
|
||||
@ -905,13 +924,18 @@ static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
|
||||
GENMASK(field->offset + field->size - 1,
|
||||
field->offset));
|
||||
|
||||
sh_pfc_check_pin(info, drive->reg, field->pin);
|
||||
pin = sh_pfc_find_pin(info, drive->reg, field->pin);
|
||||
if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
|
||||
sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
|
||||
drive->reg, i, pin->name);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
|
||||
const struct pinmux_bias_reg *bias)
|
||||
{
|
||||
const char *drvname = info->name;
|
||||
const struct sh_pfc_pin *pin;
|
||||
unsigned int i;
|
||||
u32 bits;
|
||||
|
||||
@ -923,12 +947,66 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
|
||||
sh_pfc_check_reg(info->name, bias->puen, bits);
|
||||
if (bias->pud)
|
||||
sh_pfc_check_reg(info->name, bias->pud, bits);
|
||||
for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
|
||||
sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
|
||||
for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
|
||||
pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
|
||||
if (!pin)
|
||||
continue;
|
||||
|
||||
if (bias->puen && bias->pud) {
|
||||
/*
|
||||
* Pull-enable and pull-up/down control registers
|
||||
* As some SoCs have pins that support only pull-up
|
||||
* or pull-down, we just check for one of them
|
||||
*/
|
||||
if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
|
||||
sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
|
||||
bias->puen, i, pin->name);
|
||||
} else if (bias->puen) {
|
||||
/* Pull-up control register only */
|
||||
if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
|
||||
sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
|
||||
bias->puen, i, pin->name);
|
||||
} else if (bias->pud) {
|
||||
/* Pull-down control register only */
|
||||
if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
|
||||
sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
|
||||
bias->pud, i, pin->name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sh_pfc_compare_groups(const char *drvname,
|
||||
const struct sh_pfc_pin_group *a,
|
||||
const struct sh_pfc_pin_group *b)
|
||||
{
|
||||
unsigned int i;
|
||||
size_t len;
|
||||
|
||||
if (same_name(a->name, b->name))
|
||||
sh_pfc_err("group %s: name conflict\n", a->name);
|
||||
|
||||
if (a->nr_pins > b->nr_pins)
|
||||
swap(a, b);
|
||||
|
||||
len = a->nr_pins * sizeof(a->pins[0]);
|
||||
for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
|
||||
if (a->pins == b->pins + i || a->mux == b->mux + i ||
|
||||
memcmp(a->pins, b->pins + i, len) ||
|
||||
memcmp(a->mux, b->mux + i, len))
|
||||
continue;
|
||||
|
||||
if (a->nr_pins == b->nr_pins)
|
||||
sh_pfc_warn("group %s can be an alias for %s\n",
|
||||
a->name, b->name);
|
||||
else
|
||||
sh_pfc_warn("group %s is a subset of %s\n", a->name,
|
||||
b->name);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
|
||||
{
|
||||
const struct pinmux_drive_reg *drive_regs = info->drive_regs;
|
||||
const struct pinmux_bias_reg *bias_regs = info->bias_regs;
|
||||
const char *drvname = info->name;
|
||||
unsigned int *refcnts;
|
||||
@ -937,10 +1015,14 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
|
||||
pr_info("sh_pfc: Checking %s\n", drvname);
|
||||
sh_pfc_num_regs = 0;
|
||||
sh_pfc_num_enums = 0;
|
||||
sh_pfc_bias_done = false;
|
||||
sh_pfc_drive_done = false;
|
||||
sh_pfc_power_done = false;
|
||||
|
||||
/* Check pins */
|
||||
for (i = 0; i < info->nr_pins; i++) {
|
||||
const struct sh_pfc_pin *pin = &info->pins[i];
|
||||
unsigned int x;
|
||||
|
||||
if (!pin->name) {
|
||||
sh_pfc_err("empty pin %u\n", i);
|
||||
@ -962,6 +1044,65 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
|
||||
pin->name, pin2->name,
|
||||
pin->enum_id);
|
||||
}
|
||||
|
||||
if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
|
||||
if (!info->ops || !info->ops->get_bias ||
|
||||
!info->ops->set_bias)
|
||||
sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
|
||||
|
||||
if (!bias_regs &&
|
||||
(!info->ops || !info->ops->pin_to_portcr))
|
||||
sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
|
||||
}
|
||||
|
||||
if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
|
||||
const struct pinmux_bias_reg *bias_reg =
|
||||
rcar_pin_to_bias_reg(info, pin->pin, &x);
|
||||
|
||||
if (!bias_reg ||
|
||||
((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
|
||||
!bias_reg->puen))
|
||||
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
|
||||
pin->name);
|
||||
|
||||
if (!bias_reg ||
|
||||
((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
|
||||
!bias_reg->pud))
|
||||
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
|
||||
pin->name);
|
||||
}
|
||||
|
||||
if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
|
||||
if (!drive_regs) {
|
||||
sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
|
||||
} else {
|
||||
for (j = 0; drive_regs[j / 8].reg; j++) {
|
||||
if (!drive_regs[j / 8].fields[j % 8].pin &&
|
||||
!drive_regs[j / 8].fields[j % 8].offset &&
|
||||
!drive_regs[j / 8].fields[j % 8].size)
|
||||
continue;
|
||||
|
||||
if (drive_regs[j / 8].fields[j % 8].pin == pin->pin)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!drive_regs[j / 8].reg)
|
||||
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
|
||||
pin->name);
|
||||
}
|
||||
}
|
||||
|
||||
if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
|
||||
if (!info->ops || !info->ops->pin_to_pocctrl)
|
||||
sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
|
||||
else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
|
||||
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
|
||||
pin->name);
|
||||
} else if (info->ops && info->ops->pin_to_pocctrl &&
|
||||
info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
|
||||
sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
|
||||
pin->name);
|
||||
}
|
||||
}
|
||||
|
||||
/* Check groups and functions */
|
||||
@ -1003,11 +1144,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
|
||||
sh_pfc_err("empty group %u\n", i);
|
||||
continue;
|
||||
}
|
||||
for (j = 0; j < i; j++) {
|
||||
if (same_name(group->name, info->groups[j].name))
|
||||
sh_pfc_err("group %s: name conflict\n",
|
||||
group->name);
|
||||
}
|
||||
for (j = 0; j < i; j++)
|
||||
sh_pfc_compare_groups(drvname, group, &info->groups[j]);
|
||||
|
||||
if (!refcnts[i])
|
||||
sh_pfc_err("orphan group %s\n", group->name);
|
||||
else if (refcnts[i] > 1)
|
||||
@ -1022,13 +1161,53 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
|
||||
sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
|
||||
|
||||
/* Check drive strength registers */
|
||||
for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
|
||||
sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
|
||||
for (i = 0; drive_regs && drive_regs[i].reg; i++)
|
||||
sh_pfc_check_drive_reg(info, &drive_regs[i]);
|
||||
|
||||
for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) {
|
||||
if (!drive_regs[i / 8].fields[i % 8].pin &&
|
||||
!drive_regs[i / 8].fields[i % 8].offset &&
|
||||
!drive_regs[i / 8].fields[i % 8].size)
|
||||
continue;
|
||||
|
||||
for (j = 0; j < i; j++) {
|
||||
if (drive_regs[i / 8].fields[i % 8].pin ==
|
||||
drive_regs[j / 8].fields[j % 8].pin &&
|
||||
drive_regs[j / 8].fields[j % 8].offset &&
|
||||
drive_regs[j / 8].fields[j % 8].size) {
|
||||
sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n",
|
||||
drive_regs[i / 8].reg, i % 8,
|
||||
drive_regs[j / 8].reg, j % 8);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check bias registers */
|
||||
for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
|
||||
sh_pfc_check_bias_reg(info, &bias_regs[i]);
|
||||
|
||||
for (i = 0; bias_regs &&
|
||||
(bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) {
|
||||
if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE)
|
||||
continue;
|
||||
|
||||
for (j = 0; j < i; j++) {
|
||||
if (bias_regs[i / 32].pins[i % 32] !=
|
||||
bias_regs[j / 32].pins[j % 32])
|
||||
continue;
|
||||
|
||||
if (bias_regs[i / 32].puen && bias_regs[j / 32].puen)
|
||||
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
|
||||
bias_regs[i / 32].puen, i % 32,
|
||||
bias_regs[j / 32].puen, j % 32);
|
||||
if (bias_regs[i / 32].pud && bias_regs[j / 32].pud)
|
||||
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
|
||||
bias_regs[i / 32].pud, i % 32,
|
||||
bias_regs[j / 32].pud, j % 32);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Check ioctrl registers */
|
||||
for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
|
||||
sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);
|
||||
|
||||
@ -749,23 +749,14 @@ static const unsigned int cf_ctrl_mux[] = {
|
||||
CF_CDB2_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int cf_data8_pins[] = {
|
||||
/* CF_D[0:7] */
|
||||
77, 78, 79, 80,
|
||||
81, 82, 83, 84,
|
||||
};
|
||||
static const unsigned int cf_data8_mux[] = {
|
||||
CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
|
||||
CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
|
||||
};
|
||||
static const unsigned int cf_data16_pins[] = {
|
||||
static const unsigned int cf_data_pins[] = {
|
||||
/* CF_D[0:15] */
|
||||
77, 78, 79, 80,
|
||||
81, 82, 83, 84,
|
||||
85, 86, 87, 88,
|
||||
89, 90, 91, 92,
|
||||
};
|
||||
static const unsigned int cf_data16_mux[] = {
|
||||
static const unsigned int cf_data_mux[] = {
|
||||
CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
|
||||
CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
|
||||
CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
|
||||
@ -895,26 +886,12 @@ static const unsigned int sdi0_ctrl_mux[] = {
|
||||
SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdi0_data1_pins[] = {
|
||||
/* SDI0_DATA[0] */
|
||||
53,
|
||||
};
|
||||
static const unsigned int sdi0_data1_mux[] = {
|
||||
SDI0_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdi0_data4_pins[] = {
|
||||
/* SDI0_DATA[0:3] */
|
||||
53, 54, 55, 56,
|
||||
};
|
||||
static const unsigned int sdi0_data4_mux[] = {
|
||||
SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdi0_data8_pins[] = {
|
||||
static const unsigned int sdi0_data_pins[] = {
|
||||
/* SDI0_DATA[0:7] */
|
||||
53, 54, 55, 56,
|
||||
57, 58, 59, 60
|
||||
};
|
||||
static const unsigned int sdi0_data8_mux[] = {
|
||||
static const unsigned int sdi0_data_mux[] = {
|
||||
SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
|
||||
SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
|
||||
};
|
||||
@ -928,18 +905,11 @@ static const unsigned int sdi1_ctrl_mux[] = {
|
||||
SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdi1_data1_pins[] = {
|
||||
/* SDI1_DATA[0] */
|
||||
64,
|
||||
};
|
||||
static const unsigned int sdi1_data1_mux[] = {
|
||||
SDI1_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdi1_data4_pins[] = {
|
||||
static const unsigned int sdi1_data_pins[] = {
|
||||
/* SDI1_DATA[0:3] */
|
||||
64, 65, 66, 67,
|
||||
};
|
||||
static const unsigned int sdi1_data4_mux[] = {
|
||||
static const unsigned int sdi1_data_mux[] = {
|
||||
SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
|
||||
};
|
||||
|
||||
@ -952,18 +922,11 @@ static const unsigned int sdi2_ctrl_mux[] = {
|
||||
SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdi2_data1_pins[] = {
|
||||
/* SDI2_DATA[0] */
|
||||
89,
|
||||
};
|
||||
static const unsigned int sdi2_data1_mux[] = {
|
||||
SDI2_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdi2_data4_pins[] = {
|
||||
static const unsigned int sdi2_data_pins[] = {
|
||||
/* SDI2_DATA[0:3] */
|
||||
89, 90, 91, 92,
|
||||
};
|
||||
static const unsigned int sdi2_data4_mux[] = {
|
||||
static const unsigned int sdi2_data_mux[] = {
|
||||
SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
|
||||
};
|
||||
|
||||
@ -1131,8 +1094,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(cam),
|
||||
|
||||
SH_PFC_PIN_GROUP(cf_ctrl),
|
||||
SH_PFC_PIN_GROUP(cf_data8),
|
||||
SH_PFC_PIN_GROUP(cf_data16),
|
||||
BUS_DATA_PIN_GROUP(cf_data, 8),
|
||||
BUS_DATA_PIN_GROUP(cf_data, 16),
|
||||
|
||||
SH_PFC_PIN_GROUP(dtv_a),
|
||||
SH_PFC_PIN_GROUP(dtv_b),
|
||||
@ -1161,17 +1124,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(sd_cki),
|
||||
|
||||
SH_PFC_PIN_GROUP(sdi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdi0_data4),
|
||||
SH_PFC_PIN_GROUP(sdi0_data8),
|
||||
BUS_DATA_PIN_GROUP(sdi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdi0_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdi0_data, 8),
|
||||
|
||||
SH_PFC_PIN_GROUP(sdi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdi1_data, 4),
|
||||
|
||||
SH_PFC_PIN_GROUP(sdi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdi2_data, 4),
|
||||
|
||||
SH_PFC_PIN_GROUP(tp33),
|
||||
|
||||
|
||||
@ -1449,25 +1449,11 @@ IRQC_PINS_MUX(327, 55);
|
||||
IRQC_PINS_MUX(328, 56);
|
||||
IRQC_PINS_MUX(329, 57);
|
||||
/* - MMCIF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int mmc0_data1_pins[] = {
|
||||
/* D[0] */
|
||||
164,
|
||||
};
|
||||
static const unsigned int mmc0_data1_mux[] = {
|
||||
MMCD0_0_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
164, 165, 166, 167,
|
||||
};
|
||||
static const unsigned int mmc0_data4_mux[] = {
|
||||
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data8_pins[] = {
|
||||
static const unsigned int mmc0_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
164, 165, 166, 167, 168, 169, 170, 171,
|
||||
};
|
||||
static const unsigned int mmc0_data8_mux[] = {
|
||||
static const unsigned int mmc0_data_mux[] = {
|
||||
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
|
||||
MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
|
||||
};
|
||||
@ -1479,25 +1465,11 @@ static const unsigned int mmc0_ctrl_mux[] = {
|
||||
MMCCMD0_MARK, MMCCLK0_MARK,
|
||||
};
|
||||
/* - MMCIF1 ----------------------------------------------------------------- */
|
||||
static const unsigned int mmc1_data1_pins[] = {
|
||||
/* D[0] */
|
||||
199,
|
||||
};
|
||||
static const unsigned int mmc1_data1_mux[] = {
|
||||
MMCD1_0_MARK,
|
||||
};
|
||||
static const unsigned int mmc1_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
199, 198, 197, 196,
|
||||
};
|
||||
static const unsigned int mmc1_data4_mux[] = {
|
||||
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
|
||||
};
|
||||
static const unsigned int mmc1_data8_pins[] = {
|
||||
static const unsigned int mmc1_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
199, 198, 197, 196, 195, 194, 193, 192,
|
||||
};
|
||||
static const unsigned int mmc1_data8_mux[] = {
|
||||
static const unsigned int mmc1_data_mux[] = {
|
||||
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
|
||||
MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
|
||||
};
|
||||
@ -1704,18 +1676,11 @@ static const unsigned int scifb3_ctrl_b_mux[] = {
|
||||
SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
302,
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SDHID0_0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
302, 303, 304, 305,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -1740,18 +1705,11 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SDHIWP0_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
289,
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SDHID1_0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
289, 290, 291, 292,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
@ -1762,18 +1720,11 @@ static const unsigned int sdhi1_ctrl_mux[] = {
|
||||
SDHICLK1_MARK, SDHICMD1_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
295,
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SDHID2_0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
295, 296, 297, 298,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
@ -1843,13 +1794,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(irqc_irq55),
|
||||
SH_PFC_PIN_GROUP(irqc_irq56),
|
||||
SH_PFC_PIN_GROUP(irqc_irq57),
|
||||
SH_PFC_PIN_GROUP(mmc0_data1),
|
||||
SH_PFC_PIN_GROUP(mmc0_data4),
|
||||
SH_PFC_PIN_GROUP(mmc0_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc0_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc1_data1),
|
||||
SH_PFC_PIN_GROUP(mmc1_data4),
|
||||
SH_PFC_PIN_GROUP(mmc1_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc1_ctrl),
|
||||
SH_PFC_PIN_GROUP(scifa0_data),
|
||||
SH_PFC_PIN_GROUP(scifa0_clk),
|
||||
@ -1878,16 +1829,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scifb3_data_b),
|
||||
SH_PFC_PIN_GROUP(scifb3_clk_b),
|
||||
SH_PFC_PIN_GROUP(scifb3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
};
|
||||
|
||||
@ -2655,9 +2606,9 @@ static const unsigned int r8a73a4_portcr_offsets[] = {
|
||||
0x00002000, 0x00003000, 0x00003000,
|
||||
};
|
||||
|
||||
static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
|
||||
static int r8a73a4_pin_to_portcr(unsigned int pin)
|
||||
{
|
||||
return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
|
||||
return r8a73a4_portcr_offsets[pin >> 5] + pin;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
|
||||
|
||||
@ -1638,33 +1638,14 @@ static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
};
|
||||
|
||||
/* - BSC -------------------------------------------------------------------- */
|
||||
static const unsigned int bsc_data8_pins[] = {
|
||||
/* D[0:7] */
|
||||
157, 156, 155, 154, 153, 152, 151, 150,
|
||||
};
|
||||
static const unsigned int bsc_data8_mux[] = {
|
||||
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
|
||||
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
|
||||
};
|
||||
static const unsigned int bsc_data16_pins[] = {
|
||||
/* D[0:15] */
|
||||
157, 156, 155, 154, 153, 152, 151, 150,
|
||||
149, 148, 147, 146, 145, 144, 143, 142,
|
||||
};
|
||||
static const unsigned int bsc_data16_mux[] = {
|
||||
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
|
||||
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
|
||||
D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
|
||||
D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
|
||||
};
|
||||
static const unsigned int bsc_data32_pins[] = {
|
||||
static const unsigned int bsc_data_pins[] = {
|
||||
/* D[0:31] */
|
||||
157, 156, 155, 154, 153, 152, 151, 150,
|
||||
149, 148, 147, 146, 145, 144, 143, 142,
|
||||
171, 170, 169, 168, 167, 166, 173, 172,
|
||||
165, 164, 163, 162, 161, 160, 159, 158,
|
||||
};
|
||||
static const unsigned int bsc_data32_mux[] = {
|
||||
static const unsigned int bsc_data_mux[] = {
|
||||
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
|
||||
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
|
||||
D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
|
||||
@ -1723,25 +1704,11 @@ static const unsigned int bsc_cs6a_pins[] = {
|
||||
static const unsigned int bsc_cs6a_mux[] = {
|
||||
CS6A_MARK,
|
||||
};
|
||||
static const unsigned int bsc_rd_we8_pins[] = {
|
||||
/* RD, WE[0] */
|
||||
115, 113,
|
||||
};
|
||||
static const unsigned int bsc_rd_we8_mux[] = {
|
||||
RD_FSC_MARK, WE0_FWE_MARK,
|
||||
};
|
||||
static const unsigned int bsc_rd_we16_pins[] = {
|
||||
/* RD, WE[0:1] */
|
||||
115, 113, 112,
|
||||
};
|
||||
static const unsigned int bsc_rd_we16_mux[] = {
|
||||
RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
|
||||
};
|
||||
static const unsigned int bsc_rd_we32_pins[] = {
|
||||
static const unsigned int bsc_rd_we_pins[] = {
|
||||
/* RD, WE[0:3] */
|
||||
115, 113, 112, 108, 107,
|
||||
};
|
||||
static const unsigned int bsc_rd_we32_mux[] = {
|
||||
static const unsigned int bsc_rd_we_mux[] = {
|
||||
RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
|
||||
};
|
||||
static const unsigned int bsc_bs_pins[] = {
|
||||
@ -2064,58 +2031,6 @@ IRQC_PINS_MUX(31, 0, 41);
|
||||
IRQC_PINS_MUX(31, 1, 167);
|
||||
|
||||
/* - LCD0 ------------------------------------------------------------------- */
|
||||
static const unsigned int lcd0_data8_pins[] = {
|
||||
/* D[0:7] */
|
||||
58, 57, 56, 55, 54, 53, 52, 51,
|
||||
};
|
||||
static const unsigned int lcd0_data8_mux[] = {
|
||||
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
|
||||
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
|
||||
};
|
||||
static const unsigned int lcd0_data9_pins[] = {
|
||||
/* D[0:8] */
|
||||
58, 57, 56, 55, 54, 53, 52, 51,
|
||||
50,
|
||||
};
|
||||
static const unsigned int lcd0_data9_mux[] = {
|
||||
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
|
||||
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
|
||||
LCD0_D8_MARK,
|
||||
};
|
||||
static const unsigned int lcd0_data12_pins[] = {
|
||||
/* D[0:11] */
|
||||
58, 57, 56, 55, 54, 53, 52, 51,
|
||||
50, 49, 48, 47,
|
||||
};
|
||||
static const unsigned int lcd0_data12_mux[] = {
|
||||
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
|
||||
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
|
||||
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
|
||||
};
|
||||
static const unsigned int lcd0_data16_pins[] = {
|
||||
/* D[0:15] */
|
||||
58, 57, 56, 55, 54, 53, 52, 51,
|
||||
50, 49, 48, 47, 46, 45, 44, 43,
|
||||
};
|
||||
static const unsigned int lcd0_data16_mux[] = {
|
||||
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
|
||||
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
|
||||
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
|
||||
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
|
||||
};
|
||||
static const unsigned int lcd0_data18_pins[] = {
|
||||
/* D[0:17] */
|
||||
58, 57, 56, 55, 54, 53, 52, 51,
|
||||
50, 49, 48, 47, 46, 45, 44, 43,
|
||||
42, 41,
|
||||
};
|
||||
static const unsigned int lcd0_data18_mux[] = {
|
||||
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
|
||||
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
|
||||
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
|
||||
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
|
||||
LCD0_D16_MARK, LCD0_D17_MARK,
|
||||
};
|
||||
static const unsigned int lcd0_data24_0_pins[] = {
|
||||
/* D[0:23] */
|
||||
58, 57, 56, 55, 54, 53, 52, 51,
|
||||
@ -2182,65 +2097,13 @@ static const unsigned int lcd0_sys_mux[] = {
|
||||
LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
|
||||
};
|
||||
/* - LCD1 ------------------------------------------------------------------- */
|
||||
static const unsigned int lcd1_data8_pins[] = {
|
||||
/* D[0:7] */
|
||||
4, 3, 2, 1, 0, 91, 92, 23,
|
||||
};
|
||||
static const unsigned int lcd1_data8_mux[] = {
|
||||
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
|
||||
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
|
||||
};
|
||||
static const unsigned int lcd1_data9_pins[] = {
|
||||
/* D[0:8] */
|
||||
4, 3, 2, 1, 0, 91, 92, 23,
|
||||
93,
|
||||
};
|
||||
static const unsigned int lcd1_data9_mux[] = {
|
||||
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
|
||||
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
|
||||
LCD1_D8_MARK,
|
||||
};
|
||||
static const unsigned int lcd1_data12_pins[] = {
|
||||
/* D[0:11] */
|
||||
4, 3, 2, 1, 0, 91, 92, 23,
|
||||
93, 94, 21, 201,
|
||||
};
|
||||
static const unsigned int lcd1_data12_mux[] = {
|
||||
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
|
||||
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
|
||||
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
|
||||
};
|
||||
static const unsigned int lcd1_data16_pins[] = {
|
||||
/* D[0:15] */
|
||||
4, 3, 2, 1, 0, 91, 92, 23,
|
||||
93, 94, 21, 201, 200, 199, 196, 195,
|
||||
};
|
||||
static const unsigned int lcd1_data16_mux[] = {
|
||||
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
|
||||
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
|
||||
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
|
||||
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
|
||||
};
|
||||
static const unsigned int lcd1_data18_pins[] = {
|
||||
/* D[0:17] */
|
||||
4, 3, 2, 1, 0, 91, 92, 23,
|
||||
93, 94, 21, 201, 200, 199, 196, 195,
|
||||
194, 193,
|
||||
};
|
||||
static const unsigned int lcd1_data18_mux[] = {
|
||||
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
|
||||
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
|
||||
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
|
||||
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
|
||||
LCD1_D16_MARK, LCD1_D17_MARK,
|
||||
};
|
||||
static const unsigned int lcd1_data24_pins[] = {
|
||||
static const unsigned int lcd1_data_pins[] = {
|
||||
/* D[0:23] */
|
||||
4, 3, 2, 1, 0, 91, 92, 23,
|
||||
93, 94, 21, 201, 200, 199, 196, 195,
|
||||
194, 193, 198, 197, 75, 74, 15, 14,
|
||||
};
|
||||
static const unsigned int lcd1_data24_mux[] = {
|
||||
static const unsigned int lcd1_data_mux[] = {
|
||||
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
|
||||
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
|
||||
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
|
||||
@ -2277,25 +2140,11 @@ static const unsigned int lcd1_sys_mux[] = {
|
||||
LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
|
||||
};
|
||||
/* - MMCIF ------------------------------------------------------------------ */
|
||||
static const unsigned int mmc0_data1_0_pins[] = {
|
||||
/* D[0] */
|
||||
68,
|
||||
};
|
||||
static const unsigned int mmc0_data1_0_mux[] = {
|
||||
MMC0_D0_PORT68_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data4_0_pins[] = {
|
||||
/* D[0:3] */
|
||||
68, 69, 70, 71,
|
||||
};
|
||||
static const unsigned int mmc0_data4_0_mux[] = {
|
||||
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data8_0_pins[] = {
|
||||
static const unsigned int mmc0_data_0_pins[] = {
|
||||
/* D[0:7] */
|
||||
68, 69, 70, 71, 72, 73, 74, 75,
|
||||
};
|
||||
static const unsigned int mmc0_data8_0_mux[] = {
|
||||
static const unsigned int mmc0_data_0_mux[] = {
|
||||
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
|
||||
MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
|
||||
};
|
||||
@ -2307,25 +2156,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = {
|
||||
MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int mmc0_data1_1_pins[] = {
|
||||
/* D[0] */
|
||||
149,
|
||||
};
|
||||
static const unsigned int mmc0_data1_1_mux[] = {
|
||||
MMC1_D0_PORT149_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data4_1_pins[] = {
|
||||
/* D[0:3] */
|
||||
149, 148, 147, 146,
|
||||
};
|
||||
static const unsigned int mmc0_data4_1_mux[] = {
|
||||
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data8_1_pins[] = {
|
||||
static const unsigned int mmc0_data_1_pins[] = {
|
||||
/* D[0:7] */
|
||||
149, 148, 147, 146, 145, 144, 143, 142,
|
||||
};
|
||||
static const unsigned int mmc0_data8_1_mux[] = {
|
||||
static const unsigned int mmc0_data_1_mux[] = {
|
||||
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
|
||||
MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
|
||||
};
|
||||
@ -2591,18 +2426,11 @@ static const unsigned int scifb_ctrl_1_mux[] = {
|
||||
SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
77,
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SDHI0_D0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
77, 78, 79, 80,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -2627,18 +2455,11 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SDHI0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
68,
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SDHI1_D0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
68, 69, 70, 71,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
@ -2663,18 +2484,11 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SDHI1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
205,
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SDHI2_D0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
205, 206, 207, 208,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
@ -2750,9 +2564,9 @@ static const unsigned int tpu0_to3_mux[] = {
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(bsc_data8),
|
||||
SH_PFC_PIN_GROUP(bsc_data16),
|
||||
SH_PFC_PIN_GROUP(bsc_data32),
|
||||
BUS_DATA_PIN_GROUP(bsc_data, 8),
|
||||
BUS_DATA_PIN_GROUP(bsc_data, 16),
|
||||
BUS_DATA_PIN_GROUP(bsc_data, 32),
|
||||
SH_PFC_PIN_GROUP(bsc_cs0),
|
||||
SH_PFC_PIN_GROUP(bsc_cs2),
|
||||
SH_PFC_PIN_GROUP(bsc_cs4),
|
||||
@ -2760,9 +2574,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(bsc_cs5a_1),
|
||||
SH_PFC_PIN_GROUP(bsc_cs5b),
|
||||
SH_PFC_PIN_GROUP(bsc_cs6a),
|
||||
SH_PFC_PIN_GROUP(bsc_rd_we8),
|
||||
SH_PFC_PIN_GROUP(bsc_rd_we16),
|
||||
SH_PFC_PIN_GROUP(bsc_rd_we32),
|
||||
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3),
|
||||
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5),
|
||||
SH_PFC_PIN_GROUP(bsc_bs),
|
||||
SH_PFC_PIN_GROUP(bsc_rdwr),
|
||||
SH_PFC_PIN_GROUP(ceu0_data_0_7),
|
||||
@ -2847,11 +2661,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(intc_irq30_1),
|
||||
SH_PFC_PIN_GROUP(intc_irq31_0),
|
||||
SH_PFC_PIN_GROUP(intc_irq31_1),
|
||||
SH_PFC_PIN_GROUP(lcd0_data8),
|
||||
SH_PFC_PIN_GROUP(lcd0_data9),
|
||||
SH_PFC_PIN_GROUP(lcd0_data12),
|
||||
SH_PFC_PIN_GROUP(lcd0_data16),
|
||||
SH_PFC_PIN_GROUP(lcd0_data18),
|
||||
SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8),
|
||||
SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9),
|
||||
SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12),
|
||||
SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16),
|
||||
SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18),
|
||||
SH_PFC_PIN_GROUP(lcd0_data24_0),
|
||||
SH_PFC_PIN_GROUP(lcd0_data24_1),
|
||||
SH_PFC_PIN_GROUP(lcd0_display),
|
||||
@ -2859,23 +2673,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(lcd0_lclk_1),
|
||||
SH_PFC_PIN_GROUP(lcd0_sync),
|
||||
SH_PFC_PIN_GROUP(lcd0_sys),
|
||||
SH_PFC_PIN_GROUP(lcd1_data8),
|
||||
SH_PFC_PIN_GROUP(lcd1_data9),
|
||||
SH_PFC_PIN_GROUP(lcd1_data12),
|
||||
SH_PFC_PIN_GROUP(lcd1_data16),
|
||||
SH_PFC_PIN_GROUP(lcd1_data18),
|
||||
SH_PFC_PIN_GROUP(lcd1_data24),
|
||||
BUS_DATA_PIN_GROUP(lcd1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(lcd1_data, 9),
|
||||
BUS_DATA_PIN_GROUP(lcd1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(lcd1_data, 16),
|
||||
BUS_DATA_PIN_GROUP(lcd1_data, 18),
|
||||
BUS_DATA_PIN_GROUP(lcd1_data, 24),
|
||||
SH_PFC_PIN_GROUP(lcd1_display),
|
||||
SH_PFC_PIN_GROUP(lcd1_lclk),
|
||||
SH_PFC_PIN_GROUP(lcd1_sync),
|
||||
SH_PFC_PIN_GROUP(lcd1_sys),
|
||||
SH_PFC_PIN_GROUP(mmc0_data1_0),
|
||||
SH_PFC_PIN_GROUP(mmc0_data4_0),
|
||||
SH_PFC_PIN_GROUP(mmc0_data8_0),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 1, _0),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 4, _0),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 8, _0),
|
||||
SH_PFC_PIN_GROUP(mmc0_ctrl_0),
|
||||
SH_PFC_PIN_GROUP(mmc0_data1_1),
|
||||
SH_PFC_PIN_GROUP(mmc0_data4_1),
|
||||
SH_PFC_PIN_GROUP(mmc0_data8_1),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 1, _1),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 4, _1),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 8, _1),
|
||||
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
|
||||
SH_PFC_PIN_GROUP(scifa0_data),
|
||||
SH_PFC_PIN_GROUP(scifa0_clk),
|
||||
@ -2912,18 +2726,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scifb_data_1),
|
||||
SH_PFC_PIN_GROUP(scifb_clk_1),
|
||||
SH_PFC_PIN_GROUP(scifb_ctrl_1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_0),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_0),
|
||||
@ -3681,7 +3495,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
|
||||
{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
|
||||
};
|
||||
|
||||
static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
|
||||
static int r8a7740_pin_to_portcr(unsigned int pin)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
@ -3690,10 +3504,10 @@ static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
|
||||
&r8a7740_portcr_offsets[i];
|
||||
|
||||
if (pin <= group->end_pin)
|
||||
return pfc->windows->virt + group->offset + pin;
|
||||
return group->offset + pin;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
|
||||
|
||||
@ -1595,30 +1595,14 @@ static const unsigned int i2c4_e_mux[] = {
|
||||
SCL4_E_MARK, SDA4_E_MARK,
|
||||
};
|
||||
/* - MMC -------------------------------------------------------------------- */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(0, 15),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC0_D0_SDHI1_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
|
||||
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
|
||||
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
|
||||
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
|
||||
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
|
||||
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
|
||||
MMC0_D4_MARK, MMC0_D5_MARK,
|
||||
@ -1639,19 +1623,12 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
|
||||
RCAR_GP_PIN(1, 20),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
@ -1662,19 +1639,12 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
|
||||
RCAR_GP_PIN(4, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
@ -1917,19 +1887,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
||||
SCIF_CLK_B_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
|
||||
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -1954,29 +1917,6 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(0, 15),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
MMC0_D0_SDHI1_D0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
|
||||
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
|
||||
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
/* CLK, CMD */
|
||||
RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_mux[] = {
|
||||
MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_cd_pins[] = {
|
||||
/* CD */
|
||||
RCAR_GP_PIN(0, 19),
|
||||
@ -1992,19 +1932,12 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
|
||||
RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
@ -2047,43 +1980,39 @@ static const unsigned int usb1_mux[] = {
|
||||
USB1_OVC_MARK,
|
||||
};
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin0_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
|
||||
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
|
||||
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
|
||||
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
|
||||
/* G */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
/* R */
|
||||
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
|
||||
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
|
||||
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
|
||||
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
|
||||
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
|
||||
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
|
||||
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
|
||||
/* G */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
/* R */
|
||||
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
|
||||
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
|
||||
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
|
||||
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
static const union vin_data vin0_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
/* B */
|
||||
@ -2140,25 +2069,21 @@ static const unsigned int vin0_clk_mux[] = {
|
||||
VI0_CLK_MARK,
|
||||
};
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
|
||||
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
|
||||
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
|
||||
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
|
||||
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
|
||||
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
|
||||
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
|
||||
};
|
||||
static const union vin_data vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
RCAR_GP_PIN(3, 11), /* HSYNC */
|
||||
@ -2243,16 +2168,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(i2c4_c),
|
||||
SH_PFC_PIN_GROUP(i2c4_d),
|
||||
SH_PFC_PIN_GROUP(i2c4_e),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(scif0_data_a),
|
||||
SH_PFC_PIN_GROUP(scif0_data_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data_c),
|
||||
@ -2286,37 +2211,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scif5_data_f),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1),
|
||||
SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4),
|
||||
SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
@ -3420,8 +3345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
@ -3683,7 +3607,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a77470_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
@ -3692,7 +3616,7 @@ static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77470
|
||||
const struct sh_pfc_soc_info r8a77470_pinmux_info = {
|
||||
.name = "r8a77470_pfc",
|
||||
.ops = &r8a77470_pinmux_ops,
|
||||
.ops = &r8a77470_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
@ -1427,25 +1427,17 @@ I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
|
||||
/* - MMC macro -------------------------------------------------------------- */
|
||||
#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
|
||||
#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
|
||||
#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
|
||||
#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
|
||||
#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
|
||||
SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
|
||||
|
||||
/* - MMC -------------------------------------------------------------------- */
|
||||
MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
|
||||
MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
|
||||
MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
|
||||
MMC_PFC_DAT1(mmc_data1, MMC_D0);
|
||||
MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
|
||||
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
|
||||
MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
|
||||
MMC_D2, MMC_D3);
|
||||
MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
|
||||
MMC_PFC_PINS(mmc_data, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
|
||||
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
|
||||
RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
|
||||
MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
|
||||
MMC_PFC_DAT8(mmc_data, MMC_D0, MMC_D1,
|
||||
MMC_D2, MMC_D3,
|
||||
MMC_D4, MMC_D5,
|
||||
MMC_D6, MMC_D7);
|
||||
@ -1530,7 +1522,6 @@ SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
|
||||
|
||||
/* - SDHI macro ------------------------------------------------------------- */
|
||||
#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
|
||||
#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
|
||||
#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
|
||||
#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
|
||||
#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
|
||||
@ -1541,11 +1532,9 @@ SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17));
|
||||
SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
|
||||
SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
|
||||
SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
|
||||
SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
|
||||
SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
|
||||
SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
SDHI_PFC_PINS(sdhi0_data, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
|
||||
SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
|
||||
SDHI_PFC_DAT4(sdhi0_data, SD0_DAT0, SD0_DAT1,
|
||||
SD0_DAT2, SD0_DAT3);
|
||||
SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
|
||||
SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
|
||||
@ -1559,17 +1548,13 @@ SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
|
||||
SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
|
||||
SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
|
||||
SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
|
||||
SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
|
||||
SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
|
||||
SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
|
||||
SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
|
||||
SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
|
||||
SDHI_PFC_PINS(sdhi1_data_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
|
||||
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
|
||||
SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
|
||||
SDHI_PFC_DAT4(sdhi1_data_a, SD1_DAT0_A, SD1_DAT1_A,
|
||||
SD1_DAT2_A, SD1_DAT3_A);
|
||||
SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
|
||||
SDHI_PFC_PINS(sdhi1_data_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
|
||||
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
|
||||
SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
|
||||
SDHI_PFC_DAT4(sdhi1_data_b, SD1_DAT0_B, SD1_DAT1_B,
|
||||
SD1_DAT2_B, SD1_DAT3_B);
|
||||
SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
|
||||
SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
|
||||
@ -1585,17 +1570,13 @@ SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
|
||||
SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
|
||||
SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
|
||||
SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
|
||||
SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
|
||||
SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
|
||||
SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
|
||||
SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
|
||||
SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
|
||||
SDHI_PFC_PINS(sdhi2_data_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
|
||||
RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
|
||||
SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
|
||||
SDHI_PFC_DAT4(sdhi2_data_a, SD2_DAT0_A, SD2_DAT1_A,
|
||||
SD2_DAT2_A, SD2_DAT3_A);
|
||||
SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
|
||||
SDHI_PFC_PINS(sdhi2_data_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
|
||||
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
|
||||
SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
|
||||
SDHI_PFC_DAT4(sdhi2_data_b, SD2_DAT0_B, SD2_DAT1_B,
|
||||
SD2_DAT2_B, SD2_DAT3_B);
|
||||
SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
|
||||
SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
|
||||
@ -1744,9 +1725,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(i2c3_b),
|
||||
SH_PFC_PIN_GROUP(i2c3_c),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(scif_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_data_a),
|
||||
SH_PFC_PIN_GROUP(scif0_data_b),
|
||||
@ -1781,27 +1762,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scif5_data_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd_a),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd_b),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1_a),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1_b),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4_a),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4_b),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp_a),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4_b),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_b),
|
||||
SH_PFC_PIN_GROUP(ssi012_ctrl),
|
||||
|
||||
@ -1928,28 +1928,13 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
|
||||
EX_CS5_MARK,
|
||||
};
|
||||
/* - MMCIF ------------------------------------------------------------------ */
|
||||
static const unsigned int mmc0_data1_pins[] = {
|
||||
/* D[0] */
|
||||
RCAR_GP_PIN(0, 19),
|
||||
};
|
||||
static const unsigned int mmc0_data1_mux[] = {
|
||||
MMC0_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
|
||||
RCAR_GP_PIN(0, 2),
|
||||
};
|
||||
static const unsigned int mmc0_data4_mux[] = {
|
||||
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data8_pins[] = {
|
||||
static const unsigned int mmc0_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
|
||||
};
|
||||
static const unsigned int mmc0_data8_mux[] = {
|
||||
static const unsigned int mmc0_data_mux[] = {
|
||||
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
|
||||
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
|
||||
};
|
||||
@ -1960,28 +1945,13 @@ static const unsigned int mmc0_ctrl_pins[] = {
|
||||
static const unsigned int mmc0_ctrl_mux[] = {
|
||||
MMC0_CMD_MARK, MMC0_CLK_MARK,
|
||||
};
|
||||
static const unsigned int mmc1_data1_pins[] = {
|
||||
/* D[0] */
|
||||
RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
static const unsigned int mmc1_data1_mux[] = {
|
||||
MMC1_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc1_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11),
|
||||
};
|
||||
static const unsigned int mmc1_data4_mux[] = {
|
||||
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc1_data8_pins[] = {
|
||||
static const unsigned int mmc1_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
|
||||
};
|
||||
static const unsigned int mmc1_data8_mux[] = {
|
||||
static const unsigned int mmc1_data_mux[] = {
|
||||
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
|
||||
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
|
||||
};
|
||||
@ -2386,19 +2356,12 @@ static const unsigned int scif_clk_d_mux[] = {
|
||||
SCIF_CLK_D_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 21),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
|
||||
RCAR_GP_PIN(3, 24),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -2423,19 +2386,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(0, 19),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
|
||||
RCAR_GP_PIN(0, 2),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
@ -2460,19 +2416,12 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 1),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
@ -2497,19 +2446,12 @@ static const unsigned int sdhi2_wp_mux[] = {
|
||||
SD2_WP_MARK,
|
||||
};
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(1, 18),
|
||||
};
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
|
||||
RCAR_GP_PIN(1, 21),
|
||||
};
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_ctrl_pins[] = {
|
||||
@ -2749,13 +2691,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(lbsc_ex_cs3),
|
||||
SH_PFC_PIN_GROUP(lbsc_ex_cs4),
|
||||
SH_PFC_PIN_GROUP(lbsc_ex_cs5),
|
||||
SH_PFC_PIN_GROUP(mmc0_data1),
|
||||
SH_PFC_PIN_GROUP(mmc0_data4),
|
||||
SH_PFC_PIN_GROUP(mmc0_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc0_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc1_data1),
|
||||
SH_PFC_PIN_GROUP(mmc1_data4),
|
||||
SH_PFC_PIN_GROUP(mmc1_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc1_ctrl),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
@ -2812,23 +2754,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif_clk_c),
|
||||
SH_PFC_PIN_GROUP(scif_clk_d),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
@ -3133,10 +3075,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(lbsc),
|
||||
SH_PFC_FUNCTION(mmc0),
|
||||
SH_PFC_FUNCTION(mmc1),
|
||||
SH_PFC_FUNCTION(sdhi0),
|
||||
SH_PFC_FUNCTION(sdhi1),
|
||||
SH_PFC_FUNCTION(sdhi2),
|
||||
SH_PFC_FUNCTION(sdhi3),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
@ -3144,6 +3082,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(scif4),
|
||||
SH_PFC_FUNCTION(scif5),
|
||||
SH_PFC_FUNCTION(scif_clk),
|
||||
SH_PFC_FUNCTION(sdhi0),
|
||||
SH_PFC_FUNCTION(sdhi1),
|
||||
SH_PFC_FUNCTION(sdhi2),
|
||||
SH_PFC_FUNCTION(sdhi3),
|
||||
SH_PFC_FUNCTION(usb0),
|
||||
SH_PFC_FUNCTION(usb1),
|
||||
SH_PFC_FUNCTION(usb2),
|
||||
|
||||
@ -194,24 +194,24 @@ enum {
|
||||
FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
|
||||
FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
|
||||
FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
|
||||
FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
|
||||
FN_WE0_N, FN_IECLK, FN_CAN_CLK,
|
||||
FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
|
||||
FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
|
||||
FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
|
||||
FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
|
||||
FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
|
||||
FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
|
||||
FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
|
||||
FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
|
||||
FN_SSI_WS78_B,
|
||||
|
||||
/* IPSR6 */
|
||||
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
|
||||
FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
|
||||
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
|
||||
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
|
||||
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
|
||||
FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
|
||||
FN_SSI_WS6_B, FN_SSI_SDATA8_C,
|
||||
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
|
||||
FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
|
||||
FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
|
||||
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
|
||||
FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
|
||||
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
|
||||
@ -568,23 +568,23 @@ enum {
|
||||
CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
|
||||
CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
|
||||
VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
|
||||
INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
|
||||
WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
|
||||
VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
|
||||
WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
|
||||
VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
|
||||
IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
|
||||
IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
|
||||
VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
|
||||
MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
|
||||
VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
|
||||
SSI_WS78_B_MARK,
|
||||
|
||||
DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
|
||||
DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
|
||||
VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
|
||||
DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
|
||||
SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
|
||||
INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
|
||||
SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
|
||||
DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
|
||||
MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
|
||||
MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
|
||||
SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
|
||||
ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
|
||||
TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
|
||||
@ -1094,7 +1094,6 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
|
||||
PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
|
||||
PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
|
||||
PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
|
||||
PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
|
||||
PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
|
||||
PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
|
||||
@ -1111,7 +1110,6 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
|
||||
PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
|
||||
PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
|
||||
PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
|
||||
PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
|
||||
PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
|
||||
PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
|
||||
@ -1125,7 +1123,6 @@ static const u16 pinmux_data[] = {
|
||||
|
||||
PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
|
||||
PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
|
||||
PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
|
||||
PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
|
||||
PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
|
||||
PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
|
||||
@ -1137,7 +1134,6 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
|
||||
PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
|
||||
PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
|
||||
PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
|
||||
PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
|
||||
PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
|
||||
@ -1146,7 +1142,6 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
|
||||
PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
|
||||
PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
|
||||
PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
|
||||
PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
|
||||
PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
|
||||
@ -2410,29 +2405,14 @@ static const unsigned int mlb_3pin_mux[] = {
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
|
||||
|
||||
/* - MMCIF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int mmc0_data1_pins[] = {
|
||||
/* D[0] */
|
||||
RCAR_GP_PIN(3, 18),
|
||||
};
|
||||
static const unsigned int mmc0_data1_mux[] = {
|
||||
MMC0_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
|
||||
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
|
||||
};
|
||||
static const unsigned int mmc0_data4_mux[] = {
|
||||
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc0_data8_pins[] = {
|
||||
static const unsigned int mmc0_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
|
||||
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
|
||||
RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
};
|
||||
static const unsigned int mmc0_data8_mux[] = {
|
||||
static const unsigned int mmc0_data_mux[] = {
|
||||
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
|
||||
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
|
||||
};
|
||||
@ -2444,29 +2424,14 @@ static const unsigned int mmc0_ctrl_mux[] = {
|
||||
MMC0_CLK_MARK, MMC0_CMD_MARK,
|
||||
};
|
||||
/* - MMCIF1 ----------------------------------------------------------------- */
|
||||
static const unsigned int mmc1_data1_pins[] = {
|
||||
/* D[0] */
|
||||
RCAR_GP_PIN(3, 26),
|
||||
};
|
||||
static const unsigned int mmc1_data1_mux[] = {
|
||||
MMC1_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc1_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
|
||||
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
|
||||
};
|
||||
static const unsigned int mmc1_data4_mux[] = {
|
||||
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc1_data8_pins[] = {
|
||||
static const unsigned int mmc1_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
|
||||
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
|
||||
RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
static const unsigned int mmc1_data8_mux[] = {
|
||||
static const unsigned int mmc1_data_mux[] = {
|
||||
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
|
||||
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
|
||||
};
|
||||
@ -2813,19 +2778,12 @@ static const unsigned int qspi_ctrl_pins[] = {
|
||||
static const unsigned int qspi_ctrl_mux[] = {
|
||||
SPCLK_MARK, SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
};
|
||||
static const unsigned int qspi_data2_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data4_pins[] = {
|
||||
static const unsigned int qspi_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const unsigned int qspi_data4_mux[] = {
|
||||
static const unsigned int qspi_data_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
|
||||
};
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
@ -3322,18 +3280,11 @@ static const unsigned int scif_clk_b_mux[] = {
|
||||
SCIF_CLK_B_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -3358,18 +3309,11 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 10),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
@ -3394,18 +3338,11 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 18),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
@ -3430,18 +3367,11 @@ static const unsigned int sdhi2_wp_mux[] = {
|
||||
SD2_WP_MARK,
|
||||
};
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 26),
|
||||
};
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
|
||||
};
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_ctrl_pins[] = {
|
||||
@ -3679,18 +3609,11 @@ static const unsigned int tpu0_to3_mux[] = {
|
||||
};
|
||||
/* - USB0 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb0_pins[] = {
|
||||
/* PWEN, OVC/VBUS */
|
||||
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
|
||||
/* OVC/VBUS, PWEN */
|
||||
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18),
|
||||
};
|
||||
static const unsigned int usb0_mux[] = {
|
||||
USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
|
||||
};
|
||||
static const unsigned int usb0_ovc_vbus_pins[] = {
|
||||
/* OVC/VBUS */
|
||||
RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
static const unsigned int usb0_ovc_vbus_mux[] = {
|
||||
USB0_OVC_VBUS_MARK,
|
||||
USB0_OVC_VBUS_MARK, USB0_PWEN_MARK,
|
||||
};
|
||||
/* - USB1 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb1_pins[] = {
|
||||
@ -3700,13 +3623,6 @@ static const unsigned int usb1_pins[] = {
|
||||
static const unsigned int usb1_mux[] = {
|
||||
USB1_PWEN_MARK, USB1_OVC_MARK,
|
||||
};
|
||||
static const unsigned int usb1_pwen_pins[] = {
|
||||
/* PWEN */
|
||||
RCAR_GP_PIN(5, 20),
|
||||
};
|
||||
static const unsigned int usb1_pwen_mux[] = {
|
||||
USB1_PWEN_MARK,
|
||||
};
|
||||
/* - USB2 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb2_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
@ -3716,43 +3632,39 @@ static const unsigned int usb2_mux[] = {
|
||||
USB2_PWEN_MARK, USB2_OVC_MARK,
|
||||
};
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin0_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
/* G */
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
/* R */
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
|
||||
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
/* G */
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
/* R */
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
|
||||
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
|
||||
};
|
||||
static const union vin_data vin0_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
/* B */
|
||||
@ -3809,43 +3721,39 @@ static const unsigned int vin0_clk_mux[] = {
|
||||
VI0_CLK_MARK,
|
||||
};
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin1_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
|
||||
/* G */
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
|
||||
/* R */
|
||||
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
|
||||
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
|
||||
/* G */
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
|
||||
/* R */
|
||||
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
|
||||
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const union vin_data vin1_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
|
||||
VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
|
||||
VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
|
||||
VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
|
||||
/* G */
|
||||
VI1_G0_MARK, VI1_G1_MARK,
|
||||
VI1_G2_MARK, VI1_G3_MARK,
|
||||
VI1_G4_MARK, VI1_G5_MARK,
|
||||
VI1_G6_MARK, VI1_G7_MARK,
|
||||
/* R */
|
||||
VI1_R0_MARK, VI1_R1_MARK,
|
||||
VI1_R2_MARK, VI1_R3_MARK,
|
||||
VI1_R4_MARK, VI1_R5_MARK,
|
||||
VI1_R6_MARK, VI1_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
/* B */
|
||||
VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
|
||||
VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
|
||||
VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
|
||||
VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
|
||||
/* G */
|
||||
VI1_G0_MARK, VI1_G1_MARK,
|
||||
VI1_G2_MARK, VI1_G3_MARK,
|
||||
VI1_G4_MARK, VI1_G5_MARK,
|
||||
VI1_G6_MARK, VI1_G7_MARK,
|
||||
/* R */
|
||||
VI1_R0_MARK, VI1_R1_MARK,
|
||||
VI1_R2_MARK, VI1_R3_MARK,
|
||||
VI1_R4_MARK, VI1_R5_MARK,
|
||||
VI1_R6_MARK, VI1_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data18_pins[] = {
|
||||
/* B */
|
||||
@ -3875,43 +3783,39 @@ static const unsigned int vin1_data18_mux[] = {
|
||||
VI1_R4_MARK, VI1_R5_MARK,
|
||||
VI1_R6_MARK, VI1_R7_MARK,
|
||||
};
|
||||
static const union vin_data vin1_data_b_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
/* G */
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
|
||||
/* R */
|
||||
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
|
||||
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
|
||||
},
|
||||
static const unsigned int vin1_data_b_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
/* G */
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
|
||||
/* R */
|
||||
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
|
||||
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const union vin_data vin1_data_b_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
|
||||
VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
|
||||
VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
|
||||
VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
|
||||
/* G */
|
||||
VI1_G0_B_MARK, VI1_G1_B_MARK,
|
||||
VI1_G2_B_MARK, VI1_G3_B_MARK,
|
||||
VI1_G4_B_MARK, VI1_G5_B_MARK,
|
||||
VI1_G6_B_MARK, VI1_G7_B_MARK,
|
||||
/* R */
|
||||
VI1_R0_B_MARK, VI1_R1_B_MARK,
|
||||
VI1_R2_B_MARK, VI1_R3_B_MARK,
|
||||
VI1_R4_B_MARK, VI1_R5_B_MARK,
|
||||
VI1_R6_B_MARK, VI1_R7_B_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_b_mux[] = {
|
||||
/* B */
|
||||
VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
|
||||
VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
|
||||
VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
|
||||
VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
|
||||
/* G */
|
||||
VI1_G0_B_MARK, VI1_G1_B_MARK,
|
||||
VI1_G2_B_MARK, VI1_G3_B_MARK,
|
||||
VI1_G4_B_MARK, VI1_G5_B_MARK,
|
||||
VI1_G6_B_MARK, VI1_G7_B_MARK,
|
||||
/* R */
|
||||
VI1_R0_B_MARK, VI1_R1_B_MARK,
|
||||
VI1_R2_B_MARK, VI1_R3_B_MARK,
|
||||
VI1_R4_B_MARK, VI1_R5_B_MARK,
|
||||
VI1_R6_B_MARK, VI1_R7_B_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data18_b_pins[] = {
|
||||
/* B */
|
||||
@ -3994,43 +3898,39 @@ static const unsigned int vin1_clk_b_mux[] = {
|
||||
VI1_CLK_B_MARK,
|
||||
};
|
||||
/* - VIN2 ----------------------------------------------------------------- */
|
||||
static const union vin_data vin2_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
/* G */
|
||||
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
|
||||
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
/* R */
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
|
||||
},
|
||||
static const unsigned int vin2_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
/* G */
|
||||
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
|
||||
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
/* R */
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
|
||||
};
|
||||
static const union vin_data vin2_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
|
||||
VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
|
||||
VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
|
||||
VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
|
||||
/* G */
|
||||
VI2_G0_MARK, VI2_G1_MARK,
|
||||
VI2_G2_MARK, VI2_G3_MARK,
|
||||
VI2_G4_MARK, VI2_G5_MARK,
|
||||
VI2_G6_MARK, VI2_G7_MARK,
|
||||
/* R */
|
||||
VI2_R0_MARK, VI2_R1_MARK,
|
||||
VI2_R2_MARK, VI2_R3_MARK,
|
||||
VI2_R4_MARK, VI2_R5_MARK,
|
||||
VI2_R6_MARK, VI2_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin2_data_mux[] = {
|
||||
/* B */
|
||||
VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
|
||||
VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
|
||||
VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
|
||||
VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
|
||||
/* G */
|
||||
VI2_G0_MARK, VI2_G1_MARK,
|
||||
VI2_G2_MARK, VI2_G3_MARK,
|
||||
VI2_G4_MARK, VI2_G5_MARK,
|
||||
VI2_G6_MARK, VI2_G7_MARK,
|
||||
/* R */
|
||||
VI2_R0_MARK, VI2_R1_MARK,
|
||||
VI2_R2_MARK, VI2_R3_MARK,
|
||||
VI2_R4_MARK, VI2_R5_MARK,
|
||||
VI2_R6_MARK, VI2_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin2_data18_pins[] = {
|
||||
/* B */
|
||||
@ -4060,18 +3960,6 @@ static const unsigned int vin2_data18_mux[] = {
|
||||
VI2_R4_MARK, VI2_R5_MARK,
|
||||
VI2_R6_MARK, VI2_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin2_g8_pins[] = {
|
||||
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
|
||||
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin2_g8_mux[] = {
|
||||
VI2_G0_MARK, VI2_G1_MARK,
|
||||
VI2_G2_MARK, VI2_G3_MARK,
|
||||
VI2_G4_MARK, VI2_G5_MARK,
|
||||
VI2_G6_MARK, VI2_G7_MARK,
|
||||
};
|
||||
static const unsigned int vin2_sync_pins[] = {
|
||||
RCAR_GP_PIN(1, 16), /* HSYNC */
|
||||
RCAR_GP_PIN(1, 21), /* VSYNC */
|
||||
@ -4223,13 +4111,13 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(intc_irq1),
|
||||
SH_PFC_PIN_GROUP(intc_irq2),
|
||||
SH_PFC_PIN_GROUP(intc_irq3),
|
||||
SH_PFC_PIN_GROUP(mmc0_data1),
|
||||
SH_PFC_PIN_GROUP(mmc0_data4),
|
||||
SH_PFC_PIN_GROUP(mmc0_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc0_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc0_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc1_data1),
|
||||
SH_PFC_PIN_GROUP(mmc1_data4),
|
||||
SH_PFC_PIN_GROUP(mmc1_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc1_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
@ -4279,8 +4167,8 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(pwm5),
|
||||
SH_PFC_PIN_GROUP(pwm6),
|
||||
SH_PFC_PIN_GROUP(qspi_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi_data2),
|
||||
SH_PFC_PIN_GROUP(qspi_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 4),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
@ -4350,23 +4238,23 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(scifb2_data_c),
|
||||
SH_PFC_PIN_GROUP(scif_clk),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
@ -4401,38 +4289,38 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(tpu0_to2),
|
||||
SH_PFC_PIN_GROUP(tpu0_to3),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb0_ovc_vbus),
|
||||
SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
SH_PFC_PIN_GROUP(usb1_pwen),
|
||||
SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
|
||||
SH_PFC_PIN_GROUP(usb2),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 4),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 4),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin1_data18),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 4),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 4),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 4, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_sync_b),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
@ -4441,12 +4329,12 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb_b),
|
||||
SH_PFC_PIN_GROUP(vin1_clk),
|
||||
SH_PFC_PIN_GROUP(vin1_clk_b),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 24),
|
||||
SH_PFC_PIN_GROUP(vin2_data18),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 4),
|
||||
SH_PFC_PIN_GROUP(vin2_g8),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 4),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin2_sync),
|
||||
SH_PFC_PIN_GROUP(vin2_field),
|
||||
SH_PFC_PIN_GROUP(vin2_clkenb),
|
||||
@ -4964,10 +4852,10 @@ static const struct {
|
||||
.common = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(can0),
|
||||
SH_PFC_FUNCTION(can1),
|
||||
SH_PFC_FUNCTION(can_clk),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(du0),
|
||||
SH_PFC_FUNCTION(du1),
|
||||
SH_PFC_FUNCTION(du2),
|
||||
@ -5415,9 +5303,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
|
||||
FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
|
||||
/* IP5_26_24 [3] */
|
||||
FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
|
||||
FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
|
||||
FN_MSIOF0_SCK_B, 0,
|
||||
FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
|
||||
FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
|
||||
/* IP5_23_21 [3] */
|
||||
FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
|
||||
FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
|
||||
@ -5426,7 +5313,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
|
||||
/* IP5_17_15 [3] */
|
||||
FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
|
||||
FN_INTC_IRQ4_N, 0, 0,
|
||||
0, 0, 0,
|
||||
/* IP5_14_13 [2] */
|
||||
FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
|
||||
/* IP5_12_10 [3] */
|
||||
@ -5467,19 +5354,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
|
||||
FN_I2C2_SCL_E, 0,
|
||||
/* IP6_13_11 [3] */
|
||||
FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
|
||||
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
|
||||
FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
|
||||
FN_MSIOF0_RXD_B, 0, 0,
|
||||
/* IP6_10_9 [2] */
|
||||
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
|
||||
/* IP6_8_6 [3] */
|
||||
FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
|
||||
FN_SSI_SDATA8_C, 0, 0, 0,
|
||||
FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
|
||||
/* IP6_5_3 [3] */
|
||||
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
|
||||
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
|
||||
/* IP6_2_0 [3] */
|
||||
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
|
||||
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
|
||||
FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
|
||||
FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
|
||||
GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
|
||||
@ -5987,7 +5873,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
|
||||
return -EINVAL;
|
||||
@ -6289,7 +6175,7 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
|
||||
.init = r8a7790_pinmux_soc_init,
|
||||
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
@ -6299,7 +6185,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7742
|
||||
const struct sh_pfc_soc_info r8a7742_pinmux_info = {
|
||||
.name = "r8a77420_pfc",
|
||||
.ops = &r8a7790_pinmux_ops,
|
||||
.ops = &r8a7790_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
@ -6322,7 +6208,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7790
|
||||
const struct sh_pfc_soc_info r8a7790_pinmux_info = {
|
||||
.name = "r8a77900_pfc",
|
||||
.ops = &r8a7790_pinmux_ops,
|
||||
.ops = &r8a7790_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
@ -234,11 +234,11 @@ enum {
|
||||
FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
|
||||
FN_SCIFA2_RXD, FN_FMIN_E,
|
||||
FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
|
||||
FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
|
||||
FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
|
||||
FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
|
||||
FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
|
||||
FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
|
||||
FN_IRQ0, FN_SCIFB1_RXD_D,
|
||||
FN_IRQ1, FN_SCIFB1_SCK_C,
|
||||
FN_IRQ2, FN_SCIFB1_TXD_D,
|
||||
FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,
|
||||
FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
|
||||
FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
|
||||
FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
|
||||
FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
|
||||
@ -606,12 +606,12 @@ enum {
|
||||
AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
|
||||
SCIFA2_RXD_MARK, FMIN_E_MARK,
|
||||
AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
|
||||
IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
|
||||
IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
|
||||
IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
|
||||
IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
|
||||
IRQ0_MARK, SCIFB1_RXD_D_MARK,
|
||||
IRQ1_MARK, SCIFB1_SCK_C_MARK,
|
||||
IRQ2_MARK, SCIFB1_TXD_D_MARK,
|
||||
IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,
|
||||
IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
|
||||
MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
|
||||
MSIOF2_RXD_E_MARK,
|
||||
IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
|
||||
IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
|
||||
I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
|
||||
@ -1140,22 +1140,17 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
|
||||
PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
|
||||
PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
|
||||
PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
|
||||
PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
|
||||
PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
|
||||
PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
|
||||
PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
|
||||
PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
|
||||
PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
|
||||
PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
|
||||
PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
|
||||
PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
|
||||
PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
|
||||
PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
|
||||
PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
|
||||
PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
|
||||
PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
|
||||
PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
|
||||
PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
|
||||
@ -2303,13 +2298,6 @@ static const unsigned int hscif1_data_d_pins[] = {
|
||||
static const unsigned int hscif1_data_d_mux[] = {
|
||||
HRX1_D_MARK, HTX1_D_MARK,
|
||||
};
|
||||
static const unsigned int hscif1_data_e_pins[] = {
|
||||
/* RX, TX */
|
||||
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
|
||||
};
|
||||
static const unsigned int hscif1_data_e_mux[] = {
|
||||
HRX1_C_MARK, HTX1_C_MARK,
|
||||
};
|
||||
static const unsigned int hscif1_clk_e_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(2, 6),
|
||||
@ -2604,40 +2592,25 @@ static const unsigned int mlb_3pin_mux[] = {
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
|
||||
|
||||
/* - MMCIF ------------------------------------------------------------------ */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* D[0] */
|
||||
RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
|
||||
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_b_pins[] = {
|
||||
static const unsigned int mmc_data_b_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
|
||||
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
|
||||
};
|
||||
static const unsigned int mmc_data8_b_mux[] = {
|
||||
static const unsigned int mmc_data_b_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
|
||||
};
|
||||
@ -3225,19 +3198,12 @@ static const unsigned int qspi_ctrl_pins[] = {
|
||||
static const unsigned int qspi_ctrl_mux[] = {
|
||||
SPCLK_MARK, SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
};
|
||||
static const unsigned int qspi_data2_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data4_pins[] = {
|
||||
static const unsigned int qspi_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const unsigned int qspi_data4_mux[] = {
|
||||
static const unsigned int qspi_data_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
|
||||
};
|
||||
|
||||
@ -3248,19 +3214,12 @@ static const unsigned int qspi_ctrl_b_pins[] = {
|
||||
static const unsigned int qspi_ctrl_b_mux[] = {
|
||||
SPCLK_B_MARK, SSL_B_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data2_b_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
|
||||
};
|
||||
static const unsigned int qspi_data2_b_mux[] = {
|
||||
MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data4_b_pins[] = {
|
||||
static const unsigned int qspi_data_b_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
|
||||
RCAR_GP_PIN(6, 4),
|
||||
};
|
||||
static const unsigned int qspi_data4_b_mux[] = {
|
||||
static const unsigned int qspi_data_b_mux[] = {
|
||||
MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
|
||||
};
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
@ -3821,19 +3780,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
||||
};
|
||||
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
|
||||
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -3858,19 +3810,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
|
||||
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
@ -3895,19 +3840,12 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
@ -4230,43 +4168,39 @@ static const unsigned int usb1_mux[] = {
|
||||
USB1_OVC_MARK,
|
||||
};
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin0_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
|
||||
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
/* G */
|
||||
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
|
||||
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
|
||||
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
|
||||
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
|
||||
/* R */
|
||||
RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
|
||||
RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
|
||||
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
|
||||
RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
|
||||
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
/* G */
|
||||
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
|
||||
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
|
||||
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
|
||||
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
|
||||
/* R */
|
||||
RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
|
||||
RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
|
||||
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
|
||||
RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
|
||||
};
|
||||
static const union vin_data vin0_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
/* B */
|
||||
@ -4361,43 +4295,39 @@ static const unsigned int vin1_clk_pins[] = {
|
||||
static const unsigned int vin1_clk_mux[] = {
|
||||
VI1_CLK_MARK,
|
||||
};
|
||||
static const union vin_data vin1_data_b_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
/* G */
|
||||
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
|
||||
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
|
||||
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
|
||||
RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
|
||||
/* R */
|
||||
RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
},
|
||||
static const unsigned int vin1_data_b_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
/* G */
|
||||
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
|
||||
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
|
||||
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
|
||||
RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
|
||||
/* R */
|
||||
RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
};
|
||||
static const union vin_data vin1_data_b_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
|
||||
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
|
||||
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
|
||||
VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
|
||||
/* G */
|
||||
VI1_G0_B_MARK, VI1_G1_B_MARK,
|
||||
VI1_G2_B_MARK, VI1_G3_B_MARK,
|
||||
VI1_G4_B_MARK, VI1_G5_B_MARK,
|
||||
VI1_G6_B_MARK, VI1_G7_B_MARK,
|
||||
/* R */
|
||||
VI1_R0_B_MARK, VI1_R1_B_MARK,
|
||||
VI1_R2_B_MARK, VI1_R3_B_MARK,
|
||||
VI1_R4_B_MARK, VI1_R5_B_MARK,
|
||||
VI1_R6_B_MARK, VI1_R7_B_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_b_mux[] = {
|
||||
/* B */
|
||||
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
|
||||
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
|
||||
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
|
||||
VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
|
||||
/* G */
|
||||
VI1_G0_B_MARK, VI1_G1_B_MARK,
|
||||
VI1_G2_B_MARK, VI1_G3_B_MARK,
|
||||
VI1_G4_B_MARK, VI1_G5_B_MARK,
|
||||
VI1_G6_B_MARK, VI1_G7_B_MARK,
|
||||
/* R */
|
||||
VI1_R0_B_MARK, VI1_R1_B_MARK,
|
||||
VI1_R2_B_MARK, VI1_R3_B_MARK,
|
||||
VI1_R4_B_MARK, VI1_R5_B_MARK,
|
||||
VI1_R6_B_MARK, VI1_R7_B_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data18_b_pins[] = {
|
||||
/* B */
|
||||
@ -4556,7 +4486,7 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(hscif1_clk_c),
|
||||
SH_PFC_PIN_GROUP(hscif1_ctrl_c),
|
||||
SH_PFC_PIN_GROUP(hscif1_data_d),
|
||||
SH_PFC_PIN_GROUP(hscif1_data_e),
|
||||
SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c),
|
||||
SH_PFC_PIN_GROUP(hscif1_clk_e),
|
||||
SH_PFC_PIN_GROUP(hscif1_ctrl_e),
|
||||
SH_PFC_PIN_GROUP(hscif2_data),
|
||||
@ -4596,10 +4526,10 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(intc_irq1),
|
||||
SH_PFC_PIN_GROUP(intc_irq2),
|
||||
SH_PFC_PIN_GROUP(intc_irq3),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
SH_PFC_PIN_GROUP(mmc_data8_b),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8, _b),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
@ -4683,11 +4613,11 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6),
|
||||
SH_PFC_PIN_GROUP(qspi_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi_data2),
|
||||
SH_PFC_PIN_GROUP(qspi_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(qspi_data2_b),
|
||||
SH_PFC_PIN_GROUP(qspi_data4_b),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 2, _b),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 4, _b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_data_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data_c),
|
||||
@ -4765,18 +4695,18 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(scifb2_data_d),
|
||||
SH_PFC_PIN_GROUP(scif_clk),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp),
|
||||
@ -4814,13 +4744,13 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(tpu_to3),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
@ -4830,13 +4760,13 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin1_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_sync_b),
|
||||
SH_PFC_PIN_GROUP(vin1_field_b),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb_b),
|
||||
@ -6033,15 +5963,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
|
||||
/* IP6_18_16 [3] */
|
||||
FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
|
||||
FN_INTC_IRQ4_N, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
/* IP6_15_14 [2] */
|
||||
FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
|
||||
FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,
|
||||
/* IP6_13_12 [2] */
|
||||
FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
|
||||
FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,
|
||||
/* IP6_11_10 [2] */
|
||||
FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
|
||||
FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,
|
||||
/* IP6_9_8 [2] */
|
||||
FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
|
||||
FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,
|
||||
/* IP6_7_6 [2] */
|
||||
FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
|
||||
/* IP6_5_3 [3] */
|
||||
@ -6672,7 +6602,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
|
||||
return -EINVAL;
|
||||
@ -6994,7 +6924,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
@ -7003,7 +6933,7 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7743
|
||||
const struct sh_pfc_soc_info r8a7743_pinmux_info = {
|
||||
.name = "r8a77430_pfc",
|
||||
.ops = &r8a7791_pinmux_ops,
|
||||
.ops = &r8a7791_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
@ -7026,7 +6956,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7744
|
||||
const struct sh_pfc_soc_info r8a7744_pinmux_info = {
|
||||
.name = "r8a77440_pfc",
|
||||
.ops = &r8a7791_pinmux_ops,
|
||||
.ops = &r8a7791_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
@ -7049,7 +6979,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7791
|
||||
const struct sh_pfc_soc_info r8a7791_pinmux_info = {
|
||||
.name = "r8a77910_pfc",
|
||||
.ops = &r8a7791_pinmux_ops,
|
||||
.ops = &r8a7791_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
@ -7074,7 +7004,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7793
|
||||
const struct sh_pfc_soc_info r8a7793_pinmux_info = {
|
||||
.name = "r8a77930_pfc",
|
||||
.ops = &r8a7791_pinmux_ops,
|
||||
.ops = &r8a7791_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
@ -1116,19 +1116,12 @@ static const unsigned int qspi_ctrl_pins[] = {
|
||||
static const unsigned int qspi_ctrl_mux[] = {
|
||||
SPCLK_MARK, SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
static const unsigned int qspi_data2_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data4_pins[] = {
|
||||
static const unsigned int qspi_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
|
||||
RCAR_GP_PIN(3, 24),
|
||||
};
|
||||
static const unsigned int qspi_data4_mux[] = {
|
||||
static const unsigned int qspi_data_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
|
||||
};
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
@ -1206,19 +1199,12 @@ static const unsigned int scif3_clk_mux[] = {
|
||||
SCK3_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* DAT0 */
|
||||
RCAR_GP_PIN(11, 7),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* DAT[0-3] */
|
||||
RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
|
||||
RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -1243,43 +1229,39 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin0_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
|
||||
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
|
||||
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
|
||||
/* G */
|
||||
RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
|
||||
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
|
||||
RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
|
||||
RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
|
||||
/* R */
|
||||
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
|
||||
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
|
||||
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
|
||||
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
|
||||
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
|
||||
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
|
||||
/* G */
|
||||
RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
|
||||
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
|
||||
RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
|
||||
RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
|
||||
/* R */
|
||||
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
|
||||
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
|
||||
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
|
||||
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
|
||||
};
|
||||
static const union vin_data vin0_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
|
||||
VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
|
||||
VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
|
||||
VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
|
||||
/* G */
|
||||
VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
|
||||
VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
|
||||
VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
|
||||
VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
|
||||
/* R */
|
||||
VI0_D16_R0_MARK, VI0_D17_R1_MARK,
|
||||
VI0_D18_R2_MARK, VI0_D19_R3_MARK,
|
||||
VI0_D20_R4_MARK, VI0_D21_R5_MARK,
|
||||
VI0_D22_R6_MARK, VI0_D23_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
/* B */
|
||||
VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
|
||||
VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
|
||||
VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
|
||||
VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
|
||||
/* G */
|
||||
VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
|
||||
VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
|
||||
VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
|
||||
VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
|
||||
/* R */
|
||||
VI0_D16_R0_MARK, VI0_D17_R1_MARK,
|
||||
VI0_D18_R2_MARK, VI0_D19_R3_MARK,
|
||||
VI0_D20_R4_MARK, VI0_D21_R5_MARK,
|
||||
VI0_D22_R6_MARK, VI0_D23_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
/* B */
|
||||
@ -1335,43 +1317,39 @@ static const unsigned int vin0_clk_mux[] = {
|
||||
VI0_CLK_MARK,
|
||||
};
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin1_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
|
||||
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
|
||||
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
|
||||
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
|
||||
/* G */
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
|
||||
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
|
||||
/* R */
|
||||
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
|
||||
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
|
||||
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
|
||||
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
|
||||
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
|
||||
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
|
||||
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
|
||||
/* G */
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
|
||||
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
|
||||
/* R */
|
||||
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
|
||||
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
|
||||
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
|
||||
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
|
||||
};
|
||||
static const union vin_data vin1_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
|
||||
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
|
||||
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
|
||||
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
|
||||
/* G */
|
||||
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
|
||||
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
|
||||
VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
|
||||
VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
|
||||
/* R */
|
||||
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
|
||||
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
|
||||
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
|
||||
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
/* B */
|
||||
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
|
||||
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
|
||||
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
|
||||
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
|
||||
/* G */
|
||||
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
|
||||
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
|
||||
VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
|
||||
VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
|
||||
/* R */
|
||||
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
|
||||
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
|
||||
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
|
||||
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data18_pins[] = {
|
||||
/* B */
|
||||
@ -1401,43 +1379,39 @@ static const unsigned int vin1_data18_mux[] = {
|
||||
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
|
||||
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
|
||||
};
|
||||
static const union vin_data vin1_data_b_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
|
||||
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
|
||||
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
|
||||
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
|
||||
/* G */
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
|
||||
RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
|
||||
/* R */
|
||||
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
|
||||
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
|
||||
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
|
||||
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
|
||||
},
|
||||
static const unsigned int vin1_data_b_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
|
||||
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
|
||||
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
|
||||
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
|
||||
/* G */
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
|
||||
RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
|
||||
/* R */
|
||||
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
|
||||
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
|
||||
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
|
||||
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
|
||||
};
|
||||
static const union vin_data vin1_data_b_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
|
||||
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
|
||||
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
|
||||
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
|
||||
/* G */
|
||||
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
|
||||
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
|
||||
VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
|
||||
VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
|
||||
/* R */
|
||||
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
|
||||
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
|
||||
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
|
||||
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_b_mux[] = {
|
||||
/* B */
|
||||
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
|
||||
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
|
||||
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
|
||||
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
|
||||
/* G */
|
||||
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
|
||||
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
|
||||
VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
|
||||
VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
|
||||
/* R */
|
||||
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
|
||||
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
|
||||
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
|
||||
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data18_b_pins[] = {
|
||||
/* B */
|
||||
@ -1493,29 +1467,25 @@ static const unsigned int vin1_clk_mux[] = {
|
||||
VI1_CLK_MARK,
|
||||
};
|
||||
/* - VIN2 ------------------------------------------------------------------- */
|
||||
static const union vin_data16 vin2_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
|
||||
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
|
||||
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
|
||||
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
|
||||
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
|
||||
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
|
||||
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
|
||||
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
|
||||
},
|
||||
static const unsigned int vin2_data_pins[] = {
|
||||
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
|
||||
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
|
||||
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
|
||||
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
|
||||
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
|
||||
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
|
||||
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
|
||||
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
|
||||
};
|
||||
static const union vin_data16 vin2_data_mux = {
|
||||
.data16 = {
|
||||
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
|
||||
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
|
||||
VI2_D4_C4_MARK, VI2_D5_C5_MARK,
|
||||
VI2_D6_C6_MARK, VI2_D7_C7_MARK,
|
||||
VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
|
||||
VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
|
||||
VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
|
||||
VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
|
||||
},
|
||||
static const unsigned int vin2_data_mux[] = {
|
||||
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
|
||||
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
|
||||
VI2_D4_C4_MARK, VI2_D5_C5_MARK,
|
||||
VI2_D6_C6_MARK, VI2_D7_C7_MARK,
|
||||
VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
|
||||
VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
|
||||
VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
|
||||
VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
|
||||
};
|
||||
static const unsigned int vin2_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1543,29 +1513,25 @@ static const unsigned int vin2_clk_mux[] = {
|
||||
VI2_CLK_MARK,
|
||||
};
|
||||
/* - VIN3 ------------------------------------------------------------------- */
|
||||
static const union vin_data16 vin3_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
|
||||
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
|
||||
RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
|
||||
RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
|
||||
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
|
||||
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
|
||||
RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
|
||||
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
|
||||
},
|
||||
static const unsigned int vin3_data_pins[] = {
|
||||
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
|
||||
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
|
||||
RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
|
||||
RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
|
||||
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
|
||||
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
|
||||
RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
|
||||
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
|
||||
};
|
||||
static const union vin_data16 vin3_data_mux = {
|
||||
.data16 = {
|
||||
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
|
||||
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
|
||||
VI3_D4_C4_MARK, VI3_D5_C5_MARK,
|
||||
VI3_D6_C6_MARK, VI3_D7_C7_MARK,
|
||||
VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
|
||||
VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
|
||||
VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
|
||||
VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
|
||||
},
|
||||
static const unsigned int vin3_data_mux[] = {
|
||||
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
|
||||
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
|
||||
VI3_D4_C4_MARK, VI3_D5_C5_MARK,
|
||||
VI3_D6_C6_MARK, VI3_D7_C7_MARK,
|
||||
VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
|
||||
VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
|
||||
VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
|
||||
VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
|
||||
};
|
||||
static const unsigned int vin3_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1593,25 +1559,21 @@ static const unsigned int vin3_clk_mux[] = {
|
||||
VI3_CLK_MARK,
|
||||
};
|
||||
/* - VIN4 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin4_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
|
||||
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
|
||||
RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
|
||||
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
|
||||
RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
|
||||
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
|
||||
},
|
||||
static const unsigned int vin4_data_pins[] = {
|
||||
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
|
||||
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
|
||||
RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
|
||||
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
|
||||
RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
|
||||
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
|
||||
};
|
||||
static const union vin_data12 vin4_data_mux = {
|
||||
.data12 = {
|
||||
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
|
||||
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
|
||||
VI4_D4_C4_MARK, VI4_D5_C5_MARK,
|
||||
VI4_D6_C6_MARK, VI4_D7_C7_MARK,
|
||||
VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
|
||||
VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_mux[] = {
|
||||
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
|
||||
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
|
||||
VI4_D4_C4_MARK, VI4_D5_C5_MARK,
|
||||
VI4_D6_C6_MARK, VI4_D7_C7_MARK,
|
||||
VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
|
||||
VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1639,25 +1601,21 @@ static const unsigned int vin4_clk_mux[] = {
|
||||
VI4_CLK_MARK,
|
||||
};
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin5_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
|
||||
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
|
||||
RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
|
||||
RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
|
||||
RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
|
||||
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
|
||||
},
|
||||
static const unsigned int vin5_data_pins[] = {
|
||||
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
|
||||
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
|
||||
RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
|
||||
RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
|
||||
RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
|
||||
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
|
||||
};
|
||||
static const union vin_data12 vin5_data_mux = {
|
||||
.data12 = {
|
||||
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
|
||||
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
|
||||
VI5_D4_C4_MARK, VI5_D5_C5_MARK,
|
||||
VI5_D6_C6_MARK, VI5_D7_C7_MARK,
|
||||
VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
|
||||
VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
|
||||
},
|
||||
static const unsigned int vin5_data_mux[] = {
|
||||
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
|
||||
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
|
||||
VI5_D4_C4_MARK, VI5_D5_C5_MARK,
|
||||
VI5_D6_C6_MARK, VI5_D7_C7_MARK,
|
||||
VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
|
||||
VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
|
||||
};
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1728,8 +1686,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(msiof1_rx),
|
||||
SH_PFC_PIN_GROUP(msiof1_tx),
|
||||
SH_PFC_PIN_GROUP(qspi_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi_data2),
|
||||
SH_PFC_PIN_GROUP(qspi_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 4),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
@ -1740,63 +1698,63 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scif2_clk),
|
||||
SH_PFC_PIN_GROUP(scif3_data),
|
||||
SH_PFC_PIN_GROUP(scif3_clk),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin1_data18),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin1_clk),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin2_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin2_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin2_sync),
|
||||
SH_PFC_PIN_GROUP(vin2_field),
|
||||
SH_PFC_PIN_GROUP(vin2_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin2_clk),
|
||||
VIN_DATA_PIN_GROUP(vin3_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin3_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin3_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin3_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin3_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin3_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin3_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin3_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin3_sync),
|
||||
SH_PFC_PIN_GROUP(vin3_field),
|
||||
SH_PFC_PIN_GROUP(vin3_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin3_clk),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
@ -3281,14 +3239,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7792_pinmux_info = {
|
||||
.name = "r8a77920_pfc",
|
||||
.ops = &r8a7792_pinmux_ops,
|
||||
.ops = &r8a7792_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
@ -2388,29 +2388,14 @@ static const unsigned int intc_irq9_mux[] = {
|
||||
IRQ9_MARK,
|
||||
};
|
||||
/* - MMCIF ------------------------------------------------------------------ */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* D[0] */
|
||||
RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
|
||||
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
|
||||
};
|
||||
@ -2745,19 +2730,12 @@ static const unsigned int qspi_ctrl_pins[] = {
|
||||
static const unsigned int qspi_ctrl_mux[] = {
|
||||
SPCLK_MARK, SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
};
|
||||
static const unsigned int qspi_data2_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data4_pins[] = {
|
||||
static const unsigned int qspi_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const unsigned int qspi_data4_mux[] = {
|
||||
static const unsigned int qspi_data_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
|
||||
};
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
@ -3232,19 +3210,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
||||
SCIF_CLK_B_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
|
||||
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
@ -3269,19 +3240,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
|
||||
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
@ -3306,19 +3270,12 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
@ -3673,43 +3630,39 @@ static const unsigned int usb1_mux[] = {
|
||||
USB1_OVC_MARK,
|
||||
};
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin0_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
|
||||
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
|
||||
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
|
||||
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
|
||||
/* G */
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
|
||||
RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
|
||||
RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
|
||||
/* R */
|
||||
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
|
||||
RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
|
||||
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
|
||||
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
|
||||
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
|
||||
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
|
||||
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
|
||||
/* G */
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
|
||||
RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
|
||||
RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
|
||||
/* R */
|
||||
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
|
||||
RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
|
||||
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
|
||||
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
|
||||
};
|
||||
static const union vin_data vin0_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
/* B */
|
||||
@ -3766,25 +3719,21 @@ static const unsigned int vin0_clk_mux[] = {
|
||||
VI0_CLK_MARK,
|
||||
};
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
|
||||
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
|
||||
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
};
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
RCAR_GP_PIN(5, 22), /* HSYNC */
|
||||
@ -3923,9 +3872,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(intc_irq7),
|
||||
SH_PFC_PIN_GROUP(intc_irq8),
|
||||
SH_PFC_PIN_GROUP(intc_irq9),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
@ -3975,8 +3924,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(pwm6),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi_data2),
|
||||
SH_PFC_PIN_GROUP(qspi_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 4),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_data_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data_c),
|
||||
@ -4042,18 +3991,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scifb2_ctrl),
|
||||
SH_PFC_PIN_GROUP(scif_clk),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp),
|
||||
@ -4105,20 +4054,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(tpu_to3_c),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
@ -5621,8 +5570,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
|
||||
return -EINVAL;
|
||||
|
||||
*pocctrl = 0xe606006c;
|
||||
|
||||
switch (pin & 0x1f) {
|
||||
@ -5932,7 +5884,7 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a7794_pfc_ops = {
|
||||
.init = r8a7794_pinmux_soc_init,
|
||||
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
@ -5942,7 +5894,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7745
|
||||
const struct sh_pfc_soc_info r8a7745_pinmux_info = {
|
||||
.name = "r8a77450_pfc",
|
||||
.ops = &r8a7794_pinmux_ops,
|
||||
.ops = &r8a7794_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
@ -5965,7 +5917,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7794
|
||||
const struct sh_pfc_soc_info r8a7794_pinmux_info = {
|
||||
.name = "r8a77940_pfc",
|
||||
.ops = &r8a7794_pinmux_ops,
|
||||
.ops = &r8a7794_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
@ -3140,18 +3140,11 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
@ -3163,18 +3156,11 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
@ -3395,19 +3381,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
||||
};
|
||||
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK,
|
||||
SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
@ -3433,19 +3412,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 8),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK,
|
||||
SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
@ -3471,30 +3443,14 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 2),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data8_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi2_data8_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
SD2_DAT4_MARK, SD2_DAT5_MARK,
|
||||
@ -3543,30 +3499,14 @@ static const unsigned int sdhi2_ds_mux[] = {
|
||||
SD2_DS_MARK,
|
||||
};
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 9),
|
||||
};
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
};
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data8_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
|
||||
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
static const unsigned int sdhi3_data8_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
SD3_DAT4_MARK, SD3_DAT5_MARK,
|
||||
@ -4103,11 +4043,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_a),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
@ -4137,28 +4077,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scif5_clk),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ds),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
@ -5574,8 +5514,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
@ -5832,7 +5771,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a77950_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
@ -5840,7 +5779,7 @@ static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
|
||||
|
||||
const struct sh_pfc_soc_info r8a77950_pinmux_info = {
|
||||
.name = "r8a77950_pfc",
|
||||
.ops = &r8a77950_pinmux_ops,
|
||||
.ops = &r8a77950_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
@ -3268,20 +3268,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
@ -3293,20 +3286,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
@ -3541,19 +3527,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
||||
};
|
||||
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK,
|
||||
SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
@ -3579,19 +3558,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
||||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 8),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK,
|
||||
SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
@ -3617,30 +3589,14 @@ static const unsigned int sdhi1_wp_mux[] = {
|
||||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 2),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data8_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi2_data8_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
SD2_DAT4_MARK, SD2_DAT5_MARK,
|
||||
@ -3689,30 +3645,14 @@ static const unsigned int sdhi2_ds_mux[] = {
|
||||
SD2_DS_MARK,
|
||||
};
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 9),
|
||||
};
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
};
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data8_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
|
||||
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
static const unsigned int sdhi3_data8_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
SD3_DAT4_MARK, SD3_DAT5_MARK,
|
||||
@ -4071,81 +4011,61 @@ static const unsigned int vin4_data18_b_mux[] = {
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const union vin_data vin4_data_a_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
static const unsigned int vin4_data_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const union vin_data vin4_data_a_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
};
|
||||
static const union vin_data vin4_data_b_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
};
|
||||
static const union vin_data vin4_data_b_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin4_g8_pins[] = {
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin4_g8_mux[] = {
|
||||
static const unsigned int vin4_data_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_data_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int vin4_data_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -4177,37 +4097,21 @@ static const unsigned int vin4_clk_mux[] = {
|
||||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const union vin_data16 vin5_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
},
|
||||
};
|
||||
static const union vin_data16 vin5_data_mux = {
|
||||
.data16 = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin5_high8_pins[] = {
|
||||
static const unsigned int vin5_data_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin5_high8_mux[] = {
|
||||
static const unsigned int vin5_data_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
@ -4449,11 +4353,11 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_a),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
@ -4485,28 +4389,28 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(scif5_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ds),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
@ -4549,30 +4453,30 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(usb2),
|
||||
SH_PFC_PIN_GROUP(usb2_ch3),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_g8),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 16),
|
||||
SH_PFC_PIN_GROUP(vin5_high8),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 16),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
@ -6058,8 +5962,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
|
||||
unsigned int pin, u32 *pocctrl)
|
||||
static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
@ -6316,7 +6219,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
@ -6325,7 +6228,7 @@ static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
|
||||
const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
|
||||
.name = "r8a774e1_pfc",
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.ops = &r8a77951_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
@ -6350,7 +6253,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
const struct sh_pfc_soc_info r8a77951_pinmux_info = {
|
||||
.name = "r8a77951_pfc",
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.ops = &r8a77951_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user