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dt-bindings: net: tsnep: Allow dma-coherent

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Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.

Add "dma-coherent" property to allow the configuration of cache coherent
DMA.

Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Gerhard Engleder 2022-09-27 21:58:37 +02:00 committed by David S. Miller
parent d742ea6b8e
commit ff46c610ab
1 changed files with 2 additions and 0 deletions
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Documentation/devicetree/bindings/net/engleder,tsnep.yaml
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@ -22,6 +22,8 @@ properties:
interrupts:
maxItems: 1
dma-coherent: true
local-mac-address: true
mac-address: true