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synced 2024-11-17 01:04:19 +08:00
Merge branch 'remotes/lorenzo/pci/dwc'
- Use dmam_alloc_coherent() instead of dma_map_page() to allocate the MSI target page, which means dwc drivers will work even when ZONE_DMA32 is disabled (Will McVicker) - If we can't allocate an MSI target page with a 32-bit address, try allocating one with a 64-bit address (Will McVicker) - Switch from of_gpio_named_count() to generic gpiod_count() (Andy Shevchenko) - Add support for i.MX8MP PCIe (Richard Zhu) - Fix the Freescale i.MX8 PHY driver, which had interchanged the phy_init() and phy_power_on() interfaces (Richard Zhu) * remotes/lorenzo/pci/dwc: phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on() PCI: imx6: Add i.MX8MP PCIe support PCI: dwc: Replace of_gpio_named_count() by gpiod_count() PCI: dwc: Drop dependency on ZONE_DMA32
This commit is contained in:
commit
fefb75d842
@ -51,6 +51,7 @@ enum imx6_pcie_variants {
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IMX7D,
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IMX8MQ,
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IMX8MM,
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IMX8MP,
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};
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#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
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@ -61,6 +62,7 @@ struct imx6_pcie_drvdata {
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enum imx6_pcie_variants variant;
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u32 flags;
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int dbi_length;
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const char *gpr;
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};
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struct imx6_pcie {
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@ -150,7 +152,8 @@ struct imx6_pcie {
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static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
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{
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WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
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imx6_pcie->drvdata->variant != IMX8MM);
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imx6_pcie->drvdata->variant != IMX8MM &&
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imx6_pcie->drvdata->variant != IMX8MP);
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return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
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}
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@ -301,6 +304,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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case IMX8MP:
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/*
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* The PHY initialization had been done in the PHY
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* driver, break here directly.
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@ -558,6 +562,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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break;
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case IMX8MM:
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case IMX8MQ:
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case IMX8MP:
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ret = clk_prepare_enable(imx6_pcie->pcie_aux);
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if (ret) {
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dev_err(dev, "unable to enable pcie_aux clock\n");
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@ -602,6 +607,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
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break;
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case IMX8MM:
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case IMX8MQ:
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case IMX8MP:
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clk_disable_unprepare(imx6_pcie->pcie_aux);
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break;
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default:
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@ -669,6 +675,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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reset_control_assert(imx6_pcie->pciephy_reset);
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fallthrough;
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case IMX8MM:
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case IMX8MP:
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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case IMX6SX:
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@ -744,6 +751,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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break;
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case IMX6Q: /* Nothing to do */
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case IMX8MM:
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case IMX8MP:
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break;
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}
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@ -793,6 +801,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
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case IMX7D:
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case IMX8MQ:
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case IMX8MM:
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case IMX8MP:
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reset_control_deassert(imx6_pcie->apps_reset);
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break;
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}
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@ -812,6 +821,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
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case IMX7D:
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case IMX8MQ:
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case IMX8MM:
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case IMX8MP:
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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}
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@ -935,7 +945,7 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
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}
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if (imx6_pcie->phy) {
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ret = phy_power_on(imx6_pcie->phy);
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ret = phy_init(imx6_pcie->phy);
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if (ret) {
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dev_err(dev, "pcie PHY power up failed\n");
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goto err_clk_disable;
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@ -949,7 +959,7 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
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}
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if (imx6_pcie->phy) {
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ret = phy_init(imx6_pcie->phy);
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ret = phy_power_on(imx6_pcie->phy);
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if (ret) {
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dev_err(dev, "waiting for PHY ready timeout!\n");
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goto err_phy_off;
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@ -961,7 +971,7 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
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err_phy_off:
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if (imx6_pcie->phy)
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phy_power_off(imx6_pcie->phy);
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phy_exit(imx6_pcie->phy);
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err_clk_disable:
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imx6_pcie_clk_disable(imx6_pcie);
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err_reg_disable:
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@ -1179,6 +1189,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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}
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break;
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case IMX8MM:
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case IMX8MP:
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imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(imx6_pcie->pcie_aux))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
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@ -1216,7 +1227,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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/* Grab GPR config register range */
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imx6_pcie->iomuxc_gpr =
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syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
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syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
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if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
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dev_err(dev, "unable to find iomuxc registers\n");
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return PTR_ERR(imx6_pcie->iomuxc_gpr);
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@ -1295,12 +1306,14 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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.flags = IMX6_PCIE_FLAG_IMX6_PHY |
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IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
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.dbi_length = 0x200,
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.gpr = "fsl,imx6q-iomuxc-gpr",
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},
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[IMX6SX] = {
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.variant = IMX6SX,
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.flags = IMX6_PCIE_FLAG_IMX6_PHY |
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IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
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IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx6q-iomuxc-gpr",
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},
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[IMX6QP] = {
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.variant = IMX6QP,
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@ -1308,17 +1321,26 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
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IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.dbi_length = 0x200,
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.gpr = "fsl,imx6q-iomuxc-gpr",
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},
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[IMX7D] = {
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.variant = IMX7D,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx7d-iomuxc-gpr",
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},
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[IMX8MQ] = {
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.variant = IMX8MQ,
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.gpr = "fsl,imx8mq-iomuxc-gpr",
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},
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[IMX8MM] = {
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.variant = IMX8MM,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx8mm-iomuxc-gpr",
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},
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[IMX8MP] = {
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.variant = IMX8MP,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx8mp-iomuxc-gpr",
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},
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};
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@ -1329,6 +1351,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
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{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
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{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
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{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
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{},
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};
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@ -267,15 +267,6 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
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irq_domain_remove(pp->msi_domain);
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irq_domain_remove(pp->irq_domain);
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if (pp->msi_data) {
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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dma_unmap_page(dev, pp->msi_data, PAGE_SIZE, DMA_FROM_DEVICE);
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if (pp->msi_page)
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__free_page(pp->msi_page);
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}
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}
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static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
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@ -336,6 +327,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct platform_device *pdev = to_platform_device(dev);
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u64 *msi_vaddr;
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int ret;
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u32 ctrl, num_ctrls;
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@ -375,22 +367,16 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
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dw_chained_msi_isr, pp);
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}
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ret = dma_set_mask(dev, DMA_BIT_MASK(32));
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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if (ret)
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dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
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pp->msi_page = alloc_page(GFP_DMA32);
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pp->msi_data = dma_map_page(dev, pp->msi_page, 0,
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PAGE_SIZE, DMA_FROM_DEVICE);
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ret = dma_mapping_error(dev, pp->msi_data);
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if (ret) {
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dev_err(pci->dev, "Failed to map MSI data\n");
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__free_page(pp->msi_page);
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pp->msi_page = NULL;
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pp->msi_data = 0;
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msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
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GFP_KERNEL);
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if (!msi_vaddr) {
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dev_err(dev, "Failed to alloc and map MSI data\n");
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dw_pcie_free_msi(pp);
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return ret;
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return -ENOMEM;
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}
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return 0;
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@ -243,7 +243,6 @@ struct dw_pcie_rp {
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struct irq_domain *irq_domain;
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struct irq_domain *msi_domain;
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dma_addr_t msi_data;
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struct page *msi_page;
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struct irq_chip *msi_irq_chip;
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u32 num_vectors;
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u32 irq_mask[MAX_MSI_CTRLS];
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@ -13,6 +13,7 @@
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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@ -366,12 +367,11 @@ static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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char name[32];
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int ret, i;
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/* This is an optional property */
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ret = of_gpio_named_count(np, "hisilicon,clken-gpios");
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ret = gpiod_count(dev, "hisilicon,clken");
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if (ret < 0)
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return 0;
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@ -59,7 +59,7 @@ struct imx8_pcie_phy {
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bool clkreq_unused;
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};
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static int imx8_pcie_phy_init(struct phy *phy)
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static int imx8_pcie_phy_power_on(struct phy *phy)
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{
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int ret;
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u32 val, pad_mode;
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@ -137,14 +137,14 @@ static int imx8_pcie_phy_init(struct phy *phy)
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return ret;
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}
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static int imx8_pcie_phy_power_on(struct phy *phy)
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static int imx8_pcie_phy_init(struct phy *phy)
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{
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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return clk_prepare_enable(imx8_phy->clk);
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}
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static int imx8_pcie_phy_power_off(struct phy *phy)
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static int imx8_pcie_phy_exit(struct phy *phy)
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{
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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@ -155,8 +155,8 @@ static int imx8_pcie_phy_power_off(struct phy *phy)
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static const struct phy_ops imx8_pcie_phy_ops = {
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.init = imx8_pcie_phy_init,
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.exit = imx8_pcie_phy_exit,
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.power_on = imx8_pcie_phy_power_on,
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.power_off = imx8_pcie_phy_power_off,
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.owner = THIS_MODULE,
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};
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