Merge 4.13-rc5 into usb-next
This gets the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
@ -237,6 +237,14 @@ are the following:
|
||||
This attribute is not present if the scaling driver in use does not
|
||||
support it.
|
||||
|
||||
``cpuinfo_cur_freq``
|
||||
Current frequency of the CPUs belonging to this policy as obtained from
|
||||
the hardware (in KHz).
|
||||
|
||||
This is expected to be the frequency the hardware actually runs at.
|
||||
If that frequency cannot be determined, this attribute should not
|
||||
be present.
|
||||
|
||||
``cpuinfo_max_freq``
|
||||
Maximum possible operating frequency the CPUs belonging to this policy
|
||||
can run at (in kHz).
|
||||
|
@ -343,3 +343,4 @@ Version History
|
||||
1.11.0 Fix table line argument order
|
||||
(wrong raid10_copies/raid10_format sequence)
|
||||
1.11.1 Add raid4/5/6 journal write-back support via journal_mode option
|
||||
1.12.1 fix for MD deadlock between mddev_suspend() and md_write_start() available
|
||||
|
@ -1,14 +1,22 @@
|
||||
* Renesas R-Car SATA
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one of the following:
|
||||
- compatible : should contain one or more of the following:
|
||||
- "renesas,sata-r8a7779" for R-Car H1
|
||||
("renesas,rcar-sata" is deprecated)
|
||||
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
||||
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
||||
- "renesas,sata-r8a7791" for R-Car M2-W
|
||||
- "renesas,sata-r8a7793" for R-Car M2-N
|
||||
- "renesas,sata-r8a7795" for R-Car H3
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
|
||||
- "renesas,rcar-sata" is deprecated
|
||||
|
||||
When compatible with the generic version nodes
|
||||
must list the SoC-specific version corresponding
|
||||
to the platform first followed by the generic
|
||||
version.
|
||||
|
||||
- reg : address and length of the SATA registers;
|
||||
- interrupts : must consist of one interrupt specifier.
|
||||
- clocks : must contain a reference to the functional clock.
|
||||
@ -16,7 +24,7 @@ Required properties:
|
||||
Example:
|
||||
|
||||
sata0: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7791";
|
||||
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -8,7 +8,6 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- clocks: Reference to the crypto engine clock.
|
||||
- dma-mask: The address mask limitation. Defaults to 64.
|
||||
|
||||
Example:
|
||||
|
||||
@ -24,6 +23,5 @@ Example:
|
||||
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
||||
"eip";
|
||||
clocks = <&cpm_syscon0 1 26>;
|
||||
dma-mask = <0xff 0xffffffff>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
5
Documentation/devicetree/bindings/gpio/gpio-exar.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Exportable MPIO interface of Exar UART chips
|
||||
|
||||
Required properties of the device:
|
||||
- exar,first-pin: first exportable pins (0..15)
|
||||
- ngpios: number of exportable pins (1..16)
|
@ -40,7 +40,7 @@ Optional properties:
|
||||
Example for a Mali-T760:
|
||||
|
||||
gpu@ffa30000 {
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
|
||||
reg = <0xffa30000 0x10000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -78,7 +78,6 @@ Example:
|
||||
};
|
||||
|
||||
dwmmc0@12200000 {
|
||||
num-slots = <1>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
broken-cd;
|
||||
|
@ -24,6 +24,5 @@ Example:
|
||||
|
||||
fifo-depth = <0x20>;
|
||||
bus-width = <4>;
|
||||
num-slots = <1>;
|
||||
disable-wp;
|
||||
};
|
||||
|
@ -36,7 +36,6 @@ Example:
|
||||
|
||||
/* Board portion */
|
||||
dwmmc0@fcd03000 {
|
||||
num-slots = <1>;
|
||||
vmmc-supply = <&ldo12>;
|
||||
fifo-depth = <0x100>;
|
||||
pinctrl-names = "default";
|
||||
@ -52,7 +51,6 @@ Example:
|
||||
|
||||
dwmmc_1: dwmmc1@f723e000 {
|
||||
compatible = "hisilicon,hi6220-dw-mshc";
|
||||
num-slots = <0x1>;
|
||||
bus-width = <0x4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
|
@ -12,12 +12,12 @@ Required Properties:
|
||||
* #address-cells: should be 1.
|
||||
* #size-cells: should be 0.
|
||||
|
||||
# Slots: The slot specific information are contained within child-nodes with
|
||||
each child-node representing a supported slot. There should be atleast one
|
||||
child node representing a card slot. The name of the child node representing
|
||||
the slot is recommended to be slot@n where n is the unique number of the slot
|
||||
connected to the controller. The following are optional properties which
|
||||
can be included in the slot child node.
|
||||
# Slots (DEPRECATED): The slot specific information are contained within
|
||||
child-nodes with each child-node representing a supported slot. There should
|
||||
be atleast one child node representing a card slot. The name of the child node
|
||||
representing the slot is recommended to be slot@n where n is the unique number
|
||||
of the slot connected to the controller. The following are optional properties
|
||||
which can be included in the slot child node.
|
||||
|
||||
* reg: specifies the physical slot number. The valid values of this
|
||||
property is 0 to (num-slots -1), where num-slots is the value
|
||||
@ -63,7 +63,7 @@ Optional properties:
|
||||
clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
|
||||
(Use the "max-frequency" instead of "clock-freq-min-max".)
|
||||
|
||||
* num-slots: specifies the number of slots supported by the controller.
|
||||
* num-slots (DEPRECATED): specifies the number of slots supported by the controller.
|
||||
The number of physical slots actually used could be equal or less than the
|
||||
value specified by num-slots. If this property is not specified, the value
|
||||
of num-slot property is assumed to be 1.
|
||||
@ -124,7 +124,6 @@ board specific portions as listed below.
|
||||
dwmmc0@12200000 {
|
||||
clock-frequency = <400000000>;
|
||||
clock-freq-min-max = <400000 200000000>;
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
@ -139,7 +138,6 @@ board specific portions as listed below.
|
||||
dwmmc0@12200000 {
|
||||
clock-frequency = <400000000>;
|
||||
clock-freq-min-max = <400000 200000000>;
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
|
@ -25,7 +25,6 @@ Example:
|
||||
clock-frequency = <50000000>;
|
||||
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
|
||||
clock-names = "biu", "ciu";
|
||||
num-slots = <1>;
|
||||
max-frequency = <50000000>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
|
@ -27,5 +27,11 @@ You have to add the following kernel parameters in your elilo.conf:
|
||||
Macbook Pro 17", iMac 20" :
|
||||
video=efifb:i20
|
||||
|
||||
Accepted options:
|
||||
|
||||
nowc Don't map the framebuffer write combined. This can be used
|
||||
to workaround side-effects and slowdowns on other CPU cores
|
||||
when large amounts of console data are written.
|
||||
|
||||
--
|
||||
Edgar Hucek <gimli@dark-green.com>
|
||||
|
@ -459,7 +459,7 @@ pin controller?
|
||||
|
||||
This is done by registering "ranges" of pins, which are essentially
|
||||
cross-reference tables. These are described in
|
||||
Documentation/pinctrl.txt
|
||||
Documentation/driver-api/pinctl.rst
|
||||
|
||||
While the pin allocation is totally managed by the pinctrl subsystem,
|
||||
gpio (under gpiolib) is still maintained by gpio drivers. It may happen
|
||||
|
@ -1,6 +1,31 @@
|
||||
Digital TV (DVB) devices
|
||||
------------------------
|
||||
|
||||
Digital TV devices are implemented by several different drivers:
|
||||
|
||||
- A bridge driver that is responsible to talk with the bus where the other
|
||||
devices are connected (PCI, USB, SPI), bind to the other drivers and
|
||||
implement the digital demux logic (either in software or in hardware);
|
||||
|
||||
- Frontend drivers that are usually implemented as two separate drivers:
|
||||
|
||||
- A tuner driver that implements the logic with commands the part of the
|
||||
hardware with is reponsible to tune into a digital TV transponder or
|
||||
physical channel. The output of a tuner is usually a baseband or
|
||||
Intermediate Frequency (IF) signal;
|
||||
|
||||
- A demodulator driver (a.k.a "demod") that implements the logic with
|
||||
commands the digital TV decoding hardware. The output of a demod is
|
||||
a digital stream, with multiple audio, video and data channels typically
|
||||
multiplexed using MPEG Transport Stream [#f1]_.
|
||||
|
||||
On most hardware, the frontend drivers talk with the bridge driver using an
|
||||
I2C bus.
|
||||
|
||||
.. [#f1] Some standards use TCP/IP for multiplexing data, like DVB-H (an
|
||||
abandoned standard, not used anymore) and ATSC version 3.0 current
|
||||
proposals. Currently, the DVB subsystem doesn't implement those standards.
|
||||
|
||||
Digital TV Common functions
|
||||
---------------------------
|
||||
|
||||
@ -55,8 +80,141 @@ Digital TV Frontend
|
||||
The Digital TV Frontend kABI defines a driver-internal interface for
|
||||
registering low-level, hardware specific driver to a hardware independent
|
||||
frontend layer. It is only of interest for Digital TV device driver writers.
|
||||
The header file for this API is named dvb_frontend.h and located in
|
||||
drivers/media/dvb-core.
|
||||
The header file for this API is named ``dvb_frontend.h`` and located in
|
||||
``drivers/media/dvb-core``.
|
||||
|
||||
Demodulator driver
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The demodulator driver is responsible to talk with the decoding part of the
|
||||
hardware. Such driver should implement :c:type:`dvb_frontend_ops`, with
|
||||
tells what type of digital TV standards are supported, and points to a
|
||||
series of functions that allow the DVB core to command the hardware via
|
||||
the code under ``drivers/media/dvb-core/dvb_frontend.c``.
|
||||
|
||||
A typical example of such struct in a driver ``foo`` is::
|
||||
|
||||
static struct dvb_frontend_ops foo_ops = {
|
||||
.delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
|
||||
.info = {
|
||||
.name = "foo DVB-T/T2/C driver",
|
||||
.caps = FE_CAN_FEC_1_2 |
|
||||
FE_CAN_FEC_2_3 |
|
||||
FE_CAN_FEC_3_4 |
|
||||
FE_CAN_FEC_5_6 |
|
||||
FE_CAN_FEC_7_8 |
|
||||
FE_CAN_FEC_AUTO |
|
||||
FE_CAN_QPSK |
|
||||
FE_CAN_QAM_16 |
|
||||
FE_CAN_QAM_32 |
|
||||
FE_CAN_QAM_64 |
|
||||
FE_CAN_QAM_128 |
|
||||
FE_CAN_QAM_256 |
|
||||
FE_CAN_QAM_AUTO |
|
||||
FE_CAN_TRANSMISSION_MODE_AUTO |
|
||||
FE_CAN_GUARD_INTERVAL_AUTO |
|
||||
FE_CAN_HIERARCHY_AUTO |
|
||||
FE_CAN_MUTE_TS |
|
||||
FE_CAN_2G_MODULATION,
|
||||
.frequency_min = 42000000, /* Hz */
|
||||
.frequency_max = 1002000000, /* Hz */
|
||||
.symbol_rate_min = 870000,
|
||||
.symbol_rate_max = 11700000
|
||||
},
|
||||
.init = foo_init,
|
||||
.sleep = foo_sleep,
|
||||
.release = foo_release,
|
||||
.set_frontend = foo_set_frontend,
|
||||
.get_frontend = foo_get_frontend,
|
||||
.read_status = foo_get_status_and_stats,
|
||||
.tune = foo_tune,
|
||||
.i2c_gate_ctrl = foo_i2c_gate_ctrl,
|
||||
.get_frontend_algo = foo_get_algo,
|
||||
};
|
||||
|
||||
A typical example of such struct in a driver ``bar`` meant to be used on
|
||||
Satellite TV reception is::
|
||||
|
||||
static const struct dvb_frontend_ops bar_ops = {
|
||||
.delsys = { SYS_DVBS, SYS_DVBS2 },
|
||||
.info = {
|
||||
.name = "Bar DVB-S/S2 demodulator",
|
||||
.frequency_min = 500000, /* KHz */
|
||||
.frequency_max = 2500000, /* KHz */
|
||||
.frequency_stepsize = 0,
|
||||
.symbol_rate_min = 1000000,
|
||||
.symbol_rate_max = 45000000,
|
||||
.symbol_rate_tolerance = 500,
|
||||
.caps = FE_CAN_INVERSION_AUTO |
|
||||
FE_CAN_FEC_AUTO |
|
||||
FE_CAN_QPSK,
|
||||
},
|
||||
.init = bar_init,
|
||||
.sleep = bar_sleep,
|
||||
.release = bar_release,
|
||||
.set_frontend = bar_set_frontend,
|
||||
.get_frontend = bar_get_frontend,
|
||||
.read_status = bar_get_status_and_stats,
|
||||
.i2c_gate_ctrl = bar_i2c_gate_ctrl,
|
||||
.get_frontend_algo = bar_get_algo,
|
||||
.tune = bar_tune,
|
||||
|
||||
/* Satellite-specific */
|
||||
.diseqc_send_master_cmd = bar_send_diseqc_msg,
|
||||
.diseqc_send_burst = bar_send_burst,
|
||||
.set_tone = bar_set_tone,
|
||||
.set_voltage = bar_set_voltage,
|
||||
};
|
||||
|
||||
.. note::
|
||||
|
||||
#) For satellite digital TV standards (DVB-S, DVB-S2, ISDB-S), the
|
||||
frequencies are specified in kHz, while, for terrestrial and cable
|
||||
standards, they're specified in Hz. Due to that, if the same frontend
|
||||
supports both types, you'll need to have two separate
|
||||
:c:type:`dvb_frontend_ops` structures, one for each standard.
|
||||
#) The ``.i2c_gate_ctrl`` field is present only when the hardware has
|
||||
allows controlling an I2C gate (either directly of via some GPIO pin),
|
||||
in order to remove the tuner from the I2C bus after a channel is
|
||||
tuned.
|
||||
#) All new drivers should implement the
|
||||
:ref:`DVBv5 statistics <dvbv5_stats>` via ``.read_status``.
|
||||
Yet, there are a number of callbacks meant to get statistics for
|
||||
signal strength, S/N and UCB. Those are there to provide backward
|
||||
compatibility with legacy applications that don't support the DVBv5
|
||||
API. Implementing those callbacks are optional. Those callbacks may be
|
||||
removed in the future, after we have all existing drivers supporting
|
||||
DVBv5 stats.
|
||||
#) Other callbacks are required for satellite TV standards, in order to
|
||||
control LNBf and DiSEqC: ``.diseqc_send_master_cmd``,
|
||||
``.diseqc_send_burst``, ``.set_tone``, ``.set_voltage``.
|
||||
|
||||
.. |delta| unicode:: U+00394
|
||||
|
||||
The ``drivers/media/dvb-core/dvb_frontend.c`` has a kernel thread with is
|
||||
responsible for tuning the device. It supports multiple algoritms to
|
||||
detect a channel, as defined at enum :c:func:`dvbfe_algo`.
|
||||
|
||||
The algorithm to be used is obtained via ``.get_frontend_algo``. If the driver
|
||||
doesn't fill its field at struct :c:type:`dvb_frontend_ops`, it will default to
|
||||
``DVBFE_ALGO_SW``, meaning that the dvb-core will do a zigzag when tuning,
|
||||
e. g. it will try first to use the specified center frequency ``f``,
|
||||
then, it will do ``f`` + |delta|, ``f`` - |delta|, ``f`` + 2 x |delta|,
|
||||
``f`` - 2 x |delta| and so on.
|
||||
|
||||
If the hardware has internally a some sort of zigzag algorithm, you should
|
||||
define a ``.get_frontend_algo`` function that would return ``DVBFE_ALGO_HW``.
|
||||
|
||||
.. note::
|
||||
|
||||
The core frontend support also supports
|
||||
a third type (``DVBFE_ALGO_CUSTOM``), in order to allow the driver to
|
||||
define its own hardware-assisted algorithm. Very few hardware need to
|
||||
use it nowadays. Using ``DVBFE_ALGO_CUSTOM`` require to provide other
|
||||
function callbacks at struct :c:type:`dvb_frontend_ops`.
|
||||
|
||||
Attaching frontend driver to the bridge driver
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Before using the Digital TV frontend core, the bridge driver should attach
|
||||
the frontend demod, tuner and SEC devices and call
|
||||
@ -74,6 +232,287 @@ part of their handler for :c:type:`device_driver`.\ ``resume()``.
|
||||
|
||||
A few other optional functions are provided to handle some special cases.
|
||||
|
||||
.. _dvbv5_stats:
|
||||
|
||||
Digital TV Frontend statistics
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Introduction
|
||||
^^^^^^^^^^^^
|
||||
|
||||
Digital TV frontends provide a range of
|
||||
:ref:`statistics <frontend-stat-properties>` meant to help tuning the device
|
||||
and measuring the quality of service.
|
||||
|
||||
For each statistics measurement, the driver should set the type of scale used,
|
||||
or ``FE_SCALE_NOT_AVAILABLE`` if the statistics is not available on a given
|
||||
time. Drivers should also provide the number of statistics for each type.
|
||||
that's usually 1 for most video standards [#f2]_.
|
||||
|
||||
Drivers should initialize each statistic counters with length and
|
||||
scale at its init code. For example, if the frontend provides signal
|
||||
strength, it should have, on its init code::
|
||||
|
||||
struct dtv_frontend_properties *c = &state->fe.dtv_property_cache;
|
||||
|
||||
c->strength.len = 1;
|
||||
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
|
||||
|
||||
And, when the statistics got updated, set the scale::
|
||||
|
||||
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
c->strength.stat[0].uvalue = strength;
|
||||
|
||||
.. [#f2] For ISDB-T, it may provide both a global statistics and a per-layer
|
||||
set of statistics. On such cases, len should be equal to 4. The first
|
||||
value corresponds to the global stat; the other ones to each layer, e. g.:
|
||||
|
||||
- c->cnr.stat[0] for global S/N carrier ratio,
|
||||
- c->cnr.stat[1] for Layer A S/N carrier ratio,
|
||||
- c->cnr.stat[2] for layer B S/N carrier ratio,
|
||||
- c->cnr.stat[3] for layer C S/N carrier ratio.
|
||||
|
||||
.. note:: Please prefer to use ``FE_SCALE_DECIBEL`` instead of
|
||||
``FE_SCALE_RELATIVE`` for signal strength and CNR measurements.
|
||||
|
||||
Groups of statistics
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
There are several groups of statistics currently supported:
|
||||
|
||||
Signal strength (:ref:`DTV-STAT-SIGNAL-STRENGTH`)
|
||||
- Measures the signal strength level at the analog part of the tuner or
|
||||
demod.
|
||||
|
||||
- Typically obtained from the gain applied to the tuner and/or frontend
|
||||
in order to detect the carrier. When no carrier is detected, the gain is
|
||||
at the maximum value (so, strength is on its minimal).
|
||||
|
||||
- As the gain is visible through the set of registers that adjust the gain,
|
||||
typically, this statistics is always available [#f3]_.
|
||||
|
||||
- Drivers should try to make it available all the times, as this statistics
|
||||
can be used when adjusting an antenna position and to check for troubles
|
||||
at the cabling.
|
||||
|
||||
.. [#f3] On a few devices, the gain keeps floating if no carrier.
|
||||
On such devices, strength report should check first if carrier is
|
||||
detected at the tuner (``FE_HAS_CARRIER``, see :c:type:`fe_status`),
|
||||
and otherwise return the lowest possible value.
|
||||
|
||||
Carrier Signal to Noise ratio (:ref:`DTV-STAT-CNR`)
|
||||
- Signal to Noise ratio for the main carrier.
|
||||
|
||||
- Signal to Noise measurement depends on the device. On some hardware, is
|
||||
available when the main carrier is detected. On those hardware, CNR
|
||||
measurement usually comes from the tuner (e. g. after ``FE_HAS_CARRIER``,
|
||||
see :c:type:`fe_status`).
|
||||
|
||||
On other devices, it requires inner FEC decoding,
|
||||
as the frontend measures it indirectly from other parameters (e. g. after
|
||||
``FE_HAS_VITERBI``, see :c:type:`fe_status`).
|
||||
|
||||
Having it available after inner FEC is more common.
|
||||
|
||||
Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POST-TOTAL-BIT-COUNT`)
|
||||
- Those counters measure the number of bits and bit errors errors after
|
||||
the forward error correction (FEC) on the inner coding block
|
||||
(after Viterbi, LDPC or other inner code).
|
||||
|
||||
- Due to its nature, those statistics depend on full coding lock
|
||||
(e. g. after ``FE_HAS_SYNC`` or after ``FE_HAS_LOCK``,
|
||||
see :c:type:`fe_status`).
|
||||
|
||||
Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-TOTAL-BIT-COUNT`)
|
||||
- Those counters measure the number of bits and bit errors errors before
|
||||
the forward error correction (FEC) on the inner coding block
|
||||
(before Viterbi, LDPC or other inner code).
|
||||
|
||||
- Not all frontends provide this kind of statistics.
|
||||
|
||||
- Due to its nature, those statistics depend on inner coding lock (e. g.
|
||||
after ``FE_HAS_VITERBI``, see :c:type:`fe_status`).
|
||||
|
||||
Block counts (:ref:`DTV-STAT-ERROR-BLOCK-COUNT` and :ref:`DTV-STAT-TOTAL-BLOCK-COUNT`)
|
||||
- Those counters measure the number of blocks and block errors errors after
|
||||
the forward error correction (FEC) on the inner coding block
|
||||
(before Viterbi, LDPC or other inner code).
|
||||
|
||||
- Due to its nature, those statistics depend on full coding lock
|
||||
(e. g. after ``FE_HAS_SYNC`` or after
|
||||
``FE_HAS_LOCK``, see :c:type:`fe_status`).
|
||||
|
||||
.. note:: All counters should be monotonically increased as they're
|
||||
collected from the hardware.
|
||||
|
||||
A typical example of the logic that handle status and statistics is::
|
||||
|
||||
static int foo_get_status_and_stats(struct dvb_frontend *fe)
|
||||
{
|
||||
struct foo_state *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||||
|
||||
int rc;
|
||||
enum fe_status *status;
|
||||
|
||||
/* Both status and strength are always available */
|
||||
rc = foo_read_status(fe, &status);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
rc = foo_read_strength(fe);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* Check if CNR is available */
|
||||
if (!(fe->status & FE_HAS_CARRIER))
|
||||
return 0;
|
||||
|
||||
rc = foo_read_cnr(fe);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* Check if pre-BER stats are available */
|
||||
if (!(fe->status & FE_HAS_VITERBI))
|
||||
return 0;
|
||||
|
||||
rc = foo_get_pre_ber(fe);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* Check if post-BER stats are available */
|
||||
if (!(fe->status & FE_HAS_SYNC))
|
||||
return 0;
|
||||
|
||||
rc = foo_get_post_ber(fe);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
}
|
||||
|
||||
static const struct dvb_frontend_ops ops = {
|
||||
/* ... */
|
||||
.read_status = foo_get_status_and_stats,
|
||||
};
|
||||
|
||||
Statistics collect
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
On almost all frontend hardware, the bit and byte counts are stored by
|
||||
the hardware after a certain amount of time or after the total bit/block
|
||||
counter reaches a certain value (usually programable), for example, on
|
||||
every 1000 ms or after receiving 1,000,000 bits.
|
||||
|
||||
So, if you read the registers too soon, you'll end by reading the same
|
||||
value as in the previous reading, causing the monotonic value to be
|
||||
incremented too often.
|
||||
|
||||
Drivers should take the responsibility to avoid too often reads. That
|
||||
can be done using two approaches:
|
||||
|
||||
if the driver have a bit that indicates when a collected data is ready
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
Driver should check such bit before making the statistics available.
|
||||
|
||||
An example of such behavior can be found at this code snippet (adapted
|
||||
from mb86a20s driver's logic)::
|
||||
|
||||
static int foo_get_pre_ber(struct dvb_frontend *fe)
|
||||
{
|
||||
struct foo_state *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||||
int rc, bit_error;
|
||||
|
||||
/* Check if the BER measures are already available */
|
||||
rc = foo_read_u8(state, 0x54);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
if (!rc)
|
||||
return 0;
|
||||
|
||||
/* Read Bit Error Count */
|
||||
bit_error = foo_read_u32(state, 0x55);
|
||||
if (bit_error < 0)
|
||||
return bit_error;
|
||||
|
||||
/* Read Total Bit Count */
|
||||
rc = foo_read_u32(state, 0x51);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||||
c->pre_bit_error.stat[0].uvalue += bit_error;
|
||||
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
|
||||
c->pre_bit_count.stat[0].uvalue += rc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
If the driver doesn't provide a statistics available check bit
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
A few devices, however, may not provide a way to check if the stats are
|
||||
available (or the way to check it is unknown). They may not even provide
|
||||
a way to directly read the total number of bits or blocks.
|
||||
|
||||
On those devices, the driver need to ensure that it won't be reading from
|
||||
the register too often and/or estimate the total number of bits/blocks.
|
||||
|
||||
On such drivers, a typical routine to get statistics would be like
|
||||
(adapted from dib8000 driver's logic)::
|
||||
|
||||
struct foo_state {
|
||||
/* ... */
|
||||
|
||||
unsigned long per_jiffies_stats;
|
||||
}
|
||||
|
||||
static int foo_get_pre_ber(struct dvb_frontend *fe)
|
||||
{
|
||||
struct foo_state *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||||
int rc, bit_error;
|
||||
u64 bits;
|
||||
|
||||
/* Check if time for stats was elapsed */
|
||||
if (!time_after(jiffies, state->per_jiffies_stats))
|
||||
return 0;
|
||||
|
||||
/* Next stat should be collected in 1000 ms */
|
||||
state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
|
||||
|
||||
/* Read Bit Error Count */
|
||||
bit_error = foo_read_u32(state, 0x55);
|
||||
if (bit_error < 0)
|
||||
return bit_error;
|
||||
|
||||
/*
|
||||
* On this particular frontend, there's no register that
|
||||
* would provide the number of bits per 1000ms sample. So,
|
||||
* some function would calculate it based on DTV properties
|
||||
*/
|
||||
bits = get_number_of_bits_per_1000ms(fe);
|
||||
|
||||
c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||||
c->pre_bit_error.stat[0].uvalue += bit_error;
|
||||
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
|
||||
c->pre_bit_count.stat[0].uvalue += bits;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Please notice that, on both cases, we're getting the statistics using the
|
||||
:c:type:`dvb_frontend_ops` ``.read_status`` callback. The rationale is that
|
||||
the frontend core will automatically call this function periodically
|
||||
(usually, 3 times per second, when the frontend is locked).
|
||||
|
||||
That warrants that we won't miss to collect a counter and increment the
|
||||
monotonic stats at the right time.
|
||||
|
||||
Digital TV Frontend functions and types
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
.. kernel-doc:: drivers/media/dvb-core/dvb_frontend.h
|
||||
|
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@ -147,3 +147,9 @@ appropriately. The generic error codes are described at the
|
||||
EINVAL
|
||||
The struct :c:type:`v4l2_format` ``type`` field is
|
||||
invalid or the requested buffer type not supported.
|
||||
|
||||
EBUSY
|
||||
The device is busy and cannot change the format. This could be
|
||||
because or the device is streaming or buffers are allocated or
|
||||
queued to the driver. Relevant for :ref:`VIDIOC_S_FMT
|
||||
<VIDIOC_G_FMT>` only.
|
||||
|
@ -607,8 +607,9 @@ References
|
||||
|
||||
Authors
|
||||
-------
|
||||
Steve Longerbeam <steve_longerbeam@mentor.com>
|
||||
Philipp Zabel <kernel@pengutronix.de>
|
||||
Russell King <linux@armlinux.org.uk>
|
||||
|
||||
- Steve Longerbeam <steve_longerbeam@mentor.com>
|
||||
- Philipp Zabel <kernel@pengutronix.de>
|
||||
- Russell King <linux@armlinux.org.uk>
|
||||
|
||||
Copyright (C) 2012-2017 Mentor Graphics Inc.
|
||||
|
@ -41,6 +41,7 @@ For more details see the file COPYING in the source distribution of Linux.
|
||||
cx88
|
||||
davinci-vpbe
|
||||
fimc
|
||||
imx
|
||||
ivtv
|
||||
max2175
|
||||
meye
|
||||
|
@ -435,7 +435,8 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h:
|
||||
PM status to 'suspended' and update its parent's counter of 'active'
|
||||
children as appropriate (it is only valid to use this function if
|
||||
'power.runtime_error' is set or 'power.disable_depth' is greater than
|
||||
zero)
|
||||
zero); it will fail and return an error code if the device has a child
|
||||
which is active and the 'power.ignore_children' flag is unset
|
||||
|
||||
bool pm_runtime_active(struct device *dev);
|
||||
- return true if the device's runtime PM status is 'active' or its
|
||||
|
27
MAINTAINERS
@ -1161,7 +1161,7 @@ M: Brendan Higgins <brendanhiggins@google.com>
|
||||
R: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
R: Joel Stanley <joel@jms.id.au>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
L: openbmc@lists.ozlabs.org
|
||||
L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: drivers/irqchip/irq-aspeed-i2c-ic.c
|
||||
F: drivers/i2c/busses/i2c-aspeed.c
|
||||
@ -5090,12 +5090,20 @@ M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/phy.h
|
||||
F: include/linux/phy_fixed.h
|
||||
F: drivers/net/phy/
|
||||
F: Documentation/ABI/testing/sysfs-bus-mdio
|
||||
F: Documentation/devicetree/bindings/net/mdio*
|
||||
F: Documentation/networking/phy.txt
|
||||
F: drivers/net/phy/
|
||||
F: drivers/of/of_mdio.c
|
||||
F: drivers/of/of_net.c
|
||||
F: include/linux/*mdio*.h
|
||||
F: include/linux/of_net.h
|
||||
F: include/linux/phy.h
|
||||
F: include/linux/phy_fixed.h
|
||||
F: include/linux/platform_data/mdio-gpio.h
|
||||
F: include/trace/events/mdio.h
|
||||
F: include/uapi/linux/mdio.h
|
||||
F: include/uapi/linux/mii.h
|
||||
|
||||
EXT2 FILE SYSTEM
|
||||
M: Jan Kara <jack@suse.com>
|
||||
@ -5826,7 +5834,7 @@ F: drivers/staging/greybus/spi.c
|
||||
F: drivers/staging/greybus/spilib.c
|
||||
F: drivers/staging/greybus/spilib.h
|
||||
|
||||
GREYBUS LOOBACK/TIME PROTOCOLS DRIVERS
|
||||
GREYBUS LOOPBACK/TIME PROTOCOLS DRIVERS
|
||||
M: Bryan O'Donoghue <pure.logic@nexus-software.ie>
|
||||
S: Maintained
|
||||
F: drivers/staging/greybus/loopback.c
|
||||
@ -10383,7 +10391,7 @@ L: linux-gpio@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pinctrl/
|
||||
F: Documentation/pinctrl.txt
|
||||
F: Documentation/driver-api/pinctl.rst
|
||||
F: drivers/pinctrl/
|
||||
F: include/linux/pinctrl/
|
||||
|
||||
@ -14004,6 +14012,7 @@ F: drivers/block/virtio_blk.c
|
||||
F: include/linux/virtio*.h
|
||||
F: include/uapi/linux/virtio_*.h
|
||||
F: drivers/crypto/virtio/
|
||||
F: mm/balloon_compaction.c
|
||||
|
||||
VIRTIO CRYPTO DRIVER
|
||||
M: Gonglei <arei.gonglei@huawei.com>
|
||||
@ -14218,6 +14227,12 @@ F: drivers/watchdog/
|
||||
F: include/linux/watchdog.h
|
||||
F: include/uapi/linux/watchdog.h
|
||||
|
||||
WHISKEYCOVE PMIC GPIO DRIVER
|
||||
M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/gpio/gpio-wcove.c
|
||||
|
||||
WIIMOTE HID DRIVER
|
||||
M: David Herrmann <dh.herrmann@googlemail.com>
|
||||
L: linux-input@vger.kernel.org
|
||||
|
2
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 4
|
||||
PATCHLEVEL = 13
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Fearless Coyote
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -117,7 +117,7 @@ static int arc_dma_mmap(struct device *dev, struct vm_area_struct *vma,
|
||||
|
||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||
|
||||
if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
|
||||
if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
|
||||
return ret;
|
||||
|
||||
if (off < count && user_count <= (count - off)) {
|
||||
|
@ -380,7 +380,7 @@ config ARCH_EP93XX
|
||||
bool "EP93xx-based"
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARM_AMBA
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
imply ARM_PATCH_PHYS_VIRT
|
||||
select ARM_VIC
|
||||
select AUTO_ZRELADDR
|
||||
select CLKDEV_LOOKUP
|
||||
|
@ -75,7 +75,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pca0_pins>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
@ -87,7 +87,7 @@
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -301,25 +301,4 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
|
||||
status = "okay";
|
||||
|
||||
/* VPIF capture port */
|
||||
port@0 {
|
||||
vpif_input_ch0: endpoint@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
vpif_input_ch1: endpoint@1 {
|
||||
reg = <1>;
|
||||
bus-width = <8>;
|
||||
data-shift = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* VPIF display port */
|
||||
port@1 {
|
||||
vpif_output_ch0: endpoint {
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -318,11 +318,4 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vpif_capture_pins>;
|
||||
status = "okay";
|
||||
|
||||
/* VPIF capture port */
|
||||
port {
|
||||
vpif_ch0: endpoint {
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -68,6 +68,34 @@
|
||||
DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins: nandflash_pins {
|
||||
pinctrl-single,pins = <
|
||||
DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/
|
||||
DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */
|
||||
DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */
|
||||
DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */
|
||||
DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */
|
||||
DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */
|
||||
DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */
|
||||
DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */
|
||||
DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */
|
||||
DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */
|
||||
DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */
|
||||
DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */
|
||||
DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */
|
||||
DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */
|
||||
DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */
|
||||
DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */
|
||||
DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */
|
||||
DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */
|
||||
DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */
|
||||
DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */
|
||||
DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */
|
||||
DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */
|
||||
DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
@ -90,6 +118,8 @@
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
@ -98,9 +128,11 @@
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
@ -164,7 +196,7 @@
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* At least dm8168-evm rev c won't support multipoint, later may */
|
||||
|
@ -145,7 +145,7 @@
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,816-elm";
|
||||
compatible = "ti,am3352-elm";
|
||||
ti,hwmods = "elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <4>;
|
||||
|
@ -190,7 +190,7 @@
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||
ti,impedance-control = <0x1f>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
|
||||
dp83867_1: ethernet-phy@3 {
|
||||
@ -198,7 +198,7 @@
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||
ti,impedance-control = <0x1f>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -59,6 +59,9 @@
|
||||
compatible = "samsung,exynos4210-audss-clock";
|
||||
reg = <0x03810000 0x0C>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
|
||||
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
||||
};
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
|
@ -1126,8 +1126,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
gpu: mali@ffa30000 {
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
|
||||
gpu: gpu@ffa30000 {
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
|
||||
reg = <0xffa30000 0x10000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -44,7 +44,9 @@
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
|
||||
#include <dt-bindings/clock/sun8i-r-ccu.h>
|
||||
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
@ -175,8 +177,8 @@
|
||||
compatible = "allwinner,sun8i-a83t-dma";
|
||||
reg = <0x01c02000 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu 21>;
|
||||
resets = <&ccu 7>;
|
||||
clocks = <&ccu CLK_BUS_DMA>;
|
||||
resets = <&ccu RST_BUS_DMA>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
@ -195,7 +197,7 @@
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x01c20800 0x400>;
|
||||
clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
|
||||
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
|
||||
clock-names = "apb", "hosc", "losc";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
@ -247,8 +249,8 @@
|
||||
"allwinner,sun8i-h3-spdif";
|
||||
reg = <0x01c21000 0x400>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu 44>, <&ccu 76>;
|
||||
resets = <&ccu 32>;
|
||||
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
|
||||
resets = <&ccu RST_BUS_SPDIF>;
|
||||
clock-names = "apb", "spdif";
|
||||
dmas = <&dma 2>;
|
||||
dma-names = "tx";
|
||||
@ -263,8 +265,8 @@
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&ccu 53>;
|
||||
resets = <&ccu 40>;
|
||||
clocks = <&ccu CLK_BUS_UART0>;
|
||||
resets = <&ccu RST_BUS_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -394,7 +394,7 @@
|
||||
emac: ethernet@1c30000 {
|
||||
compatible = "allwinner,sun8i-h3-emac";
|
||||
syscon = <&syscon>;
|
||||
reg = <0x01c30000 0x104>;
|
||||
reg = <0x01c30000 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
resets = <&ccu RST_BUS_EMAC>;
|
||||
|
@ -22,7 +22,7 @@
|
||||
};
|
||||
|
||||
ð0 {
|
||||
phy-connection-type = "rgmii";
|
||||
phy-connection-type = "rgmii-id";
|
||||
phy-handle = <ð0_phy>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -19,6 +19,11 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define ARCH_HAS_KIMAGE_ARCH
|
||||
struct kimage_arch {
|
||||
u32 kernel_r2;
|
||||
};
|
||||
|
||||
/**
|
||||
* crash_setup_regs() - save registers for the panic kernel
|
||||
* @newregs: registers are saved here
|
||||
|
@ -148,7 +148,8 @@ static inline void tlb_flush_mmu(struct mmu_gather *tlb)
|
||||
}
|
||||
|
||||
static inline void
|
||||
tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start, unsigned long end)
|
||||
arch_tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm,
|
||||
unsigned long start, unsigned long end)
|
||||
{
|
||||
tlb->mm = mm;
|
||||
tlb->fullmm = !(start | (end+1));
|
||||
@ -166,8 +167,14 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start
|
||||
}
|
||||
|
||||
static inline void
|
||||
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
|
||||
arch_tlb_finish_mmu(struct mmu_gather *tlb,
|
||||
unsigned long start, unsigned long end, bool force)
|
||||
{
|
||||
if (force) {
|
||||
tlb->range_start = start;
|
||||
tlb->range_end = end;
|
||||
}
|
||||
|
||||
tlb_flush_mmu(tlb);
|
||||
|
||||
/* keep the page table cache within bounds */
|
||||
|
@ -35,6 +35,12 @@ struct ucontext {
|
||||
* bytes, to prevent unpredictable padding in the signal frame.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Dummy padding block: if this magic is encountered, the block should
|
||||
* be skipped using the corresponding size field.
|
||||
*/
|
||||
#define DUMMY_MAGIC 0xb0d9ed01
|
||||
|
||||
#ifdef CONFIG_CRUNCH
|
||||
#define CRUNCH_MAGIC 0x5065cf03
|
||||
#define CRUNCH_STORAGE_SIZE (CRUNCH_SIZE + 8)
|
||||
|
@ -30,7 +30,6 @@ extern unsigned long kexec_boot_atags;
|
||||
|
||||
static atomic_t waiting_for_crash_ipi;
|
||||
|
||||
static unsigned long dt_mem;
|
||||
/*
|
||||
* Provide a dummy crash_notes definition while crash dump arrives to arm.
|
||||
* This prevents breakage of crash_notes attribute in kernel/ksysfs.c.
|
||||
@ -42,6 +41,9 @@ int machine_kexec_prepare(struct kimage *image)
|
||||
__be32 header;
|
||||
int i, err;
|
||||
|
||||
image->arch.kernel_r2 = image->start - KEXEC_ARM_ZIMAGE_OFFSET
|
||||
+ KEXEC_ARM_ATAGS_OFFSET;
|
||||
|
||||
/*
|
||||
* Validate that if the current HW supports SMP, then the SW supports
|
||||
* and implements CPU hotplug for the current HW. If not, we won't be
|
||||
@ -66,8 +68,8 @@ int machine_kexec_prepare(struct kimage *image)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (be32_to_cpu(header) == OF_DT_HEADER)
|
||||
dt_mem = current_segment->mem;
|
||||
if (header == cpu_to_be32(OF_DT_HEADER))
|
||||
image->arch.kernel_r2 = current_segment->mem;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -165,8 +167,7 @@ void machine_kexec(struct kimage *image)
|
||||
kexec_start_address = image->start;
|
||||
kexec_indirection_page = page_list;
|
||||
kexec_mach_type = machine_arch_type;
|
||||
kexec_boot_atags = dt_mem ?: image->start - KEXEC_ARM_ZIMAGE_OFFSET
|
||||
+ KEXEC_ARM_ATAGS_OFFSET;
|
||||
kexec_boot_atags = image->arch.kernel_r2;
|
||||
|
||||
/* copy our kernel relocation code to the control code page */
|
||||
reboot_entry = fncpy(reboot_code_buffer,
|
||||
|
@ -987,6 +987,9 @@ static void __init reserve_crashkernel(void)
|
||||
|
||||
if (crash_base <= 0) {
|
||||
unsigned long long crash_max = idmap_to_phys((u32)~0);
|
||||
unsigned long long lowmem_max = __pa(high_memory - 1) + 1;
|
||||
if (crash_max > lowmem_max)
|
||||
crash_max = lowmem_max;
|
||||
crash_base = memblock_find_in_range(CRASH_ALIGN, crash_max,
|
||||
crash_size, CRASH_ALIGN);
|
||||
if (!crash_base) {
|
||||
|
@ -40,8 +40,10 @@ static int preserve_crunch_context(struct crunch_sigframe __user *frame)
|
||||
return __copy_to_user(frame, kframe, sizeof(*frame));
|
||||
}
|
||||
|
||||
static int restore_crunch_context(struct crunch_sigframe __user *frame)
|
||||
static int restore_crunch_context(char __user **auxp)
|
||||
{
|
||||
struct crunch_sigframe __user *frame =
|
||||
(struct crunch_sigframe __user *)*auxp;
|
||||
char kbuf[sizeof(*frame) + 8];
|
||||
struct crunch_sigframe *kframe;
|
||||
|
||||
@ -52,6 +54,7 @@ static int restore_crunch_context(struct crunch_sigframe __user *frame)
|
||||
if (kframe->magic != CRUNCH_MAGIC ||
|
||||
kframe->size != CRUNCH_STORAGE_SIZE)
|
||||
return -1;
|
||||
*auxp += CRUNCH_STORAGE_SIZE;
|
||||
crunch_task_restore(current_thread_info(), &kframe->storage);
|
||||
return 0;
|
||||
}
|
||||
@ -59,21 +62,39 @@ static int restore_crunch_context(struct crunch_sigframe __user *frame)
|
||||
|
||||
#ifdef CONFIG_IWMMXT
|
||||
|
||||
static int preserve_iwmmxt_context(struct iwmmxt_sigframe *frame)
|
||||
static int preserve_iwmmxt_context(struct iwmmxt_sigframe __user *frame)
|
||||
{
|
||||
char kbuf[sizeof(*frame) + 8];
|
||||
struct iwmmxt_sigframe *kframe;
|
||||
int err = 0;
|
||||
|
||||
/* the iWMMXt context must be 64 bit aligned */
|
||||
kframe = (struct iwmmxt_sigframe *)((unsigned long)(kbuf + 8) & ~7);
|
||||
kframe->magic = IWMMXT_MAGIC;
|
||||
kframe->size = IWMMXT_STORAGE_SIZE;
|
||||
iwmmxt_task_copy(current_thread_info(), &kframe->storage);
|
||||
return __copy_to_user(frame, kframe, sizeof(*frame));
|
||||
|
||||
if (test_thread_flag(TIF_USING_IWMMXT)) {
|
||||
kframe->magic = IWMMXT_MAGIC;
|
||||
kframe->size = IWMMXT_STORAGE_SIZE;
|
||||
iwmmxt_task_copy(current_thread_info(), &kframe->storage);
|
||||
|
||||
err = __copy_to_user(frame, kframe, sizeof(*frame));
|
||||
} else {
|
||||
/*
|
||||
* For bug-compatibility with older kernels, some space
|
||||
* has to be reserved for iWMMXt even if it's not used.
|
||||
* Set the magic and size appropriately so that properly
|
||||
* written userspace can skip it reliably:
|
||||
*/
|
||||
__put_user_error(DUMMY_MAGIC, &frame->magic, err);
|
||||
__put_user_error(IWMMXT_STORAGE_SIZE, &frame->size, err);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
|
||||
static int restore_iwmmxt_context(char __user **auxp)
|
||||
{
|
||||
struct iwmmxt_sigframe __user *frame =
|
||||
(struct iwmmxt_sigframe __user *)*auxp;
|
||||
char kbuf[sizeof(*frame) + 8];
|
||||
struct iwmmxt_sigframe *kframe;
|
||||
|
||||
@ -81,10 +102,28 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
|
||||
kframe = (struct iwmmxt_sigframe *)((unsigned long)(kbuf + 8) & ~7);
|
||||
if (__copy_from_user(kframe, frame, sizeof(*frame)))
|
||||
return -1;
|
||||
if (kframe->magic != IWMMXT_MAGIC ||
|
||||
kframe->size != IWMMXT_STORAGE_SIZE)
|
||||
|
||||
/*
|
||||
* For non-iWMMXt threads: a single iwmmxt_sigframe-sized dummy
|
||||
* block is discarded for compatibility with setup_sigframe() if
|
||||
* present, but we don't mandate its presence. If some other
|
||||
* magic is here, it's not for us:
|
||||
*/
|
||||
if (!test_thread_flag(TIF_USING_IWMMXT) &&
|
||||
kframe->magic != DUMMY_MAGIC)
|
||||
return 0;
|
||||
|
||||
if (kframe->size != IWMMXT_STORAGE_SIZE)
|
||||
return -1;
|
||||
iwmmxt_task_restore(current_thread_info(), &kframe->storage);
|
||||
|
||||
if (test_thread_flag(TIF_USING_IWMMXT)) {
|
||||
if (kframe->magic != IWMMXT_MAGIC)
|
||||
return -1;
|
||||
|
||||
iwmmxt_task_restore(current_thread_info(), &kframe->storage);
|
||||
}
|
||||
|
||||
*auxp += IWMMXT_STORAGE_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -107,8 +146,10 @@ static int preserve_vfp_context(struct vfp_sigframe __user *frame)
|
||||
return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
|
||||
}
|
||||
|
||||
static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
||||
static int restore_vfp_context(char __user **auxp)
|
||||
{
|
||||
struct vfp_sigframe __user *frame =
|
||||
(struct vfp_sigframe __user *)*auxp;
|
||||
unsigned long magic;
|
||||
unsigned long size;
|
||||
int err = 0;
|
||||
@ -121,6 +162,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
||||
if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
*auxp += size;
|
||||
return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
|
||||
}
|
||||
|
||||
@ -141,7 +183,7 @@ struct rt_sigframe {
|
||||
|
||||
static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
|
||||
{
|
||||
struct aux_sigframe __user *aux;
|
||||
char __user *aux;
|
||||
sigset_t set;
|
||||
int err;
|
||||
|
||||
@ -169,18 +211,18 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
|
||||
|
||||
err |= !valid_user_regs(regs);
|
||||
|
||||
aux = (struct aux_sigframe __user *) sf->uc.uc_regspace;
|
||||
aux = (char __user *) sf->uc.uc_regspace;
|
||||
#ifdef CONFIG_CRUNCH
|
||||
if (err == 0)
|
||||
err |= restore_crunch_context(&aux->crunch);
|
||||
err |= restore_crunch_context(&aux);
|
||||
#endif
|
||||
#ifdef CONFIG_IWMMXT
|
||||
if (err == 0 && test_thread_flag(TIF_USING_IWMMXT))
|
||||
err |= restore_iwmmxt_context(&aux->iwmmxt);
|
||||
if (err == 0)
|
||||
err |= restore_iwmmxt_context(&aux);
|
||||
#endif
|
||||
#ifdef CONFIG_VFP
|
||||
if (err == 0)
|
||||
err |= restore_vfp_context(&aux->vfp);
|
||||
err |= restore_vfp_context(&aux);
|
||||
#endif
|
||||
|
||||
return err;
|
||||
@ -286,7 +328,7 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set)
|
||||
err |= preserve_crunch_context(&aux->crunch);
|
||||
#endif
|
||||
#ifdef CONFIG_IWMMXT
|
||||
if (err == 0 && test_thread_flag(TIF_USING_IWMMXT))
|
||||
if (err == 0)
|
||||
err |= preserve_iwmmxt_context(&aux->iwmmxt);
|
||||
#endif
|
||||
#ifdef CONFIG_VFP
|
||||
|
@ -1166,7 +1166,7 @@ static struct tvp514x_platform_data tvp5146_pdata = {
|
||||
|
||||
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
|
||||
|
||||
static const struct vpif_input da850_ch0_inputs[] = {
|
||||
static struct vpif_input da850_ch0_inputs[] = {
|
||||
{
|
||||
.input = {
|
||||
.index = 0,
|
||||
@ -1181,7 +1181,7 @@ static const struct vpif_input da850_ch0_inputs[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static const struct vpif_input da850_ch1_inputs[] = {
|
||||
static struct vpif_input da850_ch1_inputs[] = {
|
||||
{
|
||||
.input = {
|
||||
.index = 0,
|
||||
|
@ -218,6 +218,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return NULL;
|
||||
|
||||
return clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
||||
|
||||
int clk_register(struct clk *clk)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
|
@ -475,6 +475,26 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
WARN_ON(clk);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_round_rate);
|
||||
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
WARN_ON(clk);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
return clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
||||
|
||||
|
||||
static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
|
||||
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
|
||||
|
@ -95,8 +95,10 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
|
||||
}
|
||||
|
||||
static inline void __indirect_writesb(volatile void __iomem *bus_addr,
|
||||
const u8 *vaddr, int count)
|
||||
const void *p, int count)
|
||||
{
|
||||
const u8 *vaddr = p;
|
||||
|
||||
while (count--)
|
||||
writeb(*vaddr++, bus_addr);
|
||||
}
|
||||
@ -118,8 +120,10 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p)
|
||||
}
|
||||
|
||||
static inline void __indirect_writesw(volatile void __iomem *bus_addr,
|
||||
const u16 *vaddr, int count)
|
||||
const void *p, int count)
|
||||
{
|
||||
const u16 *vaddr = p;
|
||||
|
||||
while (count--)
|
||||
writew(*vaddr++, bus_addr);
|
||||
}
|
||||
@ -137,8 +141,9 @@ static inline void __indirect_writel(u32 value, volatile void __iomem *p)
|
||||
}
|
||||
|
||||
static inline void __indirect_writesl(volatile void __iomem *bus_addr,
|
||||
const u32 *vaddr, int count)
|
||||
const void *p, int count)
|
||||
{
|
||||
const u32 *vaddr = p;
|
||||
while (count--)
|
||||
writel(*vaddr++, bus_addr);
|
||||
}
|
||||
@ -160,8 +165,10 @@ static inline u8 __indirect_readb(const volatile void __iomem *p)
|
||||
}
|
||||
|
||||
static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
|
||||
u8 *vaddr, u32 count)
|
||||
void *p, u32 count)
|
||||
{
|
||||
u8 *vaddr = p;
|
||||
|
||||
while (count--)
|
||||
*vaddr++ = readb(bus_addr);
|
||||
}
|
||||
@ -183,8 +190,10 @@ static inline u16 __indirect_readw(const volatile void __iomem *p)
|
||||
}
|
||||
|
||||
static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
|
||||
u16 *vaddr, u32 count)
|
||||
void *p, u32 count)
|
||||
{
|
||||
u16 *vaddr = p;
|
||||
|
||||
while (count--)
|
||||
*vaddr++ = readw(bus_addr);
|
||||
}
|
||||
@ -204,8 +213,10 @@ static inline u32 __indirect_readl(const volatile void __iomem *p)
|
||||
}
|
||||
|
||||
static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
|
||||
u32 *vaddr, u32 count)
|
||||
void *p, u32 count)
|
||||
{
|
||||
u32 *vaddr = p;
|
||||
|
||||
while (count--)
|
||||
*vaddr++ = readl(bus_addr);
|
||||
}
|
||||
@ -523,8 +534,15 @@ static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
|
||||
#endif
|
||||
}
|
||||
|
||||
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
|
||||
#define ioport_unmap(addr)
|
||||
#define ioport_map(port, nr) ioport_map(port, nr)
|
||||
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
return ((void __iomem*)((port) + PIO_OFFSET));
|
||||
}
|
||||
#define ioport_unmap(addr) ioport_unmap(addr)
|
||||
static inline void ioport_unmap(void __iomem *addr)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#endif /* __ASM_ARM_ARCH_IO_H */
|
||||
|
@ -238,7 +238,7 @@ void pxa_usb_phy_deinit(void __iomem *phy_reg)
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_SUPPORT)
|
||||
static u64 usb_dma_mask = ~(u32)0;
|
||||
static u64 __maybe_unused usb_dma_mask = ~(u32)0;
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_MV_UDC)
|
||||
struct resource pxa168_u2o_resources[] = {
|
||||
|
@ -211,7 +211,7 @@ static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
|
||||
return PTR_ERR(base);
|
||||
|
||||
writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
|
||||
writel(virt_to_phys(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
|
||||
writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
|
||||
|
||||
iounmap(base);
|
||||
|
||||
|
@ -510,6 +510,7 @@ static void __init ams_delta_init(void)
|
||||
static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
|
||||
{
|
||||
struct modem_private_data *priv = port->private_data;
|
||||
int ret;
|
||||
|
||||
if (IS_ERR(priv->regulator))
|
||||
return;
|
||||
@ -518,9 +519,16 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
|
||||
return;
|
||||
|
||||
if (state == 0)
|
||||
regulator_enable(priv->regulator);
|
||||
ret = regulator_enable(priv->regulator);
|
||||
else if (old == 0)
|
||||
regulator_disable(priv->regulator);
|
||||
ret = regulator_disable(priv->regulator);
|
||||
else
|
||||
ret = 0;
|
||||
|
||||
if (ret)
|
||||
dev_warn(port->dev,
|
||||
"ams_delta modem_pm: failed to %sable regulator: %d\n",
|
||||
state ? "dis" : "en", ret);
|
||||
}
|
||||
|
||||
static struct plat_serial8250_port ams_delta_modem_ports[] = {
|
||||
|
@ -441,13 +441,11 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
|
||||
.chip_select = 0,
|
||||
} };
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static irqreturn_t
|
||||
osk_mistral_wake_interrupt(int irq, void *ignored)
|
||||
{
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init osk_mistral_init(void)
|
||||
{
|
||||
@ -515,7 +513,6 @@ static void __init osk_mistral_init(void)
|
||||
|
||||
gpio_direction_input(OMAP_MPUIO(2));
|
||||
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
|
||||
#ifdef CONFIG_PM
|
||||
/* share the IRQ in case someone wants to use the
|
||||
* button for more than wakeup from system sleep.
|
||||
*/
|
||||
@ -529,7 +526,6 @@ static void __init osk_mistral_init(void)
|
||||
ret);
|
||||
} else
|
||||
enable_irq_wake(irq);
|
||||
#endif
|
||||
} else
|
||||
printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");
|
||||
|
||||
|
@ -28,7 +28,7 @@ static const struct of_device_id omap_dt_match_table[] __initconst = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static void __init omap_generic_init(void)
|
||||
static void __init __maybe_unused omap_generic_init(void)
|
||||
{
|
||||
pdata_quirks_init(omap_dt_match_table);
|
||||
|
||||
|
@ -32,120 +32,6 @@ static u16 control_devconf1_offset;
|
||||
|
||||
#define HSMMC_NAME_LEN 9
|
||||
|
||||
static void omap_hsmmc1_before_set_reg(struct device *dev,
|
||||
int power_on, int vdd)
|
||||
{
|
||||
u32 reg, prog_io;
|
||||
struct omap_hsmmc_platform_data *mmc = dev->platform_data;
|
||||
|
||||
if (mmc->remux)
|
||||
mmc->remux(dev, power_on);
|
||||
|
||||
/*
|
||||
* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
|
||||
* card with Vcc regulator (from twl4030 or whatever). OMAP has both
|
||||
* 1.8V and 3.0V modes, controlled by the PBIAS register.
|
||||
*
|
||||
* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
|
||||
* is most naturally TWL VSIM; those pins also use PBIAS.
|
||||
*
|
||||
* FIXME handle VMMC1A as needed ...
|
||||
*/
|
||||
if (power_on) {
|
||||
if (cpu_is_omap2430()) {
|
||||
reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
|
||||
if ((1 << vdd) >= MMC_VDD_30_31)
|
||||
reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
|
||||
else
|
||||
reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
|
||||
omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
|
||||
}
|
||||
|
||||
if (mmc->internal_clock) {
|
||||
reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
|
||||
reg |= OMAP2_MMCSDIO1ADPCLKISEL;
|
||||
omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
|
||||
}
|
||||
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
if (cpu_is_omap3630()) {
|
||||
/* Set MMC I/O to 52MHz */
|
||||
prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
|
||||
prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
|
||||
omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
|
||||
} else {
|
||||
reg |= OMAP2_PBIASSPEEDCTRL0;
|
||||
}
|
||||
reg &= ~OMAP2_PBIASLITEPWRDNZ0;
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
} else {
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
reg &= ~OMAP2_PBIASLITEPWRDNZ0;
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
}
|
||||
}
|
||||
|
||||
static void omap_hsmmc1_after_set_reg(struct device *dev, int power_on, int vdd)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* 100ms delay required for PBIAS configuration */
|
||||
msleep(100);
|
||||
|
||||
if (power_on) {
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
|
||||
if ((1 << vdd) <= MMC_VDD_165_195)
|
||||
reg &= ~OMAP2_PBIASLITEVMODE0;
|
||||
else
|
||||
reg |= OMAP2_PBIASLITEVMODE0;
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
} else {
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
|
||||
OMAP2_PBIASLITEVMODE0);
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
}
|
||||
}
|
||||
|
||||
static void hsmmc2_select_input_clk_src(struct omap_hsmmc_platform_data *mmc)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = omap_ctrl_readl(control_devconf1_offset);
|
||||
if (mmc->internal_clock)
|
||||
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
|
||||
else
|
||||
reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
|
||||
omap_ctrl_writel(reg, control_devconf1_offset);
|
||||
}
|
||||
|
||||
static void hsmmc2_before_set_reg(struct device *dev, int power_on, int vdd)
|
||||
{
|
||||
struct omap_hsmmc_platform_data *mmc = dev->platform_data;
|
||||
|
||||
if (mmc->remux)
|
||||
mmc->remux(dev, power_on);
|
||||
|
||||
if (power_on)
|
||||
hsmmc2_select_input_clk_src(mmc);
|
||||
}
|
||||
|
||||
static int am35x_hsmmc2_set_power(struct device *dev, int power_on, int vdd)
|
||||
{
|
||||
struct omap_hsmmc_platform_data *mmc = dev->platform_data;
|
||||
|
||||
if (power_on)
|
||||
hsmmc2_select_input_clk_src(mmc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
struct omap_hsmmc_platform_data *mmc)
|
||||
{
|
||||
@ -157,101 +43,11 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (c->name)
|
||||
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
|
||||
else
|
||||
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
|
||||
c->mmc, 1);
|
||||
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", c->mmc, 1);
|
||||
mmc->name = hc_name;
|
||||
mmc->caps = c->caps;
|
||||
mmc->internal_clock = !c->ext_clock;
|
||||
mmc->reg_offset = 0;
|
||||
|
||||
if (c->cover_only) {
|
||||
/* detect if mobile phone cover removed */
|
||||
mmc->gpio_cd = -EINVAL;
|
||||
mmc->gpio_cod = c->gpio_cd;
|
||||
} else {
|
||||
/* card detect pin on the mmc socket itself */
|
||||
mmc->gpio_cd = c->gpio_cd;
|
||||
mmc->gpio_cod = -EINVAL;
|
||||
}
|
||||
mmc->gpio_wp = c->gpio_wp;
|
||||
|
||||
mmc->remux = c->remux;
|
||||
mmc->init_card = c->init_card;
|
||||
|
||||
if (c->nonremovable)
|
||||
mmc->nonremovable = 1;
|
||||
|
||||
/*
|
||||
* NOTE: MMC slots should have a Vcc regulator set up.
|
||||
* This may be from a TWL4030-family chip, another
|
||||
* controllable regulator, or a fixed supply.
|
||||
*
|
||||
* temporary HACK: ocr_mask instead of fixed supply
|
||||
*/
|
||||
if (soc_is_am35xx())
|
||||
mmc->ocr_mask = MMC_VDD_165_195 |
|
||||
MMC_VDD_26_27 |
|
||||
MMC_VDD_27_28 |
|
||||
MMC_VDD_29_30 |
|
||||
MMC_VDD_30_31 |
|
||||
MMC_VDD_31_32;
|
||||
else
|
||||
mmc->ocr_mask = c->ocr_mask;
|
||||
|
||||
if (!soc_is_am35xx())
|
||||
mmc->features |= HSMMC_HAS_PBIAS;
|
||||
|
||||
switch (c->mmc) {
|
||||
case 1:
|
||||
if (mmc->features & HSMMC_HAS_PBIAS) {
|
||||
/* on-chip level shifting via PBIAS0/PBIAS1 */
|
||||
mmc->before_set_reg =
|
||||
omap_hsmmc1_before_set_reg;
|
||||
mmc->after_set_reg =
|
||||
omap_hsmmc1_after_set_reg;
|
||||
}
|
||||
|
||||
if (soc_is_am35xx())
|
||||
mmc->set_power = nop_mmc_set_power;
|
||||
|
||||
/* OMAP3630 HSMMC1 supports only 4-bit */
|
||||
if (cpu_is_omap3630() &&
|
||||
(c->caps & MMC_CAP_8_BIT_DATA)) {
|
||||
c->caps &= ~MMC_CAP_8_BIT_DATA;
|
||||
c->caps |= MMC_CAP_4_BIT_DATA;
|
||||
mmc->caps = c->caps;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if (soc_is_am35xx())
|
||||
mmc->set_power = am35x_hsmmc2_set_power;
|
||||
|
||||
if (c->ext_clock)
|
||||
c->transceiver = 1;
|
||||
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
|
||||
c->caps &= ~MMC_CAP_8_BIT_DATA;
|
||||
c->caps |= MMC_CAP_4_BIT_DATA;
|
||||
}
|
||||
if (mmc->features & HSMMC_HAS_PBIAS) {
|
||||
/* off-chip level shifting, or none */
|
||||
mmc->before_set_reg = hsmmc2_before_set_reg;
|
||||
mmc->after_set_reg = NULL;
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
case 4:
|
||||
case 5:
|
||||
mmc->before_set_reg = NULL;
|
||||
mmc->after_set_reg = NULL;
|
||||
break;
|
||||
default:
|
||||
pr_err("MMC%d configuration not supported!\n", c->mmc);
|
||||
kfree(hc_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -260,7 +56,6 @@ static int omap_hsmmc_done;
|
||||
void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct omap_hsmmc_platform_data *mmc_pdata;
|
||||
int res;
|
||||
|
||||
if (omap_hsmmc_done != 1)
|
||||
@ -269,32 +64,12 @@ void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
|
||||
omap_hsmmc_done++;
|
||||
|
||||
for (; c->mmc; c++) {
|
||||
if (!c->deferred)
|
||||
continue;
|
||||
|
||||
pdev = c->pdev;
|
||||
if (!pdev)
|
||||
continue;
|
||||
|
||||
mmc_pdata = pdev->dev.platform_data;
|
||||
if (!mmc_pdata)
|
||||
continue;
|
||||
|
||||
if (c->cover_only) {
|
||||
/* detect if mobile phone cover removed */
|
||||
mmc_pdata->gpio_cd = -EINVAL;
|
||||
mmc_pdata->gpio_cod = c->gpio_cd;
|
||||
} else {
|
||||
/* card detect pin on the mmc socket itself */
|
||||
mmc_pdata->gpio_cd = c->gpio_cd;
|
||||
mmc_pdata->gpio_cod = -EINVAL;
|
||||
}
|
||||
mmc_pdata->gpio_wp = c->gpio_wp;
|
||||
|
||||
res = omap_device_register(pdev);
|
||||
if (res)
|
||||
pr_err("Could not late init MMC %s\n",
|
||||
c->name);
|
||||
pr_err("Could not late init MMC\n");
|
||||
}
|
||||
}
|
||||
|
||||
@ -336,13 +111,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
|
||||
if (oh->dev_attr != NULL) {
|
||||
mmc_dev_attr = oh->dev_attr;
|
||||
mmc_data->controller_flags = mmc_dev_attr->flags;
|
||||
/*
|
||||
* erratum 2.1.1.128 doesn't apply if board has
|
||||
* a transceiver is attached
|
||||
*/
|
||||
if (hsmmcinfo->transceiver)
|
||||
mmc_data->controller_flags &=
|
||||
~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
|
||||
}
|
||||
|
||||
pdev = platform_device_alloc(name, ctrl_nr - 1);
|
||||
@ -367,9 +135,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
|
||||
|
||||
hsmmcinfo->pdev = pdev;
|
||||
|
||||
if (hsmmcinfo->deferred)
|
||||
goto free_mmc;
|
||||
|
||||
res = omap_device_register(pdev);
|
||||
if (res) {
|
||||
pr_err("Could not register od for %s\n", name);
|
||||
|
@ -12,18 +12,9 @@ struct omap2_hsmmc_info {
|
||||
u8 mmc; /* controller 1/2/3 */
|
||||
u32 caps; /* 4/8 wires and any additional host
|
||||
* capabilities OR'd (ref. linux/mmc/host.h) */
|
||||
bool transceiver; /* MMC-2 option */
|
||||
bool ext_clock; /* use external pin for input clock */
|
||||
bool cover_only; /* No card detect - just cover switch */
|
||||
bool nonremovable; /* Nonremovable e.g. eMMC */
|
||||
bool deferred; /* mmc needs a deferred probe */
|
||||
int gpio_cd; /* or -EINVAL */
|
||||
int gpio_wp; /* or -EINVAL */
|
||||
char *name; /* or NULL for default */
|
||||
struct platform_device *pdev; /* mmc controller instance */
|
||||
int ocr_mask; /* temporary HACK */
|
||||
/* Remux (pad configuration) when powering on/off */
|
||||
void (*remux)(struct device *dev, int power_on);
|
||||
/* init some special card */
|
||||
void (*init_card)(struct mmc_card *card);
|
||||
};
|
||||
|
@ -410,7 +410,7 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
|
||||
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
|
||||
}
|
||||
|
||||
static void __init omap_hwmod_init_postsetup(void)
|
||||
static void __init __maybe_unused omap_hwmod_init_postsetup(void)
|
||||
{
|
||||
u8 postsetup_state;
|
||||
|
||||
|
@ -486,7 +486,6 @@ int __init omap3_pm_init(void)
|
||||
ret = request_irq(omap_prcm_event_to_irq("io"),
|
||||
_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
|
||||
omap3_pm_init);
|
||||
enable_irq(omap_prcm_event_to_irq("io"));
|
||||
|
||||
if (ret) {
|
||||
pr_err("pm: Failed to request pm_io irq\n");
|
||||
|
@ -692,7 +692,6 @@ static int omap3xxx_prm_late_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int irq_num;
|
||||
int ret;
|
||||
|
||||
if (!(prm_features & PRM_HAS_IO_WAKEUP))
|
||||
return 0;
|
||||
@ -712,12 +711,8 @@ static int omap3xxx_prm_late_init(void)
|
||||
}
|
||||
|
||||
omap3xxx_prm_enable_io_wakeup();
|
||||
ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
|
||||
if (!ret)
|
||||
irq_set_status_flags(omap_prcm_event_to_irq("io"),
|
||||
IRQ_NOAUTOEN);
|
||||
|
||||
return ret;
|
||||
return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
|
||||
}
|
||||
|
||||
static void __exit omap3xxx_prm_exit(void)
|
||||
|
@ -336,6 +336,27 @@ static void omap44xx_prm_reconfigure_io_chain(void)
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
|
||||
*
|
||||
* Activates the I/O wakeup event latches and allows events logged by
|
||||
* those latches to signal a wakeup event to the PRCM. For I/O wakeups
|
||||
* to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
|
||||
* omap44xx_prm_reconfigure_io_chain() must be called. No return value.
|
||||
*/
|
||||
static void __init omap44xx_prm_enable_io_wakeup(void)
|
||||
{
|
||||
s32 inst = omap4_prmst_get_prm_dev_inst();
|
||||
|
||||
if (inst == PRM_INSTANCE_UNKNOWN)
|
||||
return;
|
||||
|
||||
omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
|
||||
OMAP4430_GLOBAL_WUEN_MASK,
|
||||
inst,
|
||||
omap4_prcm_irq_setup.pm_ctrl);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap44xx_prm_read_reset_sources - return the last SoC reset source
|
||||
*
|
||||
@ -668,6 +689,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
|
||||
.pwrdm_has_voltdm = omap4_check_vcvp,
|
||||
};
|
||||
|
||||
static int omap44xx_prm_late_init(void);
|
||||
|
||||
/*
|
||||
* XXX document
|
||||
*/
|
||||
@ -675,6 +698,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
|
||||
.read_reset_sources = &omap44xx_prm_read_reset_sources,
|
||||
.was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
|
||||
.clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
|
||||
.late_init = &omap44xx_prm_late_init,
|
||||
.assert_hardreset = omap4_prminst_assert_hardreset,
|
||||
.deassert_hardreset = omap4_prminst_deassert_hardreset,
|
||||
.is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
|
||||
@ -711,6 +735,37 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
|
||||
return prm_register(&omap44xx_prm_ll_data);
|
||||
}
|
||||
|
||||
static int omap44xx_prm_late_init(void)
|
||||
{
|
||||
int irq_num;
|
||||
|
||||
if (!(prm_features & PRM_HAS_IO_WAKEUP))
|
||||
return 0;
|
||||
|
||||
irq_num = of_irq_get(prm_init_data->np, 0);
|
||||
/*
|
||||
* Already have OMAP4 IRQ num. For all other platforms, we need
|
||||
* IRQ numbers from DT
|
||||
*/
|
||||
if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
|
||||
if (irq_num == -EPROBE_DEFER)
|
||||
return irq_num;
|
||||
|
||||
/* Have nothing to do */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Once OMAP4 DT is filled as well */
|
||||
if (irq_num >= 0) {
|
||||
omap4_prcm_irq_setup.irq = irq_num;
|
||||
omap4_prcm_irq_setup.xlate_irq = NULL;
|
||||
}
|
||||
|
||||
omap44xx_prm_enable_io_wakeup();
|
||||
|
||||
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
|
||||
}
|
||||
|
||||
static void __exit omap44xx_prm_exit(void)
|
||||
{
|
||||
prm_unregister(&omap44xx_prm_ll_data);
|
||||
|
@ -15,7 +15,7 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include "common.h"
|
||||
|
||||
static void __init sirfsoc_init_late(void)
|
||||
static void __init __maybe_unused sirfsoc_init_late(void)
|
||||
{
|
||||
sirfsoc_pm_init();
|
||||
}
|
||||
|
@ -566,6 +566,7 @@ config MACH_ICONTROL
|
||||
config ARCH_PXA_ESERIES
|
||||
bool "PXA based Toshiba e-series PDAs"
|
||||
select FB_W100
|
||||
select FB
|
||||
select PXA25x
|
||||
|
||||
config MACH_E330
|
||||
|
@ -17,11 +17,15 @@
|
||||
|
||||
#include <mach/regs-ost.h>
|
||||
|
||||
#define xip_irqpending() (ICIP & ICMR)
|
||||
/* restored July 2017, this did not build since 2011! */
|
||||
|
||||
#define ICIP io_p2v(0x40d00000)
|
||||
#define ICMR io_p2v(0x40d00004)
|
||||
#define xip_irqpending() (readl(ICIP) & readl(ICMR))
|
||||
|
||||
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
|
||||
#define xip_currtime() (OSCR)
|
||||
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
|
||||
#define xip_currtime() readl(OSCR)
|
||||
#define xip_elapsed_since(x) (signed)((readl(OSCR) - (x)) / 4)
|
||||
|
||||
/*
|
||||
* xip_cpu_idle() is used when waiting for a delay equal or larger than
|
||||
|
@ -25,8 +25,8 @@
|
||||
* *_SIZE is the size of the region
|
||||
* *_BASE is the virtual address
|
||||
*/
|
||||
#define RAM_SIZE 0x10000000
|
||||
#define RAM_START 0x10000000
|
||||
#define RPC_RAM_SIZE 0x10000000
|
||||
#define RPC_RAM_START 0x10000000
|
||||
|
||||
#define EASI_SIZE 0x08000000 /* EASI I/O */
|
||||
#define EASI_START 0x08000000
|
||||
|
@ -35,6 +35,31 @@ struct clk clk_##_name = { \
|
||||
|
||||
static DEFINE_SPINLOCK(clocks_lock);
|
||||
|
||||
/* Dummy clk routine to build generic kernel parts that may be using them */
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
return clk_get_rate(clk);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_round_rate);
|
||||
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
||||
|
||||
static void clk_gpio27_enable(struct clk *clk)
|
||||
{
|
||||
/*
|
||||
|
@ -20,7 +20,7 @@
|
||||
#define xip_irqpending() (ICIP & ICMR)
|
||||
|
||||
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
|
||||
#define xip_currtime() (OSCR)
|
||||
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
|
||||
#define xip_currtime() readl_relaxed(OSCR)
|
||||
#define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
|
||||
|
||||
#endif /* __ARCH_SA1100_MTD_XIP_H__ */
|
||||
|
@ -67,8 +67,12 @@ static int regulator_quirk_notify(struct notifier_block *nb,
|
||||
{
|
||||
struct device *dev = data;
|
||||
struct i2c_client *client;
|
||||
static bool done;
|
||||
u32 mon;
|
||||
|
||||
if (done)
|
||||
return 0;
|
||||
|
||||
mon = ioread32(irqc + IRQC_MONITOR);
|
||||
dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
|
||||
if (mon & REGULATOR_IRQ_MASK)
|
||||
@ -99,7 +103,7 @@ static int regulator_quirk_notify(struct notifier_block *nb,
|
||||
remove:
|
||||
dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
|
||||
|
||||
bus_unregister_notifier(&i2c_bus_type, nb);
|
||||
done = true;
|
||||
iounmap(irqc);
|
||||
return 0;
|
||||
}
|
||||
|
@ -133,6 +133,7 @@ static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
|
||||
|
||||
static struct arm_pmu_platdata db8500_pmu_platdata = {
|
||||
.handle_irq = db8500_pmu_handler,
|
||||
.irq_flags = IRQF_NOBALANCING | IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
|
||||
|
@ -93,3 +93,32 @@ void nuc900_subclk_enable(struct clk *clk, int enable)
|
||||
|
||||
__raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
|
||||
}
|
||||
|
||||
/* dummy functions, should not be called */
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
WARN_ON(clk);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_round_rate);
|
||||
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
WARN_ON(clk);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
WARN_ON(clk);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
WARN_ON(clk);
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
||||
|
@ -40,9 +40,21 @@ static void *arm_nommu_dma_alloc(struct device *dev, size_t size,
|
||||
|
||||
{
|
||||
const struct dma_map_ops *ops = &dma_noop_ops;
|
||||
void *ret;
|
||||
|
||||
/*
|
||||
* We are here because:
|
||||
* Try generic allocator first if we are advertised that
|
||||
* consistency is not required.
|
||||
*/
|
||||
|
||||
if (attrs & DMA_ATTR_NON_CONSISTENT)
|
||||
return ops->alloc(dev, size, dma_handle, gfp, attrs);
|
||||
|
||||
ret = dma_alloc_from_global_coherent(size, dma_handle);
|
||||
|
||||
/*
|
||||
* dma_alloc_from_global_coherent() may fail because:
|
||||
*
|
||||
* - no consistent DMA region has been defined, so we can't
|
||||
* continue.
|
||||
* - there is no space left in consistent DMA region, so we
|
||||
@ -50,11 +62,8 @@ static void *arm_nommu_dma_alloc(struct device *dev, size_t size,
|
||||
* advertised that consistency is not required.
|
||||
*/
|
||||
|
||||
if (attrs & DMA_ATTR_NON_CONSISTENT)
|
||||
return ops->alloc(dev, size, dma_handle, gfp, attrs);
|
||||
|
||||
WARN_ON_ONCE(1);
|
||||
return NULL;
|
||||
WARN_ON_ONCE(ret == NULL);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void arm_nommu_dma_free(struct device *dev, size_t size,
|
||||
@ -63,14 +72,31 @@ static void arm_nommu_dma_free(struct device *dev, size_t size,
|
||||
{
|
||||
const struct dma_map_ops *ops = &dma_noop_ops;
|
||||
|
||||
if (attrs & DMA_ATTR_NON_CONSISTENT)
|
||||
if (attrs & DMA_ATTR_NON_CONSISTENT) {
|
||||
ops->free(dev, size, cpu_addr, dma_addr, attrs);
|
||||
else
|
||||
WARN_ON_ONCE(1);
|
||||
} else {
|
||||
int ret = dma_release_from_global_coherent(get_order(size),
|
||||
cpu_addr);
|
||||
|
||||
WARN_ON_ONCE(ret == 0);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int arm_nommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
|
||||
void *cpu_addr, dma_addr_t dma_addr, size_t size,
|
||||
unsigned long attrs)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
|
||||
return ret;
|
||||
|
||||
return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size);
|
||||
}
|
||||
|
||||
|
||||
static void __dma_page_cpu_to_dev(phys_addr_t paddr, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
@ -173,6 +199,7 @@ static void arm_nommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist
|
||||
const struct dma_map_ops arm_nommu_dma_ops = {
|
||||
.alloc = arm_nommu_dma_alloc,
|
||||
.free = arm_nommu_dma_free,
|
||||
.mmap = arm_nommu_dma_mmap,
|
||||
.map_page = arm_nommu_dma_map_page,
|
||||
.unmap_page = arm_nommu_dma_unmap_page,
|
||||
.map_sg = arm_nommu_dma_map_sg,
|
||||
|
@ -851,7 +851,7 @@ static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
|
||||
unsigned long pfn = dma_to_pfn(dev, dma_addr);
|
||||
unsigned long off = vma->vm_pgoff;
|
||||
|
||||
if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
|
||||
if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
|
||||
return ret;
|
||||
|
||||
if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
|
||||
|
@ -452,7 +452,7 @@
|
||||
emac: ethernet@1c30000 {
|
||||
compatible = "allwinner,sun50i-a64-emac";
|
||||
syscon = <&syscon>;
|
||||
reg = <0x01c30000 0x100>;
|
||||
reg = <0x01c30000 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
resets = <&ccu RST_BUS_EMAC>;
|
||||
|
@ -400,7 +400,7 @@
|
||||
};
|
||||
|
||||
pwm_AO_ab: pwm@550 {
|
||||
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
|
||||
compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
|
||||
reg = <0x0 0x00550 0x0 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
|
@ -109,8 +109,8 @@
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clkc CLKID_FCLK_DIV4>;
|
||||
clock-names = "clkin0";
|
||||
clocks = <&xtal> , <&xtal>;
|
||||
clock-names = "clkin0", "clkin1" ;
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
|
@ -10,12 +10,20 @@
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
#include "meson-gxl-s905x-p212.dtsi"
|
||||
#include "meson-gxl-s905x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
|
||||
model = "Libre Technology CC";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cvbs-connector {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
@ -26,6 +34,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
@ -53,6 +66,39 @@
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc_card: regulator-vcc-card {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "VCC_CARD";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0>;
|
||||
|
||||
states = <3300000 0>,
|
||||
<1800000 1>;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_BOOT";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cvbs_vdac_port {
|
||||
@ -61,6 +107,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
|
||||
@ -73,20 +129,43 @@
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The following devices exists but are exposed on the general
|
||||
* purpose GPIO header. End user may well decide to use those pins
|
||||
* for another purpose
|
||||
*/
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
&sd_emmc_a {
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <100000000>;
|
||||
disable-wp;
|
||||
|
||||
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
|
||||
cd-inverted;
|
||||
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_card>;
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
status = "disabled";
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <50000000>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vddio_boot>;
|
||||
};
|
||||
|
||||
&wifi32k {
|
||||
status = "disabled";
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
@ -219,7 +219,7 @@
|
||||
reg = <0x18800 0x100>, <0x18C00 0x20>;
|
||||
gpiosb: gpio {
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_sb 0 0 29>;
|
||||
gpio-ranges = <&pinctrl_sb 0 0 30>;
|
||||
gpio-controller;
|
||||
interrupts =
|
||||
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -270,6 +270,7 @@
|
||||
interrupt-names = "mem", "ring0", "ring1",
|
||||
"ring2", "ring3", "eip";
|
||||
clocks = <&cpm_clk 1 26>;
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -64,7 +64,7 @@
|
||||
compatible = "marvell,armada-8k-rtc";
|
||||
reg = <0x284000 0x20>, <0x284080 0x24>;
|
||||
reg-names = "rtc", "rtc-soc";
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cps_ethernet: ethernet@0 {
|
||||
@ -261,6 +261,7 @@
|
||||
interrupt-names = "mem", "ring0", "ring1",
|
||||
"ring2", "ring3", "eip";
|
||||
clocks = <&cps_clk 1 26>;
|
||||
dma-coherent;
|
||||
/*
|
||||
* The cryptographic engine found on the cp110
|
||||
* master is enabled by default at the SoC
|
||||
|
@ -508,7 +508,7 @@
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <11289600 12288000>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
|
@ -281,7 +281,7 @@
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <11289600 12288000>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
|
@ -476,6 +476,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
|
||||
CONFIG_MSM_GCC_8916=y
|
||||
CONFIG_MSM_GCC_8994=y
|
||||
CONFIG_MSM_MMCC_8996=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HWSPINLOCK_QCOM=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
|
@ -435,7 +435,7 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
|
||||
" sub x30, x30, %[ret]\n"
|
||||
" cbnz x30, 1b\n"
|
||||
"2:")
|
||||
: [ret] "+&r" (x0), [v] "+Q" (v->counter)
|
||||
: [ret] "+r" (x0), [v] "+Q" (v->counter)
|
||||
:
|
||||
: __LL_SC_CLOBBERS, "cc", "memory");
|
||||
|
||||
|
@ -64,8 +64,10 @@
|
||||
* TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
|
||||
*/
|
||||
#define VA_BITS (CONFIG_ARM64_VA_BITS)
|
||||
#define VA_START (UL(0xffffffffffffffff) << VA_BITS)
|
||||
#define PAGE_OFFSET (UL(0xffffffffffffffff) << (VA_BITS - 1))
|
||||
#define VA_START (UL(0xffffffffffffffff) - \
|
||||
(UL(1) << VA_BITS) + 1)
|
||||
#define PAGE_OFFSET (UL(0xffffffffffffffff) - \
|
||||
(UL(1) << (VA_BITS - 1)) + 1)
|
||||
#define KIMAGE_VADDR (MODULES_END)
|
||||
#define MODULES_END (MODULES_VADDR + MODULES_VSIZE)
|
||||
#define MODULES_VADDR (VA_START + KASAN_SHADOW_SIZE)
|
||||
|
@ -492,7 +492,7 @@ asm(
|
||||
* the "%x0" template means XZR.
|
||||
*/
|
||||
#define write_sysreg(v, r) do { \
|
||||
u64 __val = (u64)v; \
|
||||
u64 __val = (u64)(v); \
|
||||
asm volatile("msr " __stringify(r) ", %x0" \
|
||||
: : "rZ" (__val)); \
|
||||
} while (0)
|
||||
@ -508,7 +508,7 @@ asm(
|
||||
})
|
||||
|
||||
#define write_sysreg_s(v, r) do { \
|
||||
u64 __val = (u64)v; \
|
||||
u64 __val = (u64)(v); \
|
||||
asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
|
||||
} while (0)
|
||||
|
||||
|
@ -69,7 +69,7 @@ static inline void set_fs(mm_segment_t fs)
|
||||
*/
|
||||
#define __range_ok(addr, size) \
|
||||
({ \
|
||||
unsigned long __addr = (unsigned long __force)(addr); \
|
||||
unsigned long __addr = (unsigned long)(addr); \
|
||||
unsigned long flag, roksum; \
|
||||
__chk_user_ptr(addr); \
|
||||
asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \
|
||||
|
@ -82,8 +82,8 @@ static const char *__init cpu_read_enable_method(int cpu)
|
||||
* Don't warn spuriously.
|
||||
*/
|
||||
if (cpu != 0)
|
||||
pr_err("%s: missing enable-method property\n",
|
||||
dn->full_name);
|
||||
pr_err("%pOF: missing enable-method property\n",
|
||||
dn);
|
||||
}
|
||||
} else {
|
||||
enable_method = acpi_get_enable_method(cpu);
|
||||
|
@ -469,7 +469,7 @@ static u64 __init of_get_cpu_mpidr(struct device_node *dn)
|
||||
*/
|
||||
cell = of_get_property(dn, "reg", NULL);
|
||||
if (!cell) {
|
||||
pr_err("%s: missing reg property\n", dn->full_name);
|
||||
pr_err("%pOF: missing reg property\n", dn);
|
||||
return INVALID_HWID;
|
||||
}
|
||||
|
||||
@ -478,7 +478,7 @@ static u64 __init of_get_cpu_mpidr(struct device_node *dn)
|
||||
* Non affinity bits must be set to 0 in the DT
|
||||
*/
|
||||
if (hwid & ~MPIDR_HWID_BITMASK) {
|
||||
pr_err("%s: invalid reg property\n", dn->full_name);
|
||||
pr_err("%pOF: invalid reg property\n", dn);
|
||||
return INVALID_HWID;
|
||||
}
|
||||
return hwid;
|
||||
@ -627,8 +627,8 @@ static void __init of_parse_and_init_cpus(void)
|
||||
goto next;
|
||||
|
||||
if (is_mpidr_duplicate(cpu_count, hwid)) {
|
||||
pr_err("%s: duplicate cpu reg properties in the DT\n",
|
||||
dn->full_name);
|
||||
pr_err("%pOF: duplicate cpu reg properties in the DT\n",
|
||||
dn);
|
||||
goto next;
|
||||
}
|
||||
|
||||
@ -640,8 +640,8 @@ static void __init of_parse_and_init_cpus(void)
|
||||
*/
|
||||
if (hwid == cpu_logical_map(0)) {
|
||||
if (bootcpu_valid) {
|
||||
pr_err("%s: duplicate boot cpu reg property in DT\n",
|
||||
dn->full_name);
|
||||
pr_err("%pOF: duplicate boot cpu reg property in DT\n",
|
||||
dn);
|
||||
goto next;
|
||||
}
|
||||
|
||||
|
@ -45,7 +45,7 @@ static int __init get_cpu_for_node(struct device_node *node)
|
||||
}
|
||||
}
|
||||
|
||||
pr_crit("Unable to find CPU node for %s\n", cpu_node->full_name);
|
||||
pr_crit("Unable to find CPU node for %pOF\n", cpu_node);
|
||||
|
||||
of_node_put(cpu_node);
|
||||
return -1;
|
||||
@ -71,8 +71,8 @@ static int __init parse_core(struct device_node *core, int cluster_id,
|
||||
cpu_topology[cpu].core_id = core_id;
|
||||
cpu_topology[cpu].thread_id = i;
|
||||
} else {
|
||||
pr_err("%s: Can't get CPU for thread\n",
|
||||
t->full_name);
|
||||
pr_err("%pOF: Can't get CPU for thread\n",
|
||||
t);
|
||||
of_node_put(t);
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -84,15 +84,15 @@ static int __init parse_core(struct device_node *core, int cluster_id,
|
||||
cpu = get_cpu_for_node(core);
|
||||
if (cpu >= 0) {
|
||||
if (!leaf) {
|
||||
pr_err("%s: Core has both threads and CPU\n",
|
||||
core->full_name);
|
||||
pr_err("%pOF: Core has both threads and CPU\n",
|
||||
core);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cpu_topology[cpu].cluster_id = cluster_id;
|
||||
cpu_topology[cpu].core_id = core_id;
|
||||
} else if (leaf) {
|
||||
pr_err("%s: Can't get CPU for leaf core\n", core->full_name);
|
||||
pr_err("%pOF: Can't get CPU for leaf core\n", core);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -137,8 +137,8 @@ static int __init parse_cluster(struct device_node *cluster, int depth)
|
||||
has_cores = true;
|
||||
|
||||
if (depth == 0) {
|
||||
pr_err("%s: cpu-map children should be clusters\n",
|
||||
c->full_name);
|
||||
pr_err("%pOF: cpu-map children should be clusters\n",
|
||||
c);
|
||||
of_node_put(c);
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -146,8 +146,8 @@ static int __init parse_cluster(struct device_node *cluster, int depth)
|
||||
if (leaf) {
|
||||
ret = parse_core(c, cluster_id, core_id++);
|
||||
} else {
|
||||
pr_err("%s: Non-leaf cluster with core %s\n",
|
||||
cluster->full_name, name);
|
||||
pr_err("%pOF: Non-leaf cluster with core %s\n",
|
||||
cluster, name);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
@ -159,7 +159,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth)
|
||||
} while (c);
|
||||
|
||||
if (leaf && !has_cores)
|
||||
pr_warn("%s: empty cluster\n", cluster->full_name);
|
||||
pr_warn("%pOF: empty cluster\n", cluster);
|
||||
|
||||
if (leaf)
|
||||
cluster_id++;
|
||||
|
@ -274,10 +274,12 @@ static DEFINE_RAW_SPINLOCK(die_lock);
|
||||
void die(const char *str, struct pt_regs *regs, int err)
|
||||
{
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&die_lock, flags);
|
||||
|
||||
oops_enter();
|
||||
|
||||
raw_spin_lock_irq(&die_lock);
|
||||
console_verbose();
|
||||
bust_spinlocks(1);
|
||||
ret = __die(str, err, regs);
|
||||
@ -287,13 +289,15 @@ void die(const char *str, struct pt_regs *regs, int err)
|
||||
|
||||
bust_spinlocks(0);
|
||||
add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
|
||||
raw_spin_unlock_irq(&die_lock);
|
||||
oops_exit();
|
||||
|
||||
if (in_interrupt())
|
||||
panic("Fatal exception in interrupt");
|
||||
if (panic_on_oops)
|
||||
panic("Fatal exception");
|
||||
|
||||
raw_spin_unlock_irqrestore(&die_lock, flags);
|
||||
|
||||
if (ret != NOTIFY_STOP)
|
||||
do_exit(SIGSEGV);
|
||||
}
|
||||
@ -519,7 +523,7 @@ static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
|
||||
{
|
||||
int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
|
||||
|
||||
pt_regs_write_reg(regs, rt, read_sysreg(cntfrq_el0));
|
||||
pt_regs_write_reg(regs, rt, arch_timer_get_rate());
|
||||
regs->pc += 4;
|
||||
}
|
||||
|
||||
|
@ -764,7 +764,7 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
|
||||
if (p->is_write) {
|
||||
if (r->CRm & 0x2)
|
||||
/* accessing PMOVSSET_EL0 */
|
||||
kvm_pmu_overflow_set(vcpu, p->regval & mask);
|
||||
vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
|
||||
else
|
||||
/* accessing PMOVSCLR_EL0 */
|
||||
vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
|
||||
|