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spi: sh-msiof: Add reset of registers before starting transfer
In accordance with hardware specification Ver 1.0, reset register transmission / reception setting before transfer. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> [geert: Use readl_poll_timeout_atomic()] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -132,6 +132,8 @@ struct sh_msiof_spi_priv {
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#define CTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
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#define CTR_TXE BIT(9) /* Transmit Enable */
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#define CTR_RXE BIT(8) /* Receive Enable */
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#define CTR_TXRST BIT(1) /* Transmit Reset */
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#define CTR_RXRST BIT(0) /* Receive Reset */
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/* FCTR */
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#define FCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */
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@ -241,6 +243,19 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
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{
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u32 mask = CTR_TXRST | CTR_RXRST;
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u32 data;
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data = sh_msiof_read(p, CTR);
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data |= mask;
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sh_msiof_write(p, CTR, data);
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readl_poll_timeout_atomic(p->mapbase + CTR, data, !(data & mask), 1,
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100);
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}
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static const u32 sh_msiof_spi_div_array[] = {
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SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
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SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
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@ -920,6 +935,9 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr,
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bool swab;
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int ret;
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/* reset registers */
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sh_msiof_spi_reset_regs(p);
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/* setup clocks (clock already enabled in chipselect()) */
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if (!spi_controller_is_slave(p->ctlr))
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sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
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