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net: mscc: ocelot: expose ocelot_pll5_init routine
Ocelot chips have an internal PLL that must be used when communicating through external phys. Expose the init routine, so it can be used by other drivers. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -7,6 +7,7 @@
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#include <linux/dsa/ocelot.h>
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#include <linux/if_bridge.h>
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#include <linux/iopoll.h>
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#include <soc/mscc/ocelot_hsio.h>
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#include <soc/mscc/ocelot_vcap.h>
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#include "ocelot.h"
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#include "ocelot_vcap.h"
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@ -211,6 +212,36 @@ static void ocelot_mact_init(struct ocelot *ocelot)
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ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
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}
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void ocelot_pll5_init(struct ocelot *ocelot)
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{
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/* Configure PLL5. This will need a proper CCF driver
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* The values are coming from the VTSS API for Ocelot
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*/
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regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
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HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
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HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
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regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
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HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
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HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
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HSIO_PLL5G_CFG0_ENA_BIAS |
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HSIO_PLL5G_CFG0_ENA_VCO_BUF |
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HSIO_PLL5G_CFG0_ENA_CP1 |
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HSIO_PLL5G_CFG0_SELCPI(2) |
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HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
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HSIO_PLL5G_CFG0_SELBGV820(4) |
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HSIO_PLL5G_CFG0_DIV4 |
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HSIO_PLL5G_CFG0_ENA_CLKTREE |
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HSIO_PLL5G_CFG0_ENA_LANE);
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regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
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HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
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HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
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HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
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HSIO_PLL5G_CFG2_ENA_AMPCTRL |
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HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
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HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
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}
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EXPORT_SYMBOL(ocelot_pll5_init);
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static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
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{
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ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
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@ -18,7 +18,6 @@
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#include <soc/mscc/ocelot.h>
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#include <soc/mscc/ocelot_vcap.h>
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#include <soc/mscc/ocelot_hsio.h>
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#include <soc/mscc/vsc7514_regs.h>
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#include "ocelot_fdma.h"
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#include "ocelot.h"
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@ -26,35 +25,6 @@
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#define VSC7514_VCAP_POLICER_BASE 128
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#define VSC7514_VCAP_POLICER_MAX 191
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static void ocelot_pll5_init(struct ocelot *ocelot)
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{
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/* Configure PLL5. This will need a proper CCF driver
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* The values are coming from the VTSS API for Ocelot
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*/
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regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
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HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
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HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
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regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
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HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
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HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
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HSIO_PLL5G_CFG0_ENA_BIAS |
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HSIO_PLL5G_CFG0_ENA_VCO_BUF |
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HSIO_PLL5G_CFG0_ENA_CP1 |
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HSIO_PLL5G_CFG0_SELCPI(2) |
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HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
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HSIO_PLL5G_CFG0_SELBGV820(4) |
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HSIO_PLL5G_CFG0_DIV4 |
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HSIO_PLL5G_CFG0_ENA_CLKTREE |
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HSIO_PLL5G_CFG0_ENA_LANE);
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regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
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HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
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HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
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HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
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HSIO_PLL5G_CFG2_ENA_AMPCTRL |
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HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
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HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
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}
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static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
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{
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int ret;
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@ -1183,4 +1183,6 @@ ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
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}
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#endif
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void ocelot_pll5_init(struct ocelot *ocelot);
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#endif
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