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sh: Support for SH-4A memory barriers.
SH-4A supports 'synco' as a barrier, sprinkle it around the cache ops as necessary.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -184,6 +184,7 @@ void flush_cache_sigtramp(unsigned long addr)
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i++, index += cpu_data->icache.way_incr)
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ctrl_outl(0, index); /* Clear out Valid-bit */
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back_to_P1();
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wmb();
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local_irq_restore(flags);
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}
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@ -223,6 +224,8 @@ void flush_dcache_page(struct page *page)
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flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x2000, phys);
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flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x3000, phys);
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}
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wmb();
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}
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static inline void flush_icache_all(void)
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@ -247,6 +250,7 @@ void flush_dcache_all(void)
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__flush_dcache_all();
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else
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__flush_dcache_all_ex();
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wmb();
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}
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void flush_cache_all(void)
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@ -377,5 +381,6 @@ void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr, int len)
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{
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flush_cache_page(vma, addr, page_to_pfn(page));
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mb();
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}
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@ -84,10 +84,17 @@ static __inline__ unsigned long tas(volatile int *m)
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extern void __xchg_called_with_bad_pointer(void);
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#ifdef CONFIG_CPU_SH4A
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("synco": : :"memory")
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#define read_barrier_depends() do { } while(0)
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#else
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#define mb() __asm__ __volatile__ ("": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#define read_barrier_depends() do { } while(0)
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#endif
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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