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x86/speculation: Protect against userspace-userspace spectreRSB
The article "Spectre Returns! Speculation Attacks using the Return Stack Buffer" [1] describes two new (sub-)variants of spectrev2-like attacks, making use solely of the RSB contents even on CPUs that don't fallback to BTB on RSB underflow (Skylake+). Mitigate userspace-userspace attacks by always unconditionally filling RSB on context switch when the generic spectrev2 mitigation has been enabled. [1] https://arxiv.org/pdf/1807.07940.pdf Signed-off-by: Jiri Kosina <jkosina@suse.cz> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Acked-by: Tim Chen <tim.c.chen@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Borislav Petkov <bp@suse.de> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1807261308190.997@cbobk.fhfr.pm
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@ -313,23 +313,6 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
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return cmd;
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}
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/* Check for Skylake-like CPUs (for RSB handling) */
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static bool __init is_skylake_era(void)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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boot_cpu_data.x86 == 6) {
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switch (boot_cpu_data.x86_model) {
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case INTEL_FAM6_SKYLAKE_MOBILE:
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case INTEL_FAM6_SKYLAKE_DESKTOP:
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case INTEL_FAM6_SKYLAKE_X:
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case INTEL_FAM6_KABYLAKE_MOBILE:
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case INTEL_FAM6_KABYLAKE_DESKTOP:
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return true;
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}
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}
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return false;
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}
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static void __init spectre_v2_select_mitigation(void)
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{
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enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
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@ -390,22 +373,15 @@ retpoline_auto:
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pr_info("%s\n", spectre_v2_strings[mode]);
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/*
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* If neither SMEP nor PTI are available, there is a risk of
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* hitting userspace addresses in the RSB after a context switch
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* from a shallow call stack to a deeper one. To prevent this fill
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* the entire RSB, even when using IBRS.
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* If spectre v2 protection has been enabled, unconditionally fill
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* RSB during a context switch; this protects against two independent
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* issues:
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*
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* Skylake era CPUs have a separate issue with *underflow* of the
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* RSB, when they will predict 'ret' targets from the generic BTB.
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* The proper mitigation for this is IBRS. If IBRS is not supported
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* or deactivated in favour of retpolines the RSB fill on context
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* switch is required.
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* - RSB underflow (and switch to BTB) on Skylake+
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* - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
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*/
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if ((!boot_cpu_has(X86_FEATURE_PTI) &&
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!boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
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setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
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pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
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}
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setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
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pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
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/* Initialize Indirect Branch Prediction Barrier if supported */
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if (boot_cpu_has(X86_FEATURE_IBPB)) {
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