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iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG
This is a 32-bit register. Apparently harmless on real hardware, but causing justified warnings in simulation. Signed-off-by: CQ Tang <cq.tang@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Cc: stable@vger.kernel.org
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@ -1347,7 +1347,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
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sts = readl(iommu->reg + DMAR_GSTS_REG);
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if (!(sts & DMA_GSTS_QIES))
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goto end;
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@ -629,7 +629,7 @@ static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
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sts = readl(iommu->reg + DMAR_GSTS_REG);
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if (!(sts & DMA_GSTS_IRES))
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goto end;
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