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riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT

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RISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenance
helpers, which are built into the kernel unconditionally.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231018052654.50074-2-hch@lst.de
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Christoph Hellwig 2023-10-18 07:26:52 +02:00 committed by Geert Uytterhoeven
parent 1531309aa2
commit fd96278127
2 changed files with 1 additions and 2 deletions
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1
arch/riscv/Kconfig
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@ -277,7 +277,6 @@ config RISCV_DMA_NONCOHERENT
config RISCV_NONSTANDARD_CACHE_OPS config RISCV_NONSTANDARD_CACHE_OPS
bool bool
depends on RISCV_DMA_NONCOHERENT
help help
This enables function pointer support for non-standard noncoherent This enables function pointer support for non-standard noncoherent
systems to handle cache management. systems to handle cache management.

2
drivers/cache/Kconfig vendored
View File

@ -3,7 +3,7 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller" bool "Andes Technology AX45MP L2 Cache controller"
depends on RISCV_DMA_NONCOHERENT depends on RISCV
select RISCV_NONSTANDARD_CACHE_OPS select RISCV_NONSTANDARD_CACHE_OPS
help help
Support for the L2 cache controller on Andes Technology AX45MP platforms. Support for the L2 cache controller on Andes Technology AX45MP platforms.