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iommu/amd: Introduce iommu_v1_map_page and iommu_v1_unmap_page
These implement map and unmap for AMD IOMMU v1 pagetable, which will be used by the IO pagetable framework. Also clean up unused extern function declarations. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Link: https://lore.kernel.org/r/20201215073705.123786-13-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -133,19 +133,6 @@ void amd_iommu_apply_ivrs_quirks(void);
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static inline void amd_iommu_apply_ivrs_quirks(void) { }
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#endif
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/* TODO: These are temporary and will be removed once fully transition */
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extern int iommu_map_page(struct protection_domain *dom,
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unsigned long bus_addr,
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unsigned long phys_addr,
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unsigned long page_size,
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int prot,
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gfp_t gfp);
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extern unsigned long iommu_unmap_page(struct protection_domain *dom,
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unsigned long bus_addr,
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unsigned long page_size);
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extern u64 *fetch_pte(struct amd_io_pgtable *pgtable,
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unsigned long address,
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unsigned long *page_size);
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extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
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u64 *root, int mode);
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#endif
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@ -311,9 +311,9 @@ static u64 *alloc_pte(struct protection_domain *domain,
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* This function checks if there is a PTE for a given dma address. If
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* there is one, it returns the pointer to it.
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*/
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u64 *fetch_pte(struct amd_io_pgtable *pgtable,
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unsigned long address,
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unsigned long *page_size)
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static u64 *fetch_pte(struct amd_io_pgtable *pgtable,
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unsigned long address,
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unsigned long *page_size)
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{
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int level;
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u64 *pte;
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@ -386,13 +386,10 @@ static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
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* supporting all features of AMD IOMMU page tables like level skipping
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* and full 64 bit address spaces.
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*/
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int iommu_map_page(struct protection_domain *dom,
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unsigned long iova,
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unsigned long paddr,
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unsigned long size,
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int prot,
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gfp_t gfp)
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static int iommu_v1_map_page(struct io_pgtable_ops *ops, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
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{
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struct protection_domain *dom = io_pgtable_ops_to_domain(ops);
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struct page *freelist = NULL;
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bool updated = false;
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u64 __pte, *pte;
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@ -455,11 +452,11 @@ out:
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return ret;
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}
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unsigned long iommu_unmap_page(struct protection_domain *dom,
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unsigned long iova,
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unsigned long size)
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static unsigned long iommu_v1_unmap_page(struct io_pgtable_ops *ops,
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unsigned long iova,
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size_t size,
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struct iommu_iotlb_gather *gather)
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{
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struct io_pgtable_ops *ops = &dom->iop.iop.ops;
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struct amd_io_pgtable *pgtable = io_pgtable_ops_to_data(ops);
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unsigned long long unmapped;
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unsigned long unmap_size;
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@ -548,6 +545,8 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo
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cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE,
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cfg->tlb = &v1_flush_ops;
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pgtable->iop.ops.map = iommu_v1_map_page;
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pgtable->iop.ops.unmap = iommu_v1_unmap_page;
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pgtable->iop.ops.iova_to_phys = iommu_v1_iova_to_phys;
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return &pgtable->iop;
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@ -2065,8 +2065,9 @@ static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
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gfp_t gfp)
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{
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struct protection_domain *domain = to_pdomain(dom);
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struct io_pgtable_ops *ops = &domain->iop.iop.ops;
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int prot = 0;
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int ret;
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int ret = -EINVAL;
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if (domain->iop.mode == PAGE_MODE_NONE)
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return -EINVAL;
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@ -2076,9 +2077,10 @@ static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
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if (iommu_prot & IOMMU_WRITE)
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prot |= IOMMU_PROT_IW;
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ret = iommu_map_page(domain, iova, paddr, page_size, prot, gfp);
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domain_flush_np_cache(domain, iova, page_size);
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if (ops->map) {
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ret = ops->map(ops, iova, paddr, page_size, prot, gfp);
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domain_flush_np_cache(domain, iova, page_size);
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}
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return ret;
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}
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@ -2088,11 +2090,12 @@ static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
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struct iommu_iotlb_gather *gather)
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{
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struct protection_domain *domain = to_pdomain(dom);
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struct io_pgtable_ops *ops = &domain->iop.iop.ops;
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if (domain->iop.mode == PAGE_MODE_NONE)
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return 0;
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return iommu_unmap_page(domain, iova, page_size);
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return (ops->unmap) ? ops->unmap(ops, iova, page_size, gather) : 0;
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}
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static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
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