mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-25 21:24:08 +08:00
Merge branches 'core-objtool-for-linus', 'x86-cleanups-for-linus' and 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 objtool, cleanup, and apic updates from Ingo Molnar:
"Objtool:
- Fix a gawk 5.0 incompatibility in gen-insn-attr-x86.awk. Most
distros are still on gawk 4.2.x.
Cleanup:
- Misc cleanups, plus the removal of obsolete code such as Calgary
IOMMU support, which code hasn't seen any real testing in a long
time and there's no known users left.
apic:
- Two changes: a cleanup and a fix for an (old) race for oneshot
threaded IRQ handlers"
* 'core-objtool-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/insn: Fix awk regexp warnings
* 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86: Remove unused asm/rio.h
x86: Fix typos in comments
x86/pci: Remove #ifdef __KERNEL__ guard from <asm/pci.h>
x86/pci: Remove pci_64.h
x86: Remove the calgary IOMMU driver
x86/apic, x86/uprobes: Correct parameter names in kernel-doc comments
x86/kdump: Remove the unused crash_copy_backup_region()
x86/nmi: Remove stale EDAC include leftover
* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/ioapic: Rename misnamed functions
x86/ioapic: Prevent inconsistent state when moving an interrupt
This commit is contained in:
Linus Torvalds
commit
fd2615908d
10
MAINTAINERS
10
MAINTAINERS
@ -3649,16 +3649,6 @@ L: cake@lists.bufferbloat.net (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: net/sched/sch_cake.c
|
||||
|
||||
CALGARY x86-64 IOMMU
|
||||
M: Muli Ben-Yehuda <mulix@mulix.org>
|
||||
M: Jon Mason <jdmason@kudzu.us>
|
||||
L: iommu@lists.linux-foundation.org
|
||||
S: Maintained
|
||||
F: arch/x86/kernel/pci-calgary_64.c
|
||||
F: arch/x86/kernel/tce_64.c
|
||||
F: arch/x86/include/asm/calgary.h
|
||||
F: arch/x86/include/asm/tce.h
|
||||
|
||||
CAN NETWORK DRIVERS
|
||||
M: Wolfgang Grandegger <wg@grandegger.com>
|
||||
M: Marc Kleine-Budde <mkl@pengutronix.de>
|
||||
|
||||
@ -932,36 +932,6 @@ config GART_IOMMU
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
config CALGARY_IOMMU
|
||||
bool "IBM Calgary IOMMU support"
|
||||
select IOMMU_HELPER
|
||||
select SWIOTLB
|
||||
depends on X86_64 && PCI
|
||||
---help---
|
||||
Support for hardware IOMMUs in IBM's xSeries x366 and x460
|
||||
systems. Needed to run systems with more than 3GB of memory
|
||||
properly with 32-bit PCI devices that do not support DAC
|
||||
(Double Address Cycle). Calgary also supports bus level
|
||||
isolation, where all DMAs pass through the IOMMU. This
|
||||
prevents them from going anywhere except their intended
|
||||
destination. This catches hard-to-find kernel bugs and
|
||||
mis-behaving drivers and devices that do not use the DMA-API
|
||||
properly to set up their DMA buffers. The IOMMU can be
|
||||
turned off at boot time with the iommu=off parameter.
|
||||
Normally the kernel will make the right choice by itself.
|
||||
If unsure, say Y.
|
||||
|
||||
config CALGARY_IOMMU_ENABLED_BY_DEFAULT
|
||||
def_bool y
|
||||
prompt "Should Calgary be enabled by default?"
|
||||
depends on CALGARY_IOMMU
|
||||
---help---
|
||||
Should Calgary be enabled by default? if you choose 'y', Calgary
|
||||
will be used (if it exists). If you choose 'n', Calgary will not be
|
||||
used even if it exists. If you choose 'n' and would like to use
|
||||
Calgary anyway, pass 'iommu=calgary' on the kernel command line.
|
||||
If unsure, say Y.
|
||||
|
||||
config MAXSMP
|
||||
bool "Enable Maximum number of SMP Processors and NUMA Nodes"
|
||||
depends on X86_64 && SMP && DEBUG_KERNEL
|
||||
|
||||
@ -25,7 +25,6 @@ CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_CALGARY_IOMMU=y
|
||||
CONFIG_NR_CPUS=64
|
||||
CONFIG_SCHED_SMT=y
|
||||
CONFIG_PREEMPT_VOLUNTARY=y
|
||||
|
||||
@ -1,57 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Derived from include/asm-powerpc/iommu.h
|
||||
*
|
||||
* Copyright IBM Corporation, 2006-2007
|
||||
*
|
||||
* Author: Jon Mason <jdmason@us.ibm.com>
|
||||
* Author: Muli Ben-Yehuda <muli@il.ibm.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_X86_CALGARY_H
|
||||
#define _ASM_X86_CALGARY_H
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/timer.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
struct iommu_table {
|
||||
const struct cal_chipset_ops *chip_ops; /* chipset specific funcs */
|
||||
unsigned long it_base; /* mapped address of tce table */
|
||||
unsigned long it_hint; /* Hint for next alloc */
|
||||
unsigned long *it_map; /* A simple allocation bitmap for now */
|
||||
void __iomem *bbar; /* Bridge BAR */
|
||||
u64 tar_val; /* Table Address Register */
|
||||
struct timer_list watchdog_timer;
|
||||
spinlock_t it_lock; /* Protects it_map */
|
||||
unsigned int it_size; /* Size of iommu table in entries */
|
||||
unsigned char it_busno; /* Bus number this table belongs to */
|
||||
};
|
||||
|
||||
struct cal_chipset_ops {
|
||||
void (*handle_quirks)(struct iommu_table *tbl, struct pci_dev *dev);
|
||||
void (*tce_cache_blast)(struct iommu_table *tbl);
|
||||
void (*dump_error_regs)(struct iommu_table *tbl);
|
||||
};
|
||||
|
||||
#define TCE_TABLE_SIZE_UNSPECIFIED ~0
|
||||
#define TCE_TABLE_SIZE_64K 0
|
||||
#define TCE_TABLE_SIZE_128K 1
|
||||
#define TCE_TABLE_SIZE_256K 2
|
||||
#define TCE_TABLE_SIZE_512K 3
|
||||
#define TCE_TABLE_SIZE_1M 4
|
||||
#define TCE_TABLE_SIZE_2M 5
|
||||
#define TCE_TABLE_SIZE_4M 6
|
||||
#define TCE_TABLE_SIZE_8M 7
|
||||
|
||||
extern int use_calgary;
|
||||
|
||||
#ifdef CONFIG_CALGARY_IOMMU
|
||||
extern int detect_calgary(void);
|
||||
#else
|
||||
static inline int detect_calgary(void) { return -ENODEV; }
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_X86_CALGARY_H */
|
||||
@ -3,7 +3,6 @@
|
||||
#define _ASM_X86_CRASH_H
|
||||
|
||||
int crash_load_segments(struct kimage *image);
|
||||
int crash_copy_backup_region(struct kimage *image);
|
||||
int crash_setup_memmap_entries(struct kimage *image,
|
||||
struct boot_params *params);
|
||||
void crash_smp_send_stop(void);
|
||||
|
||||
@ -12,8 +12,6 @@
|
||||
#include <asm/pat.h>
|
||||
#include <asm/x86_init.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
struct pci_sysdata {
|
||||
int domain; /* PCI domain */
|
||||
int node; /* NUMA node */
|
||||
@ -118,11 +116,6 @@ void native_restore_msi_irqs(struct pci_dev *dev);
|
||||
#define native_setup_msi_irqs NULL
|
||||
#define native_teardown_msi_irq NULL
|
||||
#endif
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
#include <asm/pci_64.h>
|
||||
#endif
|
||||
|
||||
/* generic pci stuff */
|
||||
#include <asm-generic/pci.h>
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ASM_X86_PCI_64_H
|
||||
#define _ASM_X86_PCI_64_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#ifdef CONFIG_CALGARY_IOMMU
|
||||
static inline void *pci_iommu(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_sysdata *sd = bus->sysdata;
|
||||
return sd->iommu;
|
||||
}
|
||||
|
||||
static inline void set_pci_iommu(struct pci_bus *bus, void *val)
|
||||
{
|
||||
struct pci_sysdata *sd = bus->sysdata;
|
||||
sd->iommu = val;
|
||||
}
|
||||
#endif /* CONFIG_CALGARY_IOMMU */
|
||||
|
||||
extern int (*pci_config_read)(int seg, int bus, int dev, int fn,
|
||||
int reg, int len, u32 *value);
|
||||
extern int (*pci_config_write)(int seg, int bus, int dev, int fn,
|
||||
int reg, int len, u32 value);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _ASM_X86_PCI_64_H */
|
||||
@ -1,64 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Derived from include/asm-x86/mach-summit/mach_mpparse.h
|
||||
* and include/asm-x86/mach-default/bios_ebda.h
|
||||
*
|
||||
* Author: Laurent Vivier <Laurent.Vivier@bull.net>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_X86_RIO_H
|
||||
#define _ASM_X86_RIO_H
|
||||
|
||||
#define RIO_TABLE_VERSION 3
|
||||
|
||||
struct rio_table_hdr {
|
||||
u8 version; /* Version number of this data structure */
|
||||
u8 num_scal_dev; /* # of Scalability devices */
|
||||
u8 num_rio_dev; /* # of RIO I/O devices */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct scal_detail {
|
||||
u8 node_id; /* Scalability Node ID */
|
||||
u32 CBAR; /* Address of 1MB register space */
|
||||
u8 port0node; /* Node ID port connected to: 0xFF=None */
|
||||
u8 port0port; /* Port num port connected to: 0,1,2, or */
|
||||
/* 0xFF=None */
|
||||
u8 port1node; /* Node ID port connected to: 0xFF = None */
|
||||
u8 port1port; /* Port num port connected to: 0,1,2, or */
|
||||
/* 0xFF=None */
|
||||
u8 port2node; /* Node ID port connected to: 0xFF = None */
|
||||
u8 port2port; /* Port num port connected to: 0,1,2, or */
|
||||
/* 0xFF=None */
|
||||
u8 chassis_num; /* 1 based Chassis number (1 = boot node) */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct rio_detail {
|
||||
u8 node_id; /* RIO Node ID */
|
||||
u32 BBAR; /* Address of 1MB register space */
|
||||
u8 type; /* Type of device */
|
||||
u8 owner_id; /* Node ID of Hurricane that owns this */
|
||||
/* node */
|
||||
u8 port0node; /* Node ID port connected to: 0xFF=None */
|
||||
u8 port0port; /* Port num port connected to: 0,1,2, or */
|
||||
/* 0xFF=None */
|
||||
u8 port1node; /* Node ID port connected to: 0xFF=None */
|
||||
u8 port1port; /* Port num port connected to: 0,1,2, or */
|
||||
/* 0xFF=None */
|
||||
u8 first_slot; /* Lowest slot number below this Calgary */
|
||||
u8 status; /* Bit 0 = 1 : the XAPIC is used */
|
||||
/* = 0 : the XAPIC is not used, ie: */
|
||||
/* ints fwded to another XAPIC */
|
||||
/* Bits1:7 Reserved */
|
||||
u8 WP_index; /* instance index - lower ones have */
|
||||
/* lower slot numbers/PCI bus numbers */
|
||||
u8 chassis_num; /* 1 based Chassis number */
|
||||
} __attribute__((packed));
|
||||
|
||||
enum {
|
||||
HURR_SCALABILTY = 0, /* Hurricane Scalability info */
|
||||
HURR_RIOIB = 2, /* Hurricane RIOIB info */
|
||||
COMPAT_CALGARY = 4, /* Compatibility Calgary */
|
||||
ALT_CALGARY = 5, /* Second Planar Calgary */
|
||||
};
|
||||
|
||||
#endif /* _ASM_X86_RIO_H */
|
||||
@ -1,35 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* This file is derived from asm-powerpc/tce.h.
|
||||
*
|
||||
* Copyright (C) IBM Corporation, 2006
|
||||
*
|
||||
* Author: Muli Ben-Yehuda <muli@il.ibm.com>
|
||||
* Author: Jon Mason <jdmason@us.ibm.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_X86_TCE_H
|
||||
#define _ASM_X86_TCE_H
|
||||
|
||||
extern unsigned int specified_table_size;
|
||||
struct iommu_table;
|
||||
|
||||
#define TCE_ENTRY_SIZE 8 /* in bytes */
|
||||
|
||||
#define TCE_READ_SHIFT 0
|
||||
#define TCE_WRITE_SHIFT 1
|
||||
#define TCE_HUBID_SHIFT 2 /* unused */
|
||||
#define TCE_RSVD_SHIFT 8 /* unused */
|
||||
#define TCE_RPN_SHIFT 12
|
||||
#define TCE_UNUSED_SHIFT 48 /* unused */
|
||||
|
||||
#define TCE_RPN_MASK 0x0000fffffffff000ULL
|
||||
|
||||
extern void tce_build(struct iommu_table *tbl, unsigned long index,
|
||||
unsigned int npages, unsigned long uaddr, int direction);
|
||||
extern void tce_free(struct iommu_table *tbl, long index, unsigned int npages);
|
||||
extern void * __init alloc_tce_table(void);
|
||||
extern void __init free_tce_table(void *tbl);
|
||||
extern int __init build_tce_table(struct pci_dev *dev, void __iomem *bbar);
|
||||
|
||||
#endif /* _ASM_X86_TCE_H */
|
||||
@ -146,7 +146,6 @@ ifeq ($(CONFIG_X86_64),y)
|
||||
obj-$(CONFIG_AUDIT) += audit_64.o
|
||||
|
||||
obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o
|
||||
obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o
|
||||
|
||||
obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o
|
||||
obj-y += vsmp_64.o
|
||||
|
||||
@ -2337,7 +2337,7 @@ static int cpuid_to_apicid[] = {
|
||||
#ifdef CONFIG_SMP
|
||||
/**
|
||||
* apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
|
||||
* @id: APIC ID to check
|
||||
* @apicid: APIC ID to check
|
||||
*/
|
||||
bool apic_id_is_primary_thread(unsigned int apicid)
|
||||
{
|
||||
|
||||
@ -1725,19 +1725,20 @@ static bool io_apic_level_ack_pending(struct mp_chip_data *data)
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool ioapic_irqd_mask(struct irq_data *data)
|
||||
static inline bool ioapic_prepare_move(struct irq_data *data)
|
||||
{
|
||||
/* If we are moving the irq we need to mask it */
|
||||
/* If we are moving the IRQ we need to mask it */
|
||||
if (unlikely(irqd_is_setaffinity_pending(data))) {
|
||||
mask_ioapic_irq(data);
|
||||
if (!irqd_irq_masked(data))
|
||||
mask_ioapic_irq(data);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
|
||||
static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
|
||||
{
|
||||
if (unlikely(masked)) {
|
||||
if (unlikely(moveit)) {
|
||||
/* Only migrate the irq if the ack has been received.
|
||||
*
|
||||
* On rare occasions the broadcast level triggered ack gets
|
||||
@ -1766,15 +1767,17 @@ static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
|
||||
*/
|
||||
if (!io_apic_level_ack_pending(data->chip_data))
|
||||
irq_move_masked_irq(data);
|
||||
unmask_ioapic_irq(data);
|
||||
/* If the IRQ is masked in the core, leave it: */
|
||||
if (!irqd_irq_masked(data))
|
||||
unmask_ioapic_irq(data);
|
||||
}
|
||||
}
|
||||
#else
|
||||
static inline bool ioapic_irqd_mask(struct irq_data *data)
|
||||
static inline bool ioapic_prepare_move(struct irq_data *data)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
|
||||
static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
@ -1783,11 +1786,11 @@ static void ioapic_ack_level(struct irq_data *irq_data)
|
||||
{
|
||||
struct irq_cfg *cfg = irqd_cfg(irq_data);
|
||||
unsigned long v;
|
||||
bool masked;
|
||||
bool moveit;
|
||||
int i;
|
||||
|
||||
irq_complete_move(cfg);
|
||||
masked = ioapic_irqd_mask(irq_data);
|
||||
moveit = ioapic_prepare_move(irq_data);
|
||||
|
||||
/*
|
||||
* It appears there is an erratum which affects at least version 0x11
|
||||
@ -1842,7 +1845,7 @@ static void ioapic_ack_level(struct irq_data *irq_data)
|
||||
eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
|
||||
}
|
||||
|
||||
ioapic_irqd_unmask(irq_data, masked);
|
||||
ioapic_finish_move(irq_data, moveit);
|
||||
}
|
||||
|
||||
static void ioapic_ir_ack_level(struct irq_data *irq_data)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -12,7 +12,6 @@
|
||||
#include <asm/dma.h>
|
||||
#include <asm/iommu.h>
|
||||
#include <asm/gart.h>
|
||||
#include <asm/calgary.h>
|
||||
#include <asm/x86_init.h>
|
||||
#include <asm/iommu_table.h>
|
||||
|
||||
@ -112,11 +111,6 @@ static __init int iommu_setup(char *p)
|
||||
|
||||
gart_parse_options(p);
|
||||
|
||||
#ifdef CONFIG_CALGARY_IOMMU
|
||||
if (!strncmp(p, "calgary", 7))
|
||||
use_calgary = 1;
|
||||
#endif /* CONFIG_CALGARY_IOMMU */
|
||||
|
||||
p += strcspn(p, ",");
|
||||
if (*p == ',')
|
||||
++p;
|
||||
|
||||
@ -459,7 +459,7 @@ static void __init memblock_x86_reserve_range_setup_data(void)
|
||||
* due to mapping restrictions.
|
||||
*
|
||||
* On 64bit, kdump kernel need be restricted to be under 64TB, which is
|
||||
* the upper limit of system RAM in 4-level paing mode. Since the kdump
|
||||
* the upper limit of system RAM in 4-level paging mode. Since the kdump
|
||||
* jumping could be from 5-level to 4-level, the jumping will fail if
|
||||
* kernel is put above 64TB, and there's no way to detect the paging mode
|
||||
* of the kernel which will be loaded for dumping during the 1st kernel
|
||||
@ -743,8 +743,8 @@ static void __init trim_bios_range(void)
|
||||
e820__range_update(0, PAGE_SIZE, E820_TYPE_RAM, E820_TYPE_RESERVED);
|
||||
|
||||
/*
|
||||
* special case: Some BIOSen report the PC BIOS
|
||||
* area (640->1Mb) as ram even though it is not.
|
||||
* special case: Some BIOSes report the PC BIOS
|
||||
* area (640Kb -> 1Mb) as RAM even though it is not.
|
||||
* take them out.
|
||||
*/
|
||||
e820__range_remove(BIOS_BEGIN, BIOS_END - BIOS_BEGIN, E820_TYPE_RAM, 1);
|
||||
|
||||
@ -1,177 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* This file manages the translation entries for the IBM Calgary IOMMU.
|
||||
*
|
||||
* Derived from arch/powerpc/platforms/pseries/iommu.c
|
||||
*
|
||||
* Copyright (C) IBM Corporation, 2006
|
||||
*
|
||||
* Author: Jon Mason <jdmason@us.ibm.com>
|
||||
* Author: Muli Ben-Yehuda <muli@il.ibm.com>
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <asm/tce.h>
|
||||
#include <asm/calgary.h>
|
||||
#include <asm/proto.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
/* flush a tce at 'tceaddr' to main memory */
|
||||
static inline void flush_tce(void* tceaddr)
|
||||
{
|
||||
/* a single tce can't cross a cache line */
|
||||
if (boot_cpu_has(X86_FEATURE_CLFLUSH))
|
||||
clflush(tceaddr);
|
||||
else
|
||||
wbinvd();
|
||||
}
|
||||
|
||||
void tce_build(struct iommu_table *tbl, unsigned long index,
|
||||
unsigned int npages, unsigned long uaddr, int direction)
|
||||
{
|
||||
u64* tp;
|
||||
u64 t;
|
||||
u64 rpn;
|
||||
|
||||
t = (1 << TCE_READ_SHIFT);
|
||||
if (direction != DMA_TO_DEVICE)
|
||||
t |= (1 << TCE_WRITE_SHIFT);
|
||||
|
||||
tp = ((u64*)tbl->it_base) + index;
|
||||
|
||||
while (npages--) {
|
||||
rpn = (virt_to_bus((void*)uaddr)) >> PAGE_SHIFT;
|
||||
t &= ~TCE_RPN_MASK;
|
||||
t |= (rpn << TCE_RPN_SHIFT);
|
||||
|
||||
*tp = cpu_to_be64(t);
|
||||
flush_tce(tp);
|
||||
|
||||
uaddr += PAGE_SIZE;
|
||||
tp++;
|
||||
}
|
||||
}
|
||||
|
||||
void tce_free(struct iommu_table *tbl, long index, unsigned int npages)
|
||||
{
|
||||
u64* tp;
|
||||
|
||||
tp = ((u64*)tbl->it_base) + index;
|
||||
|
||||
while (npages--) {
|
||||
*tp = cpu_to_be64(0);
|
||||
flush_tce(tp);
|
||||
tp++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline unsigned int table_size_to_number_of_entries(unsigned char size)
|
||||
{
|
||||
/*
|
||||
* size is the order of the table, 0-7
|
||||
* smallest table is 8K entries, so shift result by 13 to
|
||||
* multiply by 8K
|
||||
*/
|
||||
return (1 << size) << 13;
|
||||
}
|
||||
|
||||
static int tce_table_setparms(struct pci_dev *dev, struct iommu_table *tbl)
|
||||
{
|
||||
unsigned int bitmapsz;
|
||||
unsigned long bmppages;
|
||||
int ret;
|
||||
|
||||
tbl->it_busno = dev->bus->number;
|
||||
|
||||
/* set the tce table size - measured in entries */
|
||||
tbl->it_size = table_size_to_number_of_entries(specified_table_size);
|
||||
|
||||
/*
|
||||
* number of bytes needed for the bitmap size in number of
|
||||
* entries; we need one bit per entry
|
||||
*/
|
||||
bitmapsz = tbl->it_size / BITS_PER_BYTE;
|
||||
bmppages = __get_free_pages(GFP_KERNEL, get_order(bitmapsz));
|
||||
if (!bmppages) {
|
||||
printk(KERN_ERR "Calgary: cannot allocate bitmap\n");
|
||||
ret = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
|
||||
tbl->it_map = (unsigned long*)bmppages;
|
||||
|
||||
memset(tbl->it_map, 0, bitmapsz);
|
||||
|
||||
tbl->it_hint = 0;
|
||||
|
||||
spin_lock_init(&tbl->it_lock);
|
||||
|
||||
return 0;
|
||||
|
||||
done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int __init build_tce_table(struct pci_dev *dev, void __iomem *bbar)
|
||||
{
|
||||
struct iommu_table *tbl;
|
||||
int ret;
|
||||
|
||||
if (pci_iommu(dev->bus)) {
|
||||
printk(KERN_ERR "Calgary: dev %p has sysdata->iommu %p\n",
|
||||
dev, pci_iommu(dev->bus));
|
||||
BUG();
|
||||
}
|
||||
|
||||
tbl = kzalloc(sizeof(struct iommu_table), GFP_KERNEL);
|
||||
if (!tbl) {
|
||||
printk(KERN_ERR "Calgary: error allocating iommu_table\n");
|
||||
ret = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
|
||||
ret = tce_table_setparms(dev, tbl);
|
||||
if (ret)
|
||||
goto free_tbl;
|
||||
|
||||
tbl->bbar = bbar;
|
||||
|
||||
set_pci_iommu(dev->bus, tbl);
|
||||
|
||||
return 0;
|
||||
|
||||
free_tbl:
|
||||
kfree(tbl);
|
||||
done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void * __init alloc_tce_table(void)
|
||||
{
|
||||
unsigned int size;
|
||||
|
||||
size = table_size_to_number_of_entries(specified_table_size);
|
||||
size *= TCE_ENTRY_SIZE;
|
||||
|
||||
return memblock_alloc_low(size, size);
|
||||
}
|
||||
|
||||
void __init free_tce_table(void *tbl)
|
||||
{
|
||||
unsigned int size;
|
||||
|
||||
if (!tbl)
|
||||
return;
|
||||
|
||||
size = table_size_to_number_of_entries(specified_table_size);
|
||||
size *= TCE_ENTRY_SIZE;
|
||||
|
||||
memblock_free(__pa(tbl), size);
|
||||
}
|
||||
@ -37,11 +37,6 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#if defined(CONFIG_EDAC)
|
||||
#include <linux/edac.h>
|
||||
#endif
|
||||
|
||||
#include <asm/stacktrace.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/debugreg.h>
|
||||
|
||||
@ -842,8 +842,8 @@ static int push_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
|
||||
|
||||
/**
|
||||
* arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
|
||||
* @auprobe: the probepoint information.
|
||||
* @mm: the probed address space.
|
||||
* @arch_uprobe: the probepoint information.
|
||||
* @addr: virtual address at which to install the probepoint
|
||||
* Return 0 on success or a -ve number on error.
|
||||
*/
|
||||
|
||||
@ -699,7 +699,7 @@ static int __init dummy_numa_init(void)
|
||||
* x86_numa_init - Initialize NUMA
|
||||
*
|
||||
* Try each configured NUMA initialization method until one succeeds. The
|
||||
* last fallback is dummy single node config encomapssing whole memory and
|
||||
* last fallback is dummy single node config encompassing whole memory and
|
||||
* never fails.
|
||||
*/
|
||||
void __init x86_numa_init(void)
|
||||
|
||||
@ -69,7 +69,7 @@ BEGIN {
|
||||
|
||||
lprefix1_expr = "\\((66|!F3)\\)"
|
||||
lprefix2_expr = "\\(F3\\)"
|
||||
lprefix3_expr = "\\((F2|!F3|66\\&F2)\\)"
|
||||
lprefix3_expr = "\\((F2|!F3|66&F2)\\)"
|
||||
lprefix_expr = "\\((66|F2|F3)\\)"
|
||||
max_lprefix = 4
|
||||
|
||||
@ -257,7 +257,7 @@ function convert_operands(count,opnd, i,j,imm,mod)
|
||||
return add_flags(imm, mod)
|
||||
}
|
||||
|
||||
/^[0-9a-f]+\:/ {
|
||||
/^[0-9a-f]+:/ {
|
||||
if (NR == 1)
|
||||
next
|
||||
# get index
|
||||
|
||||
@ -69,7 +69,7 @@ BEGIN {
|
||||
|
||||
lprefix1_expr = "\\((66|!F3)\\)"
|
||||
lprefix2_expr = "\\(F3\\)"
|
||||
lprefix3_expr = "\\((F2|!F3|66\\&F2)\\)"
|
||||
lprefix3_expr = "\\((F2|!F3|66&F2)\\)"
|
||||
lprefix_expr = "\\((66|F2|F3)\\)"
|
||||
max_lprefix = 4
|
||||
|
||||
@ -257,7 +257,7 @@ function convert_operands(count,opnd, i,j,imm,mod)
|
||||
return add_flags(imm, mod)
|
||||
}
|
||||
|
||||
/^[0-9a-f]+\:/ {
|
||||
/^[0-9a-f]+:/ {
|
||||
if (NR == 1)
|
||||
next
|
||||
# get index
|
||||
|
||||
Loading…
Reference in New Issue
Block a user