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platform: mellanox: Introduce support for next-generation 800GB/s switch
Introduce support for Nvidia next-generation 800GB/s ethernet switch SN5600. SN5600 is 51.2 Tbps Ethernet switch based on Nvidia Spectrum-4 ASIC. It can provide up to 64x800Gb/s (ETH) full bidirectional bandwidth per port using PAM-4 modulations. The system supports 64 Belly to Belly 2x4 OSFP cages. The switch was designed to fit standard 2U racks. Features: - 64 OSFP ports support 800GbE - 10GbE speed. - Additional 25GbE - 1GbE service port on the front panel. - Air-cooled with 3 + 1 redundant fan units. - 1 + 1 redundant 3000W or 3600W PSUs. - System management board is based on Intel Coffee-lake CPU E-2276 with secure-boot support. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-5-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Vadim Pasternak
Hans de Goede
parent
acc6ea3045
commit
fcf3790b9b
@ -253,6 +253,7 @@
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#define MLXPLAT_CPLD_CH3_ETH_MODULAR 43
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#define MLXPLAT_CPLD_CH4_ETH_MODULAR 51
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#define MLXPLAT_CPLD_CH2_RACK_SWITCH 18
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#define MLXPLAT_CPLD_CH2_NG800 34
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/* Number of LPC attached MUX platform devices */
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#define MLXPLAT_CPLD_LPC_MUX_DEVS 4
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@ -503,6 +504,37 @@ static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = {
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};
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/* Platform channels for ng800 system family */
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static const int mlxplat_ng800_channels[] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
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18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32
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};
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/* Platform ng800 mux data */
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static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = {
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{
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.parent = 1,
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.base_nr = MLXPLAT_CPLD_CH1,
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.write_only = 1,
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.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
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.reg_size = 1,
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.idle_in_use = 1,
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.values = mlxplat_ng800_channels,
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.n_values = ARRAY_SIZE(mlxplat_ng800_channels),
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},
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{
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.parent = 1,
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.base_nr = MLXPLAT_CPLD_CH2_NG800,
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.write_only = 1,
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.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
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.reg_size = 1,
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.idle_in_use = 1,
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.values = mlxplat_msn21xx_channels,
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.n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
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},
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};
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/* Platform hotplug devices */
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static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
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{
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@ -522,6 +554,15 @@ static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {
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},
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};
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static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = {
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{
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I2C_BOARD_INFO("dps460", 0x59),
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},
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{
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I2C_BOARD_INFO("dps460", 0x5a),
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},
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};
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static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
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{
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I2C_BOARD_INFO("24c32", 0x50),
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@ -601,6 +642,23 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = {
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},
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = {
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{
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.label = "pwr1",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(0),
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.hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0],
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.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
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},
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{
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.label = "pwr2",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(1),
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.hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1],
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.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
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},
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
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{
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.label = "fan1",
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@ -1224,6 +1282,47 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
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}
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};
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static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = {
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{
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.data = mlxplat_mlxcpld_default_ng_psu_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = MLXPLAT_CPLD_PSU_EXT_MASK,
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.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
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.inversed = 1,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_pwr_ng800_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = MLXPLAT_CPLD_PWR_EXT_MASK,
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.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data),
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.inversed = 0,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_ng_fan_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
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.mask = MLXPLAT_CPLD_FAN_NG_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
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.inversed = 1,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_asic_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
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.mask = MLXPLAT_CPLD_ASIC_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
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.inversed = 0,
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.health = true,
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},
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};
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static
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struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
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.items = mlxplat_mlxcpld_ext_items,
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@ -1234,6 +1333,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
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.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
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};
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static
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struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = {
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.items = mlxplat_mlxcpld_ng800_items,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items),
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.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
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.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
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.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
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.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
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{
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.label = "pwr1",
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@ -3093,6 +3202,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.mask = GENMASK(7, 0) & ~BIT(7),
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.mode = 0644,
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},
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{
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.label = "clk_brd_prog_en",
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.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(1),
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.mode = 0644,
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.secured = 1,
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},
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{
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.label = "erot1_recovery",
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.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
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@ -3221,6 +3337,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.mask = GENMASK(7, 0) & ~BIT(6),
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.mode = 0444,
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},
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{
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.label = "reset_ac_ok_fail",
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.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(7),
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.mode = 0444,
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},
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{
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.label = "psu1_on",
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.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
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@ -3302,6 +3424,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.bit = 5,
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.mode = 0444,
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},
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{
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.label = "pwr_converter_prog_en",
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.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(0),
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.mode = 0644,
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.secured = 1,
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},
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{
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.label = "vpd_wp",
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.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
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@ -3326,6 +3455,30 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.mask = GENMASK(7, 0) & ~BIT(1),
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.mode = 0444,
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},
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{
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.label = "clk_brd1_boot_fail",
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.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(4),
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.mode = 0444,
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},
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{
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.label = "clk_brd2_boot_fail",
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.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(5),
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.mode = 0444,
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},
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{
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.label = "clk_brd_fail",
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.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(6),
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.mode = 0444,
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},
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{
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.label = "asic_pg_fail",
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.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(7),
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.mode = 0444,
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},
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{
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.label = "spi_chnl_select",
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.reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT,
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@ -5211,6 +5364,27 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm
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return 1;
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}
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static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi)
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{
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int i;
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mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
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mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data);
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mlxplat_mux_data = mlxplat_ng800_mux_data;
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mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data;
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mlxplat_hotplug->deferred_nr =
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mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
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mlxplat_led = &mlxplat_default_ng_led_data;
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mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
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mlxplat_fan = &mlxplat_default_fan_data;
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for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
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mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
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mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
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mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
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return 1;
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}
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static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
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{
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.callback = mlxplat_dmi_default_wc_matched,
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@ -5287,6 +5461,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
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DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"),
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},
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},
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{
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.callback = mlxplat_dmi_ng800_matched,
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.matches = {
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DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"),
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},
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},
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{
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.callback = mlxplat_dmi_chassis_blade_matched,
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.matches = {
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