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drm/i915/gtt: Mark tlbs dirty on clear
Now when clearing ptes can modify upper level pdp's, we need to mark them dirty so that they will be flushed correctly. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1478006856-8313-1-git-send-email-mika.kuoppala@intel.com
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@ -707,6 +707,16 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
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return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
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}
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/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
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* the page table structures, we mark them dirty so that
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* context switching/execlist queuing code takes extra steps
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* to ensure that tlbs are flushed.
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*/
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static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
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{
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ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
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}
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/* Removes entries from a single page table, releasing it if it's empty.
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* Caller can use the return value to update higher-level entries.
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*/
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@ -809,6 +819,8 @@ static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
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}
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}
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mark_tlbs_dirty(ppgtt);
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if (USES_FULL_48BIT_PPGTT(vm->dev) &&
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bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(vm->dev))) {
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free_pdp(vm->dev, pdp);
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@ -1283,16 +1295,6 @@ err_out:
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return -ENOMEM;
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}
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/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
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* the page table structures, we mark them dirty so that
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* context switching/execlist queuing code takes extra steps
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* to ensure that tlbs are flushed.
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*/
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static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
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{
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ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
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}
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static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
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struct i915_page_directory_pointer *pdp,
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uint64_t start,
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