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drm/i915/dsi: let HW maintain CLK_POST
This change is to adjust TCLK-POST timing so DSI signaling can meet CTS specification. For clock lane, the TCLK-POST timing may be changed from 133.44 ns to 178.72 ns, which is greater than (60 ns+52*UI) and is conformed to the CTS standard. The computed UI is around 1.47 ns. v2: remove the change of HS-TRAIL. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: William Tseng <william.tseng@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230914095137.4132029-1-william.tseng@intel.com
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@ -1822,7 +1822,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
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u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
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u32 ths_prepare_ns, tclk_trail_ns;
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u32 hs_zero_cnt;
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u32 tclk_pre_cnt, tclk_post_cnt;
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u32 tclk_pre_cnt;
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tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
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@ -1869,15 +1869,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
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tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
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}
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/* tclk post count in escape clocks */
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tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
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if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
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drm_dbg_kms(&dev_priv->drm,
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"tclk_post_cnt out of range (%d)\n",
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tclk_post_cnt);
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tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
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}
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/* hs zero cnt in escape clocks */
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hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
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ths_prepare_ns, tlpx_ns);
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@ -1903,8 +1894,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
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CLK_ZERO(clk_zero_cnt) |
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CLK_PRE_OVERRIDE |
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CLK_PRE(tclk_pre_cnt) |
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CLK_POST_OVERRIDE |
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CLK_POST(tclk_post_cnt) |
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CLK_TRAIL_OVERRIDE |
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CLK_TRAIL(trail_cnt));
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