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usb: dwc3: core: Workaround for CSR read timeout

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This is a workaround for STAR 4846132, which only affects
DWC_usb31 version2.00a operating in host mode.

There is a problem in DWC_usb31 version 2.00a operating
in host mode that would cause a CSR read timeout When CSR
read coincides with RAM Clock Gating Entry. By disable
Clock Gating, sacrificing power consumption for normal
operation.

Cc: stable <stable@kernel.org> # 5.10.x: 1e43c86d: usb: dwc3: core: Add DWC31 version 2.00a controller
Signed-off-by: Jos Wang <joswang@lenovo.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20240619114529.3441-1-joswang1221@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jos Wang 2024-06-19 19:45:29 +08:00 committed by Greg Kroah-Hartman
parent c50814a288
commit fc1d1a712b
1 changed files with 19 additions and 1 deletions
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20
drivers/usb/dwc3/core.c
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@ -957,12 +957,16 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc)
static void dwc3_core_setup_global_control(struct dwc3 *dwc) static void dwc3_core_setup_global_control(struct dwc3 *dwc)
{ {
unsigned int power_opt;
unsigned int hw_mode;
u32 reg; u32 reg;
reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK; reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { switch (power_opt) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK: case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
/** /**
* WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
@ -995,6 +999,20 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
break; break;
} }
/*
* This is a workaround for STAR#4846132, which only affects
* DWC_usb31 version2.00a operating in host mode.
*
* There is a problem in DWC_usb31 version 2.00a operating
* in host mode that would cause a CSR read timeout When CSR
* read coincides with RAM Clock Gating Entry. By disable
* Clock Gating, sacrificing power consumption for normal
* operation.
*/
if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
reg |= DWC3_GCTL_DSBLCLKGTNG;
/* check if current dwc3 is on simulation board */ /* check if current dwc3 is on simulation board */
if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
dev_info(dwc->dev, "Running with FPGA optimizations\n"); dev_info(dwc->dev, "Running with FPGA optimizations\n");