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spi: pxa2xx: Add support for Intel Cannonlake
Intel Cannonlake LPSS SPI has up to four chip selects per port like in Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type LPSS_CNL_SSP and configuration that enable runtime chip select detection and use the same FIFO thresholds than in Sunrisepoint. Patch adds support for both Cannonlake SoC and PCH. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -151,6 +151,18 @@ static const struct lpss_config lpss_platforms[] = {
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.cs_sel_shift = 8,
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.cs_sel_mask = 3 << 8,
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},
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{ /* LPSS_CNL_SSP */
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.offset = 0x200,
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.reg_general = -1,
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.reg_ssp = 0x20,
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.reg_cs_ctrl = 0x24,
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.reg_capabilities = 0xfc,
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.rx_threshold = 1,
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.tx_threshold_lo = 32,
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.tx_threshold_hi = 56,
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.cs_sel_shift = 8,
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.cs_sel_mask = 3 << 8,
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},
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};
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static inline const struct lpss_config
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@ -167,6 +179,7 @@ static bool is_lpss_ssp(const struct driver_data *drv_data)
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case LPSS_BSW_SSP:
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case LPSS_SPT_SSP:
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case LPSS_BXT_SSP:
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case LPSS_CNL_SSP:
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return true;
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default:
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return false;
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@ -1275,6 +1288,7 @@ static int setup(struct spi_device *spi)
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case LPSS_BSW_SSP:
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case LPSS_SPT_SSP:
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case LPSS_BXT_SSP:
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case LPSS_CNL_SSP:
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config = lpss_get_config(drv_data);
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tx_thres = config->tx_threshold_lo;
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tx_hi_thres = config->tx_threshold_hi;
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@ -1470,6 +1484,14 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
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{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
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{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
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{ PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
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/* CNL-LP */
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{ PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
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/* CNL-H */
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{ PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
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{ PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
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{ },
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};
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@ -196,6 +196,7 @@ enum pxa_ssp_type {
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LPSS_BSW_SSP,
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LPSS_SPT_SSP,
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LPSS_BXT_SSP,
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LPSS_CNL_SSP,
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};
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struct ssp_device {
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