mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-26 13:44:15 +08:00
ionic: Add hardware init and device commands
The ionic device has a small set of PCI registers, including a device control and data space, and a large set of message commands. Also adds new DEVLINK_INFO_VERSION_GENERIC tags for ASIC_ID, ASIC_REV, and FW. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shannon Nelson
David S. Miller
parent
df69ba4321
commit
fbfb803153
@ -3,4 +3,5 @@
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obj-$(CONFIG_IONIC) := ionic.o
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ionic-y := ionic_main.o ionic_bus_pci.o ionic_devlink.o
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ionic-y := ionic_main.o ionic_bus_pci.o ionic_devlink.o ionic_dev.o \
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ionic_debugfs.o
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@ -4,6 +4,8 @@
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#ifndef _IONIC_H_
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#define _IONIC_H_
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#include "ionic_if.h"
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#include "ionic_dev.h"
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#include "ionic_devlink.h"
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#define IONIC_DRV_NAME "ionic"
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@ -19,9 +21,25 @@
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#define IONIC_SUBDEV_ID_NAPLES_100_4 0x4001
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#define IONIC_SUBDEV_ID_NAPLES_100_8 0x4002
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#define DEVCMD_TIMEOUT 10
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struct ionic {
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struct pci_dev *pdev;
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struct device *dev;
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struct ionic_dev idev;
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struct mutex dev_cmd_lock; /* lock for dev_cmd operations */
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struct dentry *dentry;
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struct ionic_dev_bar bars[IONIC_BARS_MAX];
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unsigned int num_bars;
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struct ionic_identity ident;
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};
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int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait);
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int ionic_set_dma_mask(struct ionic *ionic);
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int ionic_setup(struct ionic *ionic);
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int ionic_identify(struct ionic *ionic);
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int ionic_init(struct ionic *ionic);
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int ionic_reset(struct ionic *ionic);
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#endif /* _IONIC_H_ */
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@ -4,6 +4,7 @@
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#ifndef _IONIC_BUS_H_
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#define _IONIC_BUS_H_
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const char *ionic_bus_info(struct ionic *ionic);
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int ionic_bus_register_driver(void);
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void ionic_bus_unregister_driver(void);
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@ -8,6 +8,7 @@
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#include "ionic.h"
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#include "ionic_bus.h"
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#include "ionic_debugfs.h"
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/* Supported devices */
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static const struct pci_device_id ionic_id_table[] = {
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@ -17,10 +18,68 @@ static const struct pci_device_id ionic_id_table[] = {
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};
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MODULE_DEVICE_TABLE(pci, ionic_id_table);
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const char *ionic_bus_info(struct ionic *ionic)
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{
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return pci_name(ionic->pdev);
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}
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static int ionic_map_bars(struct ionic *ionic)
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{
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struct pci_dev *pdev = ionic->pdev;
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struct device *dev = ionic->dev;
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struct ionic_dev_bar *bars;
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unsigned int i, j;
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bars = ionic->bars;
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ionic->num_bars = 0;
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for (i = 0, j = 0; i < IONIC_BARS_MAX; i++) {
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if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
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continue;
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bars[j].len = pci_resource_len(pdev, i);
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/* only map the whole bar 0 */
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if (j > 0) {
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bars[j].vaddr = NULL;
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} else {
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bars[j].vaddr = pci_iomap(pdev, i, bars[j].len);
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if (!bars[j].vaddr) {
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dev_err(dev,
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"Cannot memory-map BAR %d, aborting\n",
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i);
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return -ENODEV;
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}
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}
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bars[j].bus_addr = pci_resource_start(pdev, i);
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bars[j].res_index = i;
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ionic->num_bars++;
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j++;
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}
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return 0;
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}
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static void ionic_unmap_bars(struct ionic *ionic)
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{
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struct ionic_dev_bar *bars = ionic->bars;
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unsigned int i;
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for (i = 0; i < IONIC_BARS_MAX; i++) {
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if (bars[i].vaddr) {
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iounmap(bars[i].vaddr);
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bars[i].bus_addr = 0;
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bars[i].vaddr = NULL;
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bars[i].len = 0;
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}
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}
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}
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static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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struct ionic *ionic;
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int err;
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ionic = ionic_devlink_alloc(dev);
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if (!ionic)
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@ -29,14 +88,96 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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ionic->pdev = pdev;
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ionic->dev = dev;
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pci_set_drvdata(pdev, ionic);
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mutex_init(&ionic->dev_cmd_lock);
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/* Query system for DMA addressing limitation for the device. */
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err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(IONIC_ADDR_LEN));
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if (err) {
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dev_err(dev, "Unable to obtain 64-bit DMA for consistent allocations, aborting. err=%d\n",
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err);
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goto err_out_clear_drvdata;
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}
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ionic_debugfs_add_dev(ionic);
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/* Setup PCI device */
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err = pci_enable_device_mem(pdev);
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if (err) {
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dev_err(dev, "Cannot enable PCI device: %d, aborting\n", err);
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goto err_out_debugfs_del_dev;
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}
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err = pci_request_regions(pdev, IONIC_DRV_NAME);
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if (err) {
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dev_err(dev, "Cannot request PCI regions: %d, aborting\n", err);
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goto err_out_pci_disable_device;
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}
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pci_set_master(pdev);
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err = ionic_map_bars(ionic);
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if (err)
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goto err_out_pci_clear_master;
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/* Configure the device */
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err = ionic_setup(ionic);
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if (err) {
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dev_err(dev, "Cannot setup device: %d, aborting\n", err);
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goto err_out_unmap_bars;
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}
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err = ionic_identify(ionic);
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if (err) {
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dev_err(dev, "Cannot identify device: %d, aborting\n", err);
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goto err_out_teardown;
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}
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err = ionic_init(ionic);
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if (err) {
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dev_err(dev, "Cannot init device: %d, aborting\n", err);
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goto err_out_teardown;
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}
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err = ionic_devlink_register(ionic);
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if (err)
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dev_err(dev, "Cannot register devlink: %d\n", err);
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return 0;
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err_out_teardown:
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ionic_dev_teardown(ionic);
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err_out_unmap_bars:
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ionic_unmap_bars(ionic);
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pci_release_regions(pdev);
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err_out_pci_clear_master:
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pci_clear_master(pdev);
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err_out_pci_disable_device:
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pci_disable_device(pdev);
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err_out_debugfs_del_dev:
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ionic_debugfs_del_dev(ionic);
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err_out_clear_drvdata:
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mutex_destroy(&ionic->dev_cmd_lock);
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ionic_devlink_free(ionic);
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return err;
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}
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static void ionic_remove(struct pci_dev *pdev)
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{
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struct ionic *ionic = pci_get_drvdata(pdev);
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if (!ionic)
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return;
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ionic_devlink_unregister(ionic);
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ionic_reset(ionic);
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ionic_dev_teardown(ionic);
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ionic_unmap_bars(ionic);
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pci_release_regions(pdev);
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pci_clear_master(pdev);
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pci_disable_device(pdev);
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ionic_debugfs_del_dev(ionic);
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mutex_destroy(&ionic->dev_cmd_lock);
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ionic_devlink_free(ionic);
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}
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61
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
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61
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
Normal file
@ -0,0 +1,61 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
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#include <linux/netdevice.h>
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#include "ionic.h"
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#include "ionic_bus.h"
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#include "ionic_debugfs.h"
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *ionic_dir;
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void ionic_debugfs_create(void)
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{
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ionic_dir = debugfs_create_dir(IONIC_DRV_NAME, NULL);
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}
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void ionic_debugfs_destroy(void)
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{
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debugfs_remove_recursive(ionic_dir);
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}
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void ionic_debugfs_add_dev(struct ionic *ionic)
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{
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ionic->dentry = debugfs_create_dir(ionic_bus_info(ionic), ionic_dir);
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}
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void ionic_debugfs_del_dev(struct ionic *ionic)
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{
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debugfs_remove_recursive(ionic->dentry);
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ionic->dentry = NULL;
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}
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static int identity_show(struct seq_file *seq, void *v)
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{
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struct ionic *ionic = seq->private;
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struct ionic_identity *ident;
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ident = &ionic->ident;
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seq_printf(seq, "nlifs: %d\n", ident->dev.nlifs);
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seq_printf(seq, "nintrs: %d\n", ident->dev.nintrs);
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seq_printf(seq, "ndbpgs_per_lif: %d\n", ident->dev.ndbpgs_per_lif);
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seq_printf(seq, "intr_coal_mult: %d\n", ident->dev.intr_coal_mult);
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seq_printf(seq, "intr_coal_div: %d\n", ident->dev.intr_coal_div);
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seq_printf(seq, "max_ucast_filters: %d\n", ident->lif.eth.max_ucast_filters);
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seq_printf(seq, "max_mcast_filters: %d\n", ident->lif.eth.max_mcast_filters);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(identity);
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void ionic_debugfs_add_ident(struct ionic *ionic)
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{
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debugfs_create_file("identity", 0400, ionic->dentry,
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ionic, &identity_fops) ? 0 : -EOPNOTSUPP;
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}
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#endif
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24
drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
Normal file
24
drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
Normal file
@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
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#ifndef _IONIC_DEBUGFS_H_
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#define _IONIC_DEBUGFS_H_
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#include <linux/debugfs.h>
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#ifdef CONFIG_DEBUG_FS
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void ionic_debugfs_create(void);
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void ionic_debugfs_destroy(void);
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void ionic_debugfs_add_dev(struct ionic *ionic);
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void ionic_debugfs_del_dev(struct ionic *ionic);
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void ionic_debugfs_add_ident(struct ionic *ionic);
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#else
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static inline void ionic_debugfs_create(void) { }
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static inline void ionic_debugfs_destroy(void) { }
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static inline void ionic_debugfs_add_dev(struct ionic *ionic) { }
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static inline void ionic_debugfs_del_dev(struct ionic *ionic) { }
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static inline void ionic_debugfs_add_ident(struct ionic *ionic) { }
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#endif
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#endif /* _IONIC_DEBUGFS_H_ */
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136
drivers/net/ethernet/pensando/ionic/ionic_dev.c
Normal file
136
drivers/net/ethernet/pensando/ionic/ionic_dev.c
Normal file
@ -0,0 +1,136 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/etherdevice.h>
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#include "ionic.h"
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#include "ionic_dev.h"
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void ionic_init_devinfo(struct ionic *ionic)
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{
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struct ionic_dev *idev = &ionic->idev;
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idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
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idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
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memcpy_fromio(idev->dev_info.fw_version,
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idev->dev_info_regs->fw_version,
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IONIC_DEVINFO_FWVERS_BUFLEN);
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memcpy_fromio(idev->dev_info.serial_num,
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idev->dev_info_regs->serial_num,
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IONIC_DEVINFO_SERIAL_BUFLEN);
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idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0;
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idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0;
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dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version);
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}
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int ionic_dev_setup(struct ionic *ionic)
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{
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struct ionic_dev_bar *bar = ionic->bars;
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unsigned int num_bars = ionic->num_bars;
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struct ionic_dev *idev = &ionic->idev;
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struct device *dev = ionic->dev;
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u32 sig;
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/* BAR0: dev_cmd and interrupts */
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if (num_bars < 1) {
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dev_err(dev, "No bars found, aborting\n");
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return -EFAULT;
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}
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if (bar->len < IONIC_BAR0_SIZE) {
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dev_err(dev, "Resource bar size %lu too small, aborting\n",
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bar->len);
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return -EFAULT;
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}
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idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET;
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idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET;
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idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET;
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idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET;
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sig = ioread32(&idev->dev_info_regs->signature);
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if (sig != IONIC_DEV_INFO_SIGNATURE) {
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dev_err(dev, "Incompatible firmware signature %x", sig);
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return -EFAULT;
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}
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ionic_init_devinfo(ionic);
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/* BAR1: doorbells */
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bar++;
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if (num_bars < 2) {
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dev_err(dev, "Doorbell bar missing, aborting\n");
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return -EFAULT;
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}
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idev->db_pages = bar->vaddr;
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idev->phy_db_pages = bar->bus_addr;
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return 0;
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}
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void ionic_dev_teardown(struct ionic *ionic)
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{
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/* place holder */
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}
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/* Devcmd Interface */
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u8 ionic_dev_cmd_status(struct ionic_dev *idev)
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{
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return ioread8(&idev->dev_cmd_regs->comp.comp.status);
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}
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bool ionic_dev_cmd_done(struct ionic_dev *idev)
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{
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return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE;
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}
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void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp)
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{
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memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
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}
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void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
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{
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memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
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iowrite32(0, &idev->dev_cmd_regs->done);
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iowrite32(1, &idev->dev_cmd_regs->doorbell);
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}
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/* Device commands */
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void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
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{
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union ionic_dev_cmd cmd = {
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.identify.opcode = IONIC_CMD_IDENTIFY,
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.identify.ver = ver,
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};
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ionic_dev_cmd_go(idev, &cmd);
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}
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void ionic_dev_cmd_init(struct ionic_dev *idev)
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{
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union ionic_dev_cmd cmd = {
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.init.opcode = IONIC_CMD_INIT,
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.init.type = 0,
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};
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ionic_dev_cmd_go(idev, &cmd);
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}
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void ionic_dev_cmd_reset(struct ionic_dev *idev)
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{
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union ionic_dev_cmd cmd = {
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.reset.opcode = IONIC_CMD_RESET,
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};
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ionic_dev_cmd_go(idev, &cmd);
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}
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138
drivers/net/ethernet/pensando/ionic/ionic_dev.h
Normal file
138
drivers/net/ethernet/pensando/ionic/ionic_dev.h
Normal file
@ -0,0 +1,138 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
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#ifndef _IONIC_DEV_H_
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#define _IONIC_DEV_H_
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#include <linux/mutex.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include "ionic_if.h"
|
||||
#include "ionic_regs.h"
|
||||
|
||||
struct ionic_dev_bar {
|
||||
void __iomem *vaddr;
|
||||
phys_addr_t bus_addr;
|
||||
unsigned long len;
|
||||
int res_index;
|
||||
};
|
||||
|
||||
/* Registers */
|
||||
static_assert(sizeof(struct ionic_intr) == 32);
|
||||
|
||||
static_assert(sizeof(struct ionic_doorbell) == 8);
|
||||
static_assert(sizeof(struct ionic_intr_status) == 8);
|
||||
static_assert(sizeof(union ionic_dev_regs) == 4096);
|
||||
static_assert(sizeof(union ionic_dev_info_regs) == 2048);
|
||||
static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
|
||||
static_assert(sizeof(struct ionic_lif_stats) == 1024);
|
||||
|
||||
static_assert(sizeof(struct ionic_admin_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_admin_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_nop_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_nop_comp) == 16);
|
||||
|
||||
/* Device commands */
|
||||
static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_dev_init_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
|
||||
|
||||
/* Port commands */
|
||||
static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_port_identify_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_port_init_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_port_init_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_port_reset_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_port_setattr_comp) == 16);
|
||||
|
||||
/* LIF commands */
|
||||
static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_lif_init_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
|
||||
static_assert(sizeof(ionic_lif_reset_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);
|
||||
|
||||
static_assert(sizeof(struct ionic_q_init_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_q_init_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_q_control_cmd) == 64);
|
||||
static_assert(sizeof(ionic_q_control_comp) == 16);
|
||||
|
||||
static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
|
||||
static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
|
||||
static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
|
||||
static_assert(sizeof(ionic_rx_filter_del_comp) == 16);
|
||||
|
||||
/* RDMA commands */
|
||||
static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
|
||||
static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);
|
||||
|
||||
/* Events */
|
||||
static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
|
||||
static_assert(sizeof(union ionic_notifyq_comp) == 64);
|
||||
static_assert(sizeof(struct ionic_notifyq_event) == 64);
|
||||
static_assert(sizeof(struct ionic_link_change_event) == 64);
|
||||
static_assert(sizeof(struct ionic_reset_event) == 64);
|
||||
static_assert(sizeof(struct ionic_heartbeat_event) == 64);
|
||||
static_assert(sizeof(struct ionic_log_event) == 64);
|
||||
|
||||
/* I/O */
|
||||
static_assert(sizeof(struct ionic_txq_desc) == 16);
|
||||
static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
|
||||
static_assert(sizeof(struct ionic_txq_comp) == 16);
|
||||
|
||||
static_assert(sizeof(struct ionic_rxq_desc) == 16);
|
||||
static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
|
||||
static_assert(sizeof(struct ionic_rxq_comp) == 16);
|
||||
|
||||
struct ionic_devinfo {
|
||||
u8 asic_type;
|
||||
u8 asic_rev;
|
||||
char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
|
||||
char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
|
||||
};
|
||||
|
||||
struct ionic_dev {
|
||||
union ionic_dev_info_regs __iomem *dev_info_regs;
|
||||
union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
|
||||
|
||||
u64 __iomem *db_pages;
|
||||
dma_addr_t phy_db_pages;
|
||||
|
||||
struct ionic_intr __iomem *intr_ctrl;
|
||||
u64 __iomem *intr_status;
|
||||
|
||||
struct ionic_devinfo dev_info;
|
||||
};
|
||||
|
||||
struct ionic;
|
||||
|
||||
void ionic_init_devinfo(struct ionic *ionic);
|
||||
int ionic_dev_setup(struct ionic *ionic);
|
||||
void ionic_dev_teardown(struct ionic *ionic);
|
||||
|
||||
void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
|
||||
u8 ionic_dev_cmd_status(struct ionic_dev *idev);
|
||||
bool ionic_dev_cmd_done(struct ionic_dev *idev);
|
||||
void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp);
|
||||
|
||||
void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
|
||||
void ionic_dev_cmd_init(struct ionic_dev *idev);
|
||||
void ionic_dev_cmd_reset(struct ionic_dev *idev);
|
||||
|
||||
#endif /* _IONIC_DEV_H_ */
|
||||
@ -11,7 +11,39 @@
|
||||
static int ionic_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
|
||||
struct netlink_ext_ack *extack)
|
||||
{
|
||||
return devlink_info_driver_name_put(req, IONIC_DRV_NAME);
|
||||
struct ionic *ionic = devlink_priv(dl);
|
||||
struct ionic_dev *idev = &ionic->idev;
|
||||
char buf[16];
|
||||
int err = 0;
|
||||
|
||||
err = devlink_info_driver_name_put(req, IONIC_DRV_NAME);
|
||||
if (err)
|
||||
goto info_out;
|
||||
|
||||
err = devlink_info_version_running_put(req,
|
||||
DEVLINK_INFO_VERSION_GENERIC_FW,
|
||||
idev->dev_info.fw_version);
|
||||
if (err)
|
||||
goto info_out;
|
||||
|
||||
snprintf(buf, sizeof(buf), "0x%x", idev->dev_info.asic_type);
|
||||
err = devlink_info_version_fixed_put(req,
|
||||
DEVLINK_INFO_VERSION_GENERIC_ASIC_ID,
|
||||
buf);
|
||||
if (err)
|
||||
goto info_out;
|
||||
|
||||
snprintf(buf, sizeof(buf), "0x%x", idev->dev_info.asic_rev);
|
||||
err = devlink_info_version_fixed_put(req,
|
||||
DEVLINK_INFO_VERSION_GENERIC_ASIC_REV,
|
||||
buf);
|
||||
if (err)
|
||||
goto info_out;
|
||||
|
||||
err = devlink_info_serial_number_put(req, idev->dev_info.serial_num);
|
||||
|
||||
info_out:
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct devlink_ops ionic_dl_ops = {
|
||||
@ -33,3 +65,22 @@ void ionic_devlink_free(struct ionic *ionic)
|
||||
|
||||
devlink_free(dl);
|
||||
}
|
||||
|
||||
int ionic_devlink_register(struct ionic *ionic)
|
||||
{
|
||||
struct devlink *dl = priv_to_devlink(ionic);
|
||||
int err;
|
||||
|
||||
err = devlink_register(dl, ionic->dev);
|
||||
if (err)
|
||||
dev_warn(ionic->dev, "devlink_register failed: %d\n", err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
void ionic_devlink_unregister(struct ionic *ionic)
|
||||
{
|
||||
struct devlink *dl = priv_to_devlink(ionic);
|
||||
|
||||
devlink_unregister(dl);
|
||||
}
|
||||
|
||||
@ -8,5 +8,7 @@
|
||||
|
||||
struct ionic *ionic_devlink_alloc(struct device *dev);
|
||||
void ionic_devlink_free(struct ionic *ionic);
|
||||
int ionic_devlink_register(struct ionic *ionic);
|
||||
void ionic_devlink_unregister(struct ionic *ionic);
|
||||
|
||||
#endif /* _IONIC_DEVLINK_H_ */
|
||||
|
||||
2482
drivers/net/ethernet/pensando/ionic/ionic_if.h
Normal file
2482
drivers/net/ethernet/pensando/ionic/ionic_if.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -8,22 +8,313 @@
|
||||
|
||||
#include "ionic.h"
|
||||
#include "ionic_bus.h"
|
||||
#include "ionic_debugfs.h"
|
||||
|
||||
MODULE_DESCRIPTION(IONIC_DRV_DESCRIPTION);
|
||||
MODULE_AUTHOR("Pensando Systems, Inc");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION(IONIC_DRV_VERSION);
|
||||
|
||||
static const char *ionic_error_to_str(enum ionic_status_code code)
|
||||
{
|
||||
switch (code) {
|
||||
case IONIC_RC_SUCCESS:
|
||||
return "IONIC_RC_SUCCESS";
|
||||
case IONIC_RC_EVERSION:
|
||||
return "IONIC_RC_EVERSION";
|
||||
case IONIC_RC_EOPCODE:
|
||||
return "IONIC_RC_EOPCODE";
|
||||
case IONIC_RC_EIO:
|
||||
return "IONIC_RC_EIO";
|
||||
case IONIC_RC_EPERM:
|
||||
return "IONIC_RC_EPERM";
|
||||
case IONIC_RC_EQID:
|
||||
return "IONIC_RC_EQID";
|
||||
case IONIC_RC_EQTYPE:
|
||||
return "IONIC_RC_EQTYPE";
|
||||
case IONIC_RC_ENOENT:
|
||||
return "IONIC_RC_ENOENT";
|
||||
case IONIC_RC_EINTR:
|
||||
return "IONIC_RC_EINTR";
|
||||
case IONIC_RC_EAGAIN:
|
||||
return "IONIC_RC_EAGAIN";
|
||||
case IONIC_RC_ENOMEM:
|
||||
return "IONIC_RC_ENOMEM";
|
||||
case IONIC_RC_EFAULT:
|
||||
return "IONIC_RC_EFAULT";
|
||||
case IONIC_RC_EBUSY:
|
||||
return "IONIC_RC_EBUSY";
|
||||
case IONIC_RC_EEXIST:
|
||||
return "IONIC_RC_EEXIST";
|
||||
case IONIC_RC_EINVAL:
|
||||
return "IONIC_RC_EINVAL";
|
||||
case IONIC_RC_ENOSPC:
|
||||
return "IONIC_RC_ENOSPC";
|
||||
case IONIC_RC_ERANGE:
|
||||
return "IONIC_RC_ERANGE";
|
||||
case IONIC_RC_BAD_ADDR:
|
||||
return "IONIC_RC_BAD_ADDR";
|
||||
case IONIC_RC_DEV_CMD:
|
||||
return "IONIC_RC_DEV_CMD";
|
||||
case IONIC_RC_ERROR:
|
||||
return "IONIC_RC_ERROR";
|
||||
case IONIC_RC_ERDMA:
|
||||
return "IONIC_RC_ERDMA";
|
||||
default:
|
||||
return "IONIC_RC_UNKNOWN";
|
||||
}
|
||||
}
|
||||
|
||||
static int ionic_error_to_errno(enum ionic_status_code code)
|
||||
{
|
||||
switch (code) {
|
||||
case IONIC_RC_SUCCESS:
|
||||
return 0;
|
||||
case IONIC_RC_EVERSION:
|
||||
case IONIC_RC_EQTYPE:
|
||||
case IONIC_RC_EQID:
|
||||
case IONIC_RC_EINVAL:
|
||||
return -EINVAL;
|
||||
case IONIC_RC_EPERM:
|
||||
return -EPERM;
|
||||
case IONIC_RC_ENOENT:
|
||||
return -ENOENT;
|
||||
case IONIC_RC_EAGAIN:
|
||||
return -EAGAIN;
|
||||
case IONIC_RC_ENOMEM:
|
||||
return -ENOMEM;
|
||||
case IONIC_RC_EFAULT:
|
||||
return -EFAULT;
|
||||
case IONIC_RC_EBUSY:
|
||||
return -EBUSY;
|
||||
case IONIC_RC_EEXIST:
|
||||
return -EEXIST;
|
||||
case IONIC_RC_ENOSPC:
|
||||
return -ENOSPC;
|
||||
case IONIC_RC_ERANGE:
|
||||
return -ERANGE;
|
||||
case IONIC_RC_BAD_ADDR:
|
||||
return -EFAULT;
|
||||
case IONIC_RC_EOPCODE:
|
||||
case IONIC_RC_EINTR:
|
||||
case IONIC_RC_DEV_CMD:
|
||||
case IONIC_RC_ERROR:
|
||||
case IONIC_RC_ERDMA:
|
||||
case IONIC_RC_EIO:
|
||||
default:
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
static const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode)
|
||||
{
|
||||
switch (opcode) {
|
||||
case IONIC_CMD_NOP:
|
||||
return "IONIC_CMD_NOP";
|
||||
case IONIC_CMD_INIT:
|
||||
return "IONIC_CMD_INIT";
|
||||
case IONIC_CMD_RESET:
|
||||
return "IONIC_CMD_RESET";
|
||||
case IONIC_CMD_IDENTIFY:
|
||||
return "IONIC_CMD_IDENTIFY";
|
||||
case IONIC_CMD_GETATTR:
|
||||
return "IONIC_CMD_GETATTR";
|
||||
case IONIC_CMD_SETATTR:
|
||||
return "IONIC_CMD_SETATTR";
|
||||
case IONIC_CMD_PORT_IDENTIFY:
|
||||
return "IONIC_CMD_PORT_IDENTIFY";
|
||||
case IONIC_CMD_PORT_INIT:
|
||||
return "IONIC_CMD_PORT_INIT";
|
||||
case IONIC_CMD_PORT_RESET:
|
||||
return "IONIC_CMD_PORT_RESET";
|
||||
case IONIC_CMD_PORT_GETATTR:
|
||||
return "IONIC_CMD_PORT_GETATTR";
|
||||
case IONIC_CMD_PORT_SETATTR:
|
||||
return "IONIC_CMD_PORT_SETATTR";
|
||||
case IONIC_CMD_LIF_INIT:
|
||||
return "IONIC_CMD_LIF_INIT";
|
||||
case IONIC_CMD_LIF_RESET:
|
||||
return "IONIC_CMD_LIF_RESET";
|
||||
case IONIC_CMD_LIF_IDENTIFY:
|
||||
return "IONIC_CMD_LIF_IDENTIFY";
|
||||
case IONIC_CMD_LIF_SETATTR:
|
||||
return "IONIC_CMD_LIF_SETATTR";
|
||||
case IONIC_CMD_LIF_GETATTR:
|
||||
return "IONIC_CMD_LIF_GETATTR";
|
||||
case IONIC_CMD_RX_MODE_SET:
|
||||
return "IONIC_CMD_RX_MODE_SET";
|
||||
case IONIC_CMD_RX_FILTER_ADD:
|
||||
return "IONIC_CMD_RX_FILTER_ADD";
|
||||
case IONIC_CMD_RX_FILTER_DEL:
|
||||
return "IONIC_CMD_RX_FILTER_DEL";
|
||||
case IONIC_CMD_Q_INIT:
|
||||
return "IONIC_CMD_Q_INIT";
|
||||
case IONIC_CMD_Q_CONTROL:
|
||||
return "IONIC_CMD_Q_CONTROL";
|
||||
case IONIC_CMD_RDMA_RESET_LIF:
|
||||
return "IONIC_CMD_RDMA_RESET_LIF";
|
||||
case IONIC_CMD_RDMA_CREATE_EQ:
|
||||
return "IONIC_CMD_RDMA_CREATE_EQ";
|
||||
case IONIC_CMD_RDMA_CREATE_CQ:
|
||||
return "IONIC_CMD_RDMA_CREATE_CQ";
|
||||
case IONIC_CMD_RDMA_CREATE_ADMINQ:
|
||||
return "IONIC_CMD_RDMA_CREATE_ADMINQ";
|
||||
case IONIC_CMD_FW_DOWNLOAD:
|
||||
return "IONIC_CMD_FW_DOWNLOAD";
|
||||
case IONIC_CMD_FW_CONTROL:
|
||||
return "IONIC_CMD_FW_CONTROL";
|
||||
default:
|
||||
return "DEVCMD_UNKNOWN";
|
||||
}
|
||||
}
|
||||
|
||||
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds)
|
||||
{
|
||||
struct ionic_dev *idev = &ionic->idev;
|
||||
unsigned long start_time;
|
||||
unsigned long max_wait;
|
||||
unsigned long duration;
|
||||
int opcode;
|
||||
int done;
|
||||
int err;
|
||||
|
||||
WARN_ON(in_interrupt());
|
||||
|
||||
/* Wait for dev cmd to complete, retrying if we get EAGAIN,
|
||||
* but don't wait any longer than max_seconds.
|
||||
*/
|
||||
max_wait = jiffies + (max_seconds * HZ);
|
||||
try_again:
|
||||
start_time = jiffies;
|
||||
do {
|
||||
done = ionic_dev_cmd_done(idev);
|
||||
if (done)
|
||||
break;
|
||||
msleep(20);
|
||||
} while (!done && time_before(jiffies, max_wait));
|
||||
duration = jiffies - start_time;
|
||||
|
||||
opcode = idev->dev_cmd_regs->cmd.cmd.opcode;
|
||||
dev_dbg(ionic->dev, "DEVCMD %s (%d) done=%d took %ld secs (%ld jiffies)\n",
|
||||
ionic_opcode_to_str(opcode), opcode,
|
||||
done, duration / HZ, duration);
|
||||
|
||||
if (!done && !time_before(jiffies, max_wait)) {
|
||||
dev_warn(ionic->dev, "DEVCMD %s (%d) timeout after %ld secs\n",
|
||||
ionic_opcode_to_str(opcode), opcode, max_seconds);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
err = ionic_dev_cmd_status(&ionic->idev);
|
||||
if (err) {
|
||||
if (err == IONIC_RC_EAGAIN && !time_after(jiffies, max_wait)) {
|
||||
dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) retrying...\n",
|
||||
ionic_opcode_to_str(opcode), opcode,
|
||||
ionic_error_to_str(err), err);
|
||||
|
||||
msleep(1000);
|
||||
iowrite32(0, &idev->dev_cmd_regs->done);
|
||||
iowrite32(1, &idev->dev_cmd_regs->doorbell);
|
||||
goto try_again;
|
||||
}
|
||||
|
||||
dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) failed\n",
|
||||
ionic_opcode_to_str(opcode), opcode,
|
||||
ionic_error_to_str(err), err);
|
||||
|
||||
return ionic_error_to_errno(err);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ionic_setup(struct ionic *ionic)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = ionic_dev_setup(ionic);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ionic_identify(struct ionic *ionic)
|
||||
{
|
||||
struct ionic_identity *ident = &ionic->ident;
|
||||
struct ionic_dev *idev = &ionic->idev;
|
||||
size_t sz;
|
||||
int err;
|
||||
|
||||
memset(ident, 0, sizeof(*ident));
|
||||
|
||||
ident->drv.os_type = cpu_to_le32(IONIC_OS_TYPE_LINUX);
|
||||
strncpy(ident->drv.driver_ver_str, IONIC_DRV_VERSION,
|
||||
sizeof(ident->drv.driver_ver_str) - 1);
|
||||
|
||||
mutex_lock(&ionic->dev_cmd_lock);
|
||||
|
||||
sz = min(sizeof(ident->drv), sizeof(idev->dev_cmd_regs->data));
|
||||
memcpy_toio(&idev->dev_cmd_regs->data, &ident->drv, sz);
|
||||
|
||||
ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1);
|
||||
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
|
||||
if (!err) {
|
||||
sz = min(sizeof(ident->dev), sizeof(idev->dev_cmd_regs->data));
|
||||
memcpy_fromio(&ident->dev, &idev->dev_cmd_regs->data, sz);
|
||||
}
|
||||
|
||||
mutex_unlock(&ionic->dev_cmd_lock);
|
||||
|
||||
if (err)
|
||||
goto err_out_unmap;
|
||||
|
||||
ionic_debugfs_add_ident(ionic);
|
||||
|
||||
return 0;
|
||||
|
||||
err_out_unmap:
|
||||
return err;
|
||||
}
|
||||
|
||||
int ionic_init(struct ionic *ionic)
|
||||
{
|
||||
struct ionic_dev *idev = &ionic->idev;
|
||||
int err;
|
||||
|
||||
mutex_lock(&ionic->dev_cmd_lock);
|
||||
ionic_dev_cmd_init(idev);
|
||||
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
|
||||
mutex_unlock(&ionic->dev_cmd_lock);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int ionic_reset(struct ionic *ionic)
|
||||
{
|
||||
struct ionic_dev *idev = &ionic->idev;
|
||||
int err;
|
||||
|
||||
mutex_lock(&ionic->dev_cmd_lock);
|
||||
ionic_dev_cmd_reset(idev);
|
||||
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
|
||||
mutex_unlock(&ionic->dev_cmd_lock);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __init ionic_init_module(void)
|
||||
{
|
||||
pr_info("%s %s, ver %s\n",
|
||||
IONIC_DRV_NAME, IONIC_DRV_DESCRIPTION, IONIC_DRV_VERSION);
|
||||
ionic_debugfs_create();
|
||||
return ionic_bus_register_driver();
|
||||
}
|
||||
|
||||
static void __exit ionic_cleanup_module(void)
|
||||
{
|
||||
ionic_bus_unregister_driver();
|
||||
ionic_debugfs_destroy();
|
||||
|
||||
pr_info("%s removed\n", IONIC_DRV_NAME);
|
||||
}
|
||||
|
||||
133
drivers/net/ethernet/pensando/ionic/ionic_regs.h
Normal file
133
drivers/net/ethernet/pensando/ionic/ionic_regs.h
Normal file
@ -0,0 +1,133 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */
|
||||
/* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
|
||||
|
||||
#ifndef IONIC_REGS_H
|
||||
#define IONIC_REGS_H
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
/** struct ionic_intr - interrupt control register set.
|
||||
* @coal_init: coalesce timer initial value.
|
||||
* @mask: interrupt mask value.
|
||||
* @credits: interrupt credit count and return.
|
||||
* @mask_assert: interrupt mask value on assert.
|
||||
* @coal: coalesce timer time remaining.
|
||||
*/
|
||||
struct ionic_intr {
|
||||
u32 coal_init;
|
||||
u32 mask;
|
||||
u32 credits;
|
||||
u32 mask_assert;
|
||||
u32 coal;
|
||||
u32 rsvd[3];
|
||||
};
|
||||
|
||||
/** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
|
||||
* @IONIC_INTR_MASK_CLEAR: unmask interrupt.
|
||||
* @IONIC_INTR_MASK_SET: mask interrupt.
|
||||
*/
|
||||
enum ionic_intr_mask_vals {
|
||||
IONIC_INTR_MASK_CLEAR = 0,
|
||||
IONIC_INTR_MASK_SET = 1,
|
||||
};
|
||||
|
||||
/** enum ionic_intr_credits_bits - bitwise composition of credits values.
|
||||
* @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
|
||||
* @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
|
||||
* @IONIC_INTR_CRED_UNMASK: unmask the interrupt.
|
||||
* @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer.
|
||||
* @IONIC_INTR_CRED_REARM: unmask the and reset the timer.
|
||||
*/
|
||||
enum ionic_intr_credits_bits {
|
||||
IONIC_INTR_CRED_COUNT = 0x7fffu,
|
||||
IONIC_INTR_CRED_COUNT_SIGNED = 0xffffu,
|
||||
IONIC_INTR_CRED_UNMASK = 0x10000u,
|
||||
IONIC_INTR_CRED_RESET_COALESCE = 0x20000u,
|
||||
IONIC_INTR_CRED_REARM = (IONIC_INTR_CRED_UNMASK |
|
||||
IONIC_INTR_CRED_RESET_COALESCE),
|
||||
};
|
||||
|
||||
static inline void ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl,
|
||||
int intr_idx, u32 coal)
|
||||
{
|
||||
iowrite32(coal, &intr_ctrl[intr_idx].coal_init);
|
||||
}
|
||||
|
||||
static inline void ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl,
|
||||
int intr_idx, u32 mask)
|
||||
{
|
||||
iowrite32(mask, &intr_ctrl[intr_idx].mask);
|
||||
}
|
||||
|
||||
static inline void ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl,
|
||||
int intr_idx, u32 cred, u32 flags)
|
||||
{
|
||||
if (WARN_ON_ONCE(cred > IONIC_INTR_CRED_COUNT)) {
|
||||
cred = ioread32(&intr_ctrl[intr_idx].credits);
|
||||
cred &= IONIC_INTR_CRED_COUNT_SIGNED;
|
||||
}
|
||||
|
||||
iowrite32(cred | flags, &intr_ctrl[intr_idx].credits);
|
||||
}
|
||||
|
||||
static inline void ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl,
|
||||
int intr_idx)
|
||||
{
|
||||
u32 cred;
|
||||
|
||||
cred = ioread32(&intr_ctrl[intr_idx].credits);
|
||||
cred &= IONIC_INTR_CRED_COUNT_SIGNED;
|
||||
cred |= IONIC_INTR_CRED_RESET_COALESCE;
|
||||
iowrite32(cred, &intr_ctrl[intr_idx].credits);
|
||||
}
|
||||
|
||||
static inline void ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl,
|
||||
int intr_idx, u32 mask)
|
||||
{
|
||||
iowrite32(mask, &intr_ctrl[intr_idx].mask_assert);
|
||||
}
|
||||
|
||||
/** enum ionic_dbell_bits - bitwise composition of dbell values.
|
||||
*
|
||||
* @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits.
|
||||
* @IONIC_DBELL_QID_SHIFT: queue id shift amount in dbell value.
|
||||
* @IONIC_DBELL_QID: macro to build QID component of dbell value.
|
||||
*
|
||||
* @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits.
|
||||
* @IONIC_DBELL_RING_SHIFT: ring shift amount in dbell value.
|
||||
* @IONIC_DBELL_RING: macro to build ring component of dbell value.
|
||||
*
|
||||
* @IONIC_DBELL_RING_0: ring zero dbell component value.
|
||||
* @IONIC_DBELL_RING_1: ring one dbell component value.
|
||||
* @IONIC_DBELL_RING_2: ring two dbell component value.
|
||||
* @IONIC_DBELL_RING_3: ring three dbell component value.
|
||||
*
|
||||
* @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed.
|
||||
*/
|
||||
enum ionic_dbell_bits {
|
||||
IONIC_DBELL_QID_MASK = 0xffffff,
|
||||
IONIC_DBELL_QID_SHIFT = 24,
|
||||
|
||||
#define IONIC_DBELL_QID(n) \
|
||||
(((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT)
|
||||
|
||||
IONIC_DBELL_RING_MASK = 0x7,
|
||||
IONIC_DBELL_RING_SHIFT = 16,
|
||||
|
||||
#define IONIC_DBELL_RING(n) \
|
||||
(((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT)
|
||||
|
||||
IONIC_DBELL_RING_0 = 0,
|
||||
IONIC_DBELL_RING_1 = IONIC_DBELL_RING(1),
|
||||
IONIC_DBELL_RING_2 = IONIC_DBELL_RING(2),
|
||||
IONIC_DBELL_RING_3 = IONIC_DBELL_RING(3),
|
||||
|
||||
IONIC_DBELL_INDEX_MASK = 0xffff,
|
||||
};
|
||||
|
||||
static inline void ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val)
|
||||
{
|
||||
writeq(val, &db_page[qtype]);
|
||||
}
|
||||
|
||||
#endif /* IONIC_REGS_H */
|
||||
Loading…
Reference in New Issue
Block a user