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drm/i915: refactor some crtc code out of intel display. (v2)
There may be more crtc code that can be pulled out, but this is a good start. v2: move plane before this. Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_crtc.h a bit.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/eacbe964f90d189c5940c12af5e09091b37a19c3.1610622609.git.jani.nikula@intel.com
This commit is contained in:
Dave Airlie
Jani Nikula
parent
3170a21f70
commit
fbf756c31c
@ -196,6 +196,7 @@ i915-y += \
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display/intel_color.o \
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display/intel_combo_phy.o \
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display/intel_connector.o \
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display/intel_crtc.o \
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display/intel_csr.o \
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display/intel_cursor.o \
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display/intel_display.o \
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325
drivers/gpu/drm/i915/display/intel_crtc.c
Normal file
325
drivers/gpu/drm/i915/display/intel_crtc.c
Normal file
@ -0,0 +1,325 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_plane.h>
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#include <drm/drm_plane_helper.h>
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#include "intel_atomic.h"
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#include "intel_atomic_plane.h"
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#include "intel_color.h"
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#include "intel_crtc.h"
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#include "intel_cursor.h"
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#include "intel_display_debugfs.h"
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#include "intel_display_types.h"
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#include "intel_pipe_crc.h"
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#include "intel_sprite.h"
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#include "i9xx_plane.h"
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static void assert_vblank_disabled(struct drm_crtc *crtc)
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{
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if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
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drm_crtc_vblank_put(crtc);
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}
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u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
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if (!vblank->max_vblank_count)
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return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
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return crtc->base.funcs->get_vblank_counter(&crtc->base);
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}
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u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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u32 mode_flags = crtc->mode_flags;
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/*
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* From Gen 11, In case of dsi cmd mode, frame counter wouldnt
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* have updated at the beginning of TE, if we want to use
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* the hw counter, then we would find it updated in only
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* the next TE, hence switching to sw counter.
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*/
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if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
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return 0;
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/*
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* On i965gm the hardware frame counter reads
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* zero when the TV encoder is enabled :(
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*/
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if (IS_I965GM(dev_priv) &&
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(crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
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return 0;
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if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
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return 0xffffffff; /* full 32 bit counter */
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else if (INTEL_GEN(dev_priv) >= 3)
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return 0xffffff; /* only 24 bits of frame count */
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else
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return 0; /* Gen2 doesn't have a hardware frame counter */
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}
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void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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assert_vblank_disabled(&crtc->base);
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drm_crtc_set_max_vblank_count(&crtc->base,
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intel_crtc_max_vblank_count(crtc_state));
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drm_crtc_vblank_on(&crtc->base);
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}
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void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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drm_crtc_vblank_off(&crtc->base);
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assert_vblank_disabled(&crtc->base);
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}
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struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
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{
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struct intel_crtc_state *crtc_state;
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crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
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if (crtc_state)
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intel_crtc_state_reset(crtc_state, crtc);
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return crtc_state;
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}
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void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
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struct intel_crtc *crtc)
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{
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memset(crtc_state, 0, sizeof(*crtc_state));
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__drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
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crtc_state->cpu_transcoder = INVALID_TRANSCODER;
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crtc_state->master_transcoder = INVALID_TRANSCODER;
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crtc_state->hsw_workaround_pipe = INVALID_PIPE;
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crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
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crtc_state->scaler_state.scaler_id = -1;
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crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
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}
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static struct intel_crtc *intel_crtc_alloc(void)
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{
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struct intel_crtc_state *crtc_state;
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struct intel_crtc *crtc;
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crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
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if (!crtc)
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return ERR_PTR(-ENOMEM);
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crtc_state = intel_crtc_state_alloc(crtc);
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if (!crtc_state) {
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kfree(crtc);
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return ERR_PTR(-ENOMEM);
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}
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crtc->base.state = &crtc_state->uapi;
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crtc->config = crtc_state;
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return crtc;
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}
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static void intel_crtc_free(struct intel_crtc *crtc)
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{
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intel_crtc_destroy_state(&crtc->base, crtc->base.state);
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kfree(crtc);
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}
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static void intel_crtc_destroy(struct drm_crtc *crtc)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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drm_crtc_cleanup(crtc);
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kfree(intel_crtc);
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}
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static int intel_crtc_late_register(struct drm_crtc *crtc)
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{
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intel_crtc_debugfs_add(crtc);
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return 0;
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}
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#define INTEL_CRTC_FUNCS \
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.set_config = drm_atomic_helper_set_config, \
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.destroy = intel_crtc_destroy, \
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.page_flip = drm_atomic_helper_page_flip, \
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.atomic_duplicate_state = intel_crtc_duplicate_state, \
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.atomic_destroy_state = intel_crtc_destroy_state, \
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.set_crc_source = intel_crtc_set_crc_source, \
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.verify_crc_source = intel_crtc_verify_crc_source, \
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.get_crc_sources = intel_crtc_get_crc_sources, \
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.late_register = intel_crtc_late_register
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static const struct drm_crtc_funcs bdw_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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.get_vblank_counter = g4x_get_vblank_counter,
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.enable_vblank = bdw_enable_vblank,
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.disable_vblank = bdw_disable_vblank,
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.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
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};
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static const struct drm_crtc_funcs ilk_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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.get_vblank_counter = g4x_get_vblank_counter,
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.enable_vblank = ilk_enable_vblank,
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.disable_vblank = ilk_disable_vblank,
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.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
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};
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static const struct drm_crtc_funcs g4x_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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.get_vblank_counter = g4x_get_vblank_counter,
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.enable_vblank = i965_enable_vblank,
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.disable_vblank = i965_disable_vblank,
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.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
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};
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static const struct drm_crtc_funcs i965_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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.get_vblank_counter = i915_get_vblank_counter,
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.enable_vblank = i965_enable_vblank,
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.disable_vblank = i965_disable_vblank,
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.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
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};
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static const struct drm_crtc_funcs i915gm_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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.get_vblank_counter = i915_get_vblank_counter,
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.enable_vblank = i915gm_enable_vblank,
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.disable_vblank = i915gm_disable_vblank,
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.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
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};
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static const struct drm_crtc_funcs i915_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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.get_vblank_counter = i915_get_vblank_counter,
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.enable_vblank = i8xx_enable_vblank,
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.disable_vblank = i8xx_disable_vblank,
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.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
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};
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static const struct drm_crtc_funcs i8xx_crtc_funcs = {
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INTEL_CRTC_FUNCS,
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/* no hw vblank counter */
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.enable_vblank = i8xx_enable_vblank,
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.disable_vblank = i8xx_disable_vblank,
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.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
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};
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int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
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{
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struct intel_plane *primary, *cursor;
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const struct drm_crtc_funcs *funcs;
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struct intel_crtc *crtc;
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int sprite, ret;
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crtc = intel_crtc_alloc();
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if (IS_ERR(crtc))
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return PTR_ERR(crtc);
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crtc->pipe = pipe;
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crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
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primary = intel_primary_plane_create(dev_priv, pipe);
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if (IS_ERR(primary)) {
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ret = PTR_ERR(primary);
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goto fail;
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}
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crtc->plane_ids_mask |= BIT(primary->id);
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for_each_sprite(dev_priv, pipe, sprite) {
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struct intel_plane *plane;
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plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
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if (IS_ERR(plane)) {
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ret = PTR_ERR(plane);
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goto fail;
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}
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crtc->plane_ids_mask |= BIT(plane->id);
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}
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cursor = intel_cursor_plane_create(dev_priv, pipe);
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if (IS_ERR(cursor)) {
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ret = PTR_ERR(cursor);
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goto fail;
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}
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crtc->plane_ids_mask |= BIT(cursor->id);
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if (HAS_GMCH(dev_priv)) {
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if (IS_CHERRYVIEW(dev_priv) ||
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IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
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funcs = &g4x_crtc_funcs;
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else if (IS_GEN(dev_priv, 4))
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funcs = &i965_crtc_funcs;
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else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
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funcs = &i915gm_crtc_funcs;
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else if (IS_GEN(dev_priv, 3))
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funcs = &i915_crtc_funcs;
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else
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funcs = &i8xx_crtc_funcs;
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} else {
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if (INTEL_GEN(dev_priv) >= 8)
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funcs = &bdw_crtc_funcs;
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else
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funcs = &ilk_crtc_funcs;
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}
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ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
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&primary->base, &cursor->base,
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funcs, "pipe %c", pipe_name(pipe));
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if (ret)
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goto fail;
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BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
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dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
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dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
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if (INTEL_GEN(dev_priv) < 9) {
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enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
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BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
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dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
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dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
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}
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if (INTEL_GEN(dev_priv) >= 10)
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drm_crtc_create_scaling_filter_property(&crtc->base,
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BIT(DRM_SCALING_FILTER_DEFAULT) |
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BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
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intel_color_init(crtc);
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intel_crtc_crc_init(crtc);
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drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
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return 0;
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fail:
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intel_crtc_free(crtc);
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return ret;
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}
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22
drivers/gpu/drm/i915/display/intel_crtc.h
Normal file
22
drivers/gpu/drm/i915/display/intel_crtc.h
Normal file
@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#ifndef _INTEL_CRTC_H_
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#define _INTEL_CRTC_H_
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#include <linux/types.h>
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enum pipe;
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struct drm_i915_private;
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struct intel_crtc;
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struct intel_crtc_state;
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u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state);
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int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe);
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struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
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void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
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struct intel_crtc *crtc);
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#endif
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@ -68,8 +68,8 @@
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#include "intel_bw.h"
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#include "intel_cdclk.h"
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#include "intel_color.h"
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#include "intel_crtc.h"
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#include "intel_csr.h"
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#include "intel_cursor.h"
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#include "intel_display_types.h"
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#include "intel_dp_link_training.h"
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#include "intel_fbc.h"
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@ -114,7 +114,6 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
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static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
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static void intel_modeset_setup_hw_state(struct drm_device *dev,
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struct drm_modeset_acquire_ctx *ctx);
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static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
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struct intel_limit {
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struct {
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@ -1253,12 +1252,6 @@ static void assert_planes_disabled(struct intel_crtc *crtc)
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assert_plane_disabled(plane);
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}
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static void assert_vblank_disabled(struct drm_crtc *crtc)
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{
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if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
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drm_crtc_vblank_put(crtc);
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}
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void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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@ -1743,55 +1736,6 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
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return crtc->pipe;
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}
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static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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u32 mode_flags = crtc->mode_flags;
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/*
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* From Gen 11, In case of dsi cmd mode, frame counter wouldnt
|
||||
* have updated at the beginning of TE, if we want to use
|
||||
* the hw counter, then we would find it updated in only
|
||||
* the next TE, hence switching to sw counter.
|
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*/
|
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if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
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return 0;
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/*
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* On i965gm the hardware frame counter reads
|
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* zero when the TV encoder is enabled :(
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*/
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if (IS_I965GM(dev_priv) &&
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(crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
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return 0;
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if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
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return 0xffffffff; /* full 32 bit counter */
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else if (INTEL_GEN(dev_priv) >= 3)
|
||||
return 0xffffff; /* only 24 bits of frame count */
|
||||
else
|
||||
return 0; /* Gen2 doesn't have a hardware frame counter */
|
||||
}
|
||||
|
||||
void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
|
||||
assert_vblank_disabled(&crtc->base);
|
||||
drm_crtc_set_max_vblank_count(&crtc->base,
|
||||
intel_crtc_max_vblank_count(crtc_state));
|
||||
drm_crtc_vblank_on(&crtc->base);
|
||||
}
|
||||
|
||||
void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
|
||||
drm_crtc_vblank_off(&crtc->base);
|
||||
assert_vblank_disabled(&crtc->base);
|
||||
}
|
||||
|
||||
void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
|
||||
@ -11462,33 +11406,6 @@ static void ilk_pch_clock_get(struct intel_crtc *crtc,
|
||||
&pipe_config->fdi_m_n);
|
||||
}
|
||||
|
||||
static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
memset(crtc_state, 0, sizeof(*crtc_state));
|
||||
|
||||
__drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
|
||||
|
||||
crtc_state->cpu_transcoder = INVALID_TRANSCODER;
|
||||
crtc_state->master_transcoder = INVALID_TRANSCODER;
|
||||
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
|
||||
crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
|
||||
crtc_state->scaler_state.scaler_id = -1;
|
||||
crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
|
||||
}
|
||||
|
||||
static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
|
||||
{
|
||||
struct intel_crtc_state *crtc_state;
|
||||
|
||||
crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
|
||||
|
||||
if (crtc_state)
|
||||
intel_crtc_state_reset(crtc_state, crtc);
|
||||
|
||||
return crtc_state;
|
||||
}
|
||||
|
||||
/* Returns the currently programmed mode of the given encoder. */
|
||||
struct drm_display_mode *
|
||||
intel_encoder_current_mode(struct intel_encoder *encoder)
|
||||
@ -11529,14 +11446,6 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
|
||||
return mode;
|
||||
}
|
||||
|
||||
static void intel_crtc_destroy(struct drm_crtc *crtc)
|
||||
{
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
|
||||
drm_crtc_cleanup(crtc);
|
||||
kfree(intel_crtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_wm_need_update - Check whether watermarks need updating
|
||||
* @cur: current plane state
|
||||
@ -14740,17 +14649,6 @@ static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->base.dev;
|
||||
struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
|
||||
|
||||
if (!vblank->max_vblank_count)
|
||||
return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
|
||||
|
||||
return crtc->base.funcs->get_vblank_counter(&crtc->base);
|
||||
}
|
||||
|
||||
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
@ -15803,113 +15701,6 @@ void intel_plane_destroy(struct drm_plane *plane)
|
||||
kfree(to_intel_plane(plane));
|
||||
}
|
||||
|
||||
static int intel_crtc_late_register(struct drm_crtc *crtc)
|
||||
{
|
||||
intel_crtc_debugfs_add(crtc);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define INTEL_CRTC_FUNCS \
|
||||
.set_config = drm_atomic_helper_set_config, \
|
||||
.destroy = intel_crtc_destroy, \
|
||||
.page_flip = drm_atomic_helper_page_flip, \
|
||||
.atomic_duplicate_state = intel_crtc_duplicate_state, \
|
||||
.atomic_destroy_state = intel_crtc_destroy_state, \
|
||||
.set_crc_source = intel_crtc_set_crc_source, \
|
||||
.verify_crc_source = intel_crtc_verify_crc_source, \
|
||||
.get_crc_sources = intel_crtc_get_crc_sources, \
|
||||
.late_register = intel_crtc_late_register
|
||||
|
||||
static const struct drm_crtc_funcs bdw_crtc_funcs = {
|
||||
INTEL_CRTC_FUNCS,
|
||||
|
||||
.get_vblank_counter = g4x_get_vblank_counter,
|
||||
.enable_vblank = bdw_enable_vblank,
|
||||
.disable_vblank = bdw_disable_vblank,
|
||||
.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
|
||||
};
|
||||
|
||||
static const struct drm_crtc_funcs ilk_crtc_funcs = {
|
||||
INTEL_CRTC_FUNCS,
|
||||
|
||||
.get_vblank_counter = g4x_get_vblank_counter,
|
||||
.enable_vblank = ilk_enable_vblank,
|
||||
.disable_vblank = ilk_disable_vblank,
|
||||
.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
|
||||
};
|
||||
|
||||
static const struct drm_crtc_funcs g4x_crtc_funcs = {
|
||||
INTEL_CRTC_FUNCS,
|
||||
|
||||
.get_vblank_counter = g4x_get_vblank_counter,
|
||||
.enable_vblank = i965_enable_vblank,
|
||||
.disable_vblank = i965_disable_vblank,
|
||||
.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
|
||||
};
|
||||
|
||||
static const struct drm_crtc_funcs i965_crtc_funcs = {
|
||||
INTEL_CRTC_FUNCS,
|
||||
|
||||
.get_vblank_counter = i915_get_vblank_counter,
|
||||
.enable_vblank = i965_enable_vblank,
|
||||
.disable_vblank = i965_disable_vblank,
|
||||
.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
|
||||
};
|
||||
|
||||
static const struct drm_crtc_funcs i915gm_crtc_funcs = {
|
||||
INTEL_CRTC_FUNCS,
|
||||
|
||||
.get_vblank_counter = i915_get_vblank_counter,
|
||||
.enable_vblank = i915gm_enable_vblank,
|
||||
.disable_vblank = i915gm_disable_vblank,
|
||||
.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
|
||||
};
|
||||
|
||||
static const struct drm_crtc_funcs i915_crtc_funcs = {
|
||||
INTEL_CRTC_FUNCS,
|
||||
|
||||
.get_vblank_counter = i915_get_vblank_counter,
|
||||
.enable_vblank = i8xx_enable_vblank,
|
||||
.disable_vblank = i8xx_disable_vblank,
|
||||
.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
|
||||
};
|
||||
|
||||
static const struct drm_crtc_funcs i8xx_crtc_funcs = {
|
||||
INTEL_CRTC_FUNCS,
|
||||
|
||||
/* no hw vblank counter */
|
||||
.enable_vblank = i8xx_enable_vblank,
|
||||
.disable_vblank = i8xx_disable_vblank,
|
||||
.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
|
||||
};
|
||||
|
||||
static struct intel_crtc *intel_crtc_alloc(void)
|
||||
{
|
||||
struct intel_crtc_state *crtc_state;
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
|
||||
if (!crtc)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
crtc_state = intel_crtc_state_alloc(crtc);
|
||||
if (!crtc_state) {
|
||||
kfree(crtc);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
crtc->base.state = &crtc_state->uapi;
|
||||
crtc->config = crtc_state;
|
||||
|
||||
return crtc;
|
||||
}
|
||||
|
||||
static void intel_crtc_free(struct intel_crtc *crtc)
|
||||
{
|
||||
intel_crtc_destroy_state(&crtc->base, crtc->base.state);
|
||||
kfree(crtc);
|
||||
}
|
||||
|
||||
static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_plane *plane;
|
||||
@ -15922,100 +15713,6 @@ static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
|
||||
}
|
||||
}
|
||||
|
||||
static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
|
||||
{
|
||||
struct intel_plane *primary, *cursor;
|
||||
const struct drm_crtc_funcs *funcs;
|
||||
struct intel_crtc *crtc;
|
||||
int sprite, ret;
|
||||
|
||||
crtc = intel_crtc_alloc();
|
||||
if (IS_ERR(crtc))
|
||||
return PTR_ERR(crtc);
|
||||
|
||||
crtc->pipe = pipe;
|
||||
crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
|
||||
|
||||
primary = intel_primary_plane_create(dev_priv, pipe);
|
||||
if (IS_ERR(primary)) {
|
||||
ret = PTR_ERR(primary);
|
||||
goto fail;
|
||||
}
|
||||
crtc->plane_ids_mask |= BIT(primary->id);
|
||||
|
||||
for_each_sprite(dev_priv, pipe, sprite) {
|
||||
struct intel_plane *plane;
|
||||
|
||||
plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
|
||||
if (IS_ERR(plane)) {
|
||||
ret = PTR_ERR(plane);
|
||||
goto fail;
|
||||
}
|
||||
crtc->plane_ids_mask |= BIT(plane->id);
|
||||
}
|
||||
|
||||
cursor = intel_cursor_plane_create(dev_priv, pipe);
|
||||
if (IS_ERR(cursor)) {
|
||||
ret = PTR_ERR(cursor);
|
||||
goto fail;
|
||||
}
|
||||
crtc->plane_ids_mask |= BIT(cursor->id);
|
||||
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (IS_CHERRYVIEW(dev_priv) ||
|
||||
IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
|
||||
funcs = &g4x_crtc_funcs;
|
||||
else if (IS_GEN(dev_priv, 4))
|
||||
funcs = &i965_crtc_funcs;
|
||||
else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
|
||||
funcs = &i915gm_crtc_funcs;
|
||||
else if (IS_GEN(dev_priv, 3))
|
||||
funcs = &i915_crtc_funcs;
|
||||
else
|
||||
funcs = &i8xx_crtc_funcs;
|
||||
} else {
|
||||
if (INTEL_GEN(dev_priv) >= 8)
|
||||
funcs = &bdw_crtc_funcs;
|
||||
else
|
||||
funcs = &ilk_crtc_funcs;
|
||||
}
|
||||
|
||||
ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
|
||||
&primary->base, &cursor->base,
|
||||
funcs, "pipe %c", pipe_name(pipe));
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
|
||||
dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
|
||||
dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
|
||||
|
||||
if (INTEL_GEN(dev_priv) < 9) {
|
||||
enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
|
||||
|
||||
BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
|
||||
dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
|
||||
dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
|
||||
}
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 10)
|
||||
drm_crtc_create_scaling_filter_property(&crtc->base,
|
||||
BIT(DRM_SCALING_FILTER_DEFAULT) |
|
||||
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
|
||||
|
||||
intel_color_init(crtc);
|
||||
|
||||
intel_crtc_crc_init(crtc);
|
||||
|
||||
drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
intel_crtc_free(crtc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user