pinctrl: renesas: r8a779h0: Add SCIF_CLK pins, groups, functions

Add pins, groups and functions for the baud rate generation clock pins
(SCIF_CLK) on the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ee056d78d3a339bdbcca2cc5281f1fe01bbc3953.1706264667.git.geert+renesas@glider.be
This commit is contained in:
Cong Dang 2024-01-26 11:44:05 +01:00 committed by Geert Uytterhoeven
parent bc56b11cd7
commit fbaff0364a

View File

@ -1642,6 +1642,23 @@ static const unsigned int scif4_ctrl_mux[] = {
RTS4_N_MARK, CTS4_N_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(1, 17),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
static const unsigned int scif_clk2_pins[] = {
/* SCIF_CLK2 */
RCAR_GP_PIN(4, 11),
};
static const unsigned int scif_clk2_mux[] = {
SCIF_CLK2_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
@ -1706,6 +1723,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif4_data),
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk2),
};
static const char * const avb0_groups[] = {
@ -1796,6 +1815,14 @@ static const char * const scif4_groups[] = {
"scif4_ctrl",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
};
static const char * const scif_clk2_groups[] = {
"scif_clk2",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(avb1),
@ -1810,6 +1837,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(scif_clk2),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {