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pinctrl: renesas: r8a779h0: Add SCIF_CLK pins, groups, functions
Add pins, groups and functions for the baud rate generation clock pins (SCIF_CLK) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ee056d78d3a339bdbcca2cc5281f1fe01bbc3953.1706264667.git.geert+renesas@glider.be
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@ -1642,6 +1642,23 @@ static const unsigned int scif4_ctrl_mux[] = {
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RTS4_N_MARK, CTS4_N_MARK,
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};
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/* - SCIF Clock ------------------------------------------------------------- */
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static const unsigned int scif_clk_pins[] = {
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/* SCIF_CLK */
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RCAR_GP_PIN(1, 17),
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};
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static const unsigned int scif_clk_mux[] = {
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SCIF_CLK_MARK,
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};
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static const unsigned int scif_clk2_pins[] = {
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/* SCIF_CLK2 */
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RCAR_GP_PIN(4, 11),
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};
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static const unsigned int scif_clk2_mux[] = {
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SCIF_CLK2_MARK,
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};
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static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(avb0_link),
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SH_PFC_PIN_GROUP(avb0_magic),
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@ -1706,6 +1723,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scif4_data),
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SH_PFC_PIN_GROUP(scif4_clk),
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SH_PFC_PIN_GROUP(scif4_ctrl),
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SH_PFC_PIN_GROUP(scif_clk),
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SH_PFC_PIN_GROUP(scif_clk2),
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};
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static const char * const avb0_groups[] = {
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@ -1796,6 +1815,14 @@ static const char * const scif4_groups[] = {
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"scif4_ctrl",
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};
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static const char * const scif_clk_groups[] = {
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"scif_clk",
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};
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static const char * const scif_clk2_groups[] = {
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"scif_clk2",
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};
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(avb0),
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SH_PFC_FUNCTION(avb1),
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@ -1810,6 +1837,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(scif1),
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SH_PFC_FUNCTION(scif3),
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SH_PFC_FUNCTION(scif4),
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SH_PFC_FUNCTION(scif_clk),
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SH_PFC_FUNCTION(scif_clk2),
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};
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static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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