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cxl/pci: Fix CDAT retrieval on big endian
The CDAT exposed in sysfs differs between little endian and big endian
arches: On big endian, every 4 bytes are byte-swapped.
PCI Configuration Space is little endian (PCI r3.0 sec 6.1). Accessors
such as pci_read_config_dword() implicitly swap bytes on big endian.
That way, the macros in include/uapi/linux/pci_regs.h work regardless of
the arch's endianness. For an example of implicit byte-swapping, see
ppc4xx_pciex_read_config(), which calls in_le32(), which uses lwbrx
(Load Word Byte-Reverse Indexed).
DOE Read/Write Data Mailbox Registers are unlike other registers in
Configuration Space in that they contain or receive a 4 byte portion of
an opaque byte stream (a "Data Object" per PCIe r6.0 sec 7.9.24.5f).
They need to be copied to or from the request/response buffer verbatim.
So amend pci_doe_send_req() and pci_doe_recv_resp() to undo the implicit
byte-swapping.
The CXL_DOE_TABLE_ACCESS_* and PCI_DOE_DATA_OBJECT_DISC_* macros assume
implicit byte-swapping. Byte-swap requests after constructing them with
those macros and byte-swap responses before parsing them.
Change the request and response type to __le32 to avoid sparse warnings.
Per a request from Jonathan, replace sizeof(u32) with sizeof(__le32) for
consistency.
Fixes: c97006046c
("cxl/port: Read CDAT table")
Tested-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Cc: stable@vger.kernel.org # v6.0+
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/3051114102f41d19df3debbee123129118fc5e6d.1678543498.git.lukas@wunner.de
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
parent
e8d018dd02
commit
fbaa38214c
@ -462,7 +462,7 @@ static struct pci_doe_mb *find_cdat_doe(struct device *uport)
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return NULL;
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}
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#define CDAT_DOE_REQ(entry_handle) \
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#define CDAT_DOE_REQ(entry_handle) cpu_to_le32 \
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(FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \
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CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \
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FIELD_PREP(CXL_DOE_TABLE_ACCESS_TABLE_TYPE, \
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@ -475,8 +475,8 @@ static void cxl_doe_task_complete(struct pci_doe_task *task)
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}
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struct cdat_doe_task {
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u32 request_pl;
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u32 response_pl[32];
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__le32 request_pl;
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__le32 response_pl[32];
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struct completion c;
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struct pci_doe_task task;
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};
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@ -510,10 +510,10 @@ static int cxl_cdat_get_length(struct device *dev,
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return rc;
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}
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wait_for_completion(&t.c);
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if (t.task.rv < sizeof(u32))
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if (t.task.rv < sizeof(__le32))
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return -EIO;
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*length = t.response_pl[1];
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*length = le32_to_cpu(t.response_pl[1]);
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dev_dbg(dev, "CDAT length %zu\n", *length);
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return 0;
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@ -524,13 +524,13 @@ static int cxl_cdat_read_table(struct device *dev,
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struct cxl_cdat *cdat)
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{
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size_t length = cdat->length;
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u32 *data = cdat->table;
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__le32 *data = cdat->table;
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int entry_handle = 0;
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do {
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DECLARE_CDAT_DOE_TASK(CDAT_DOE_REQ(entry_handle), t);
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size_t entry_dw;
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u32 *entry;
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__le32 *entry;
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int rc;
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rc = pci_doe_submit_task(cdat_doe, &t.task);
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@ -540,21 +540,21 @@ static int cxl_cdat_read_table(struct device *dev,
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}
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wait_for_completion(&t.c);
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/* 1 DW header + 1 DW data min */
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if (t.task.rv < (2 * sizeof(u32)))
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if (t.task.rv < (2 * sizeof(__le32)))
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return -EIO;
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/* Get the CXL table access header entry handle */
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entry_handle = FIELD_GET(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE,
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t.response_pl[0]);
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le32_to_cpu(t.response_pl[0]));
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entry = t.response_pl + 1;
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entry_dw = t.task.rv / sizeof(u32);
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entry_dw = t.task.rv / sizeof(__le32);
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/* Skip Header */
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entry_dw -= 1;
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entry_dw = min(length / sizeof(u32), entry_dw);
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entry_dw = min(length / sizeof(__le32), entry_dw);
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/* Prevent length < 1 DW from causing a buffer overflow */
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if (entry_dw) {
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memcpy(data, entry, entry_dw * sizeof(u32));
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length -= entry_dw * sizeof(u32);
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memcpy(data, entry, entry_dw * sizeof(__le32));
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length -= entry_dw * sizeof(__le32);
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data += entry_dw;
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}
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} while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY);
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@ -128,7 +128,7 @@ static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
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return -EIO;
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/* Length is 2 DW of header + length of payload in DW */
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length = 2 + task->request_pl_sz / sizeof(u32);
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length = 2 + task->request_pl_sz / sizeof(__le32);
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if (length > PCI_DOE_MAX_LENGTH)
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return -EIO;
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if (length == PCI_DOE_MAX_LENGTH)
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@ -141,9 +141,9 @@ static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
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pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
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FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
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length));
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for (i = 0; i < task->request_pl_sz / sizeof(u32); i++)
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for (i = 0; i < task->request_pl_sz / sizeof(__le32); i++)
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pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
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task->request_pl[i]);
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le32_to_cpu(task->request_pl[i]));
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pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_GO);
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@ -195,11 +195,11 @@ static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *tas
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/* First 2 dwords have already been read */
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length -= 2;
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payload_length = min(length, task->response_pl_sz / sizeof(u32));
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payload_length = min(length, task->response_pl_sz / sizeof(__le32));
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/* Read the rest of the response payload */
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for (i = 0; i < payload_length; i++) {
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pci_read_config_dword(pdev, offset + PCI_DOE_READ,
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&task->response_pl[i]);
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pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
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task->response_pl[i] = cpu_to_le32(val);
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/* Prior to the last ack, ensure Data Object Ready */
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if (i == (payload_length - 1) && !pci_doe_data_obj_ready(doe_mb))
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return -EIO;
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@ -217,7 +217,7 @@ static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *tas
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if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
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return -EIO;
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return min(length, task->response_pl_sz / sizeof(u32)) * sizeof(u32);
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return min(length, task->response_pl_sz / sizeof(__le32)) * sizeof(__le32);
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}
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static void signal_task_complete(struct pci_doe_task *task, int rv)
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@ -317,14 +317,16 @@ static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid,
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{
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u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX,
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*index);
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__le32 request_pl_le = cpu_to_le32(request_pl);
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__le32 response_pl_le;
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u32 response_pl;
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DECLARE_COMPLETION_ONSTACK(c);
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struct pci_doe_task task = {
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.prot.vid = PCI_VENDOR_ID_PCI_SIG,
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.prot.type = PCI_DOE_PROTOCOL_DISCOVERY,
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.request_pl = &request_pl,
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.request_pl = &request_pl_le,
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.request_pl_sz = sizeof(request_pl),
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.response_pl = &response_pl,
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.response_pl = &response_pl_le,
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.response_pl_sz = sizeof(response_pl),
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.complete = pci_doe_task_complete,
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.private = &c,
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@ -340,6 +342,7 @@ static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid,
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if (task.rv != sizeof(response_pl))
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return -EIO;
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response_pl = le32_to_cpu(response_pl_le);
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*vid = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID, response_pl);
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*protocol = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL,
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response_pl);
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@ -533,8 +536,8 @@ int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
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* DOE requests must be a whole number of DW and the response needs to
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* be big enough for at least 1 DW
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*/
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if (task->request_pl_sz % sizeof(u32) ||
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task->response_pl_sz < sizeof(u32))
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if (task->request_pl_sz % sizeof(__le32) ||
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task->response_pl_sz < sizeof(__le32))
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return -EINVAL;
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if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags))
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@ -34,6 +34,10 @@ struct pci_doe_mb;
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* @work: Used internally by the mailbox
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* @doe_mb: Used internally by the mailbox
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*
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* Payloads are treated as opaque byte streams which are transmitted verbatim,
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* without byte-swapping. If payloads contain little-endian register values,
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* the caller is responsible for conversion with cpu_to_le32() / le32_to_cpu().
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*
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* The payload sizes and rv are specified in bytes with the following
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* restrictions concerning the protocol.
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*
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@ -45,9 +49,9 @@ struct pci_doe_mb;
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*/
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struct pci_doe_task {
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struct pci_doe_protocol prot;
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u32 *request_pl;
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__le32 *request_pl;
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size_t request_pl_sz;
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u32 *response_pl;
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__le32 *response_pl;
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size_t response_pl_sz;
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int rv;
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void (*complete)(struct pci_doe_task *task);
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