korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-29 22:14:41 +08:00
Code Issues Packages Projects Releases Wiki Activity

stmmac: intel: move definitions to dwmac-intel header file

Browse Source 
Currently some of the dwmac-intel definitions are in the header file,
while some are in the driver source file. Cleaning this by moving all
the definitions to the header file.

Signed-off-by: Wong Vee Khee <vee.khee.wong@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Wong Vee Khee 2021-06-11 21:16:08 +08:00 committed by David S. Miller
parent bf75213f24
commit fb9349c416
2 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
View File

@ -10,22 +10,6 @@
#include "stmmac.h"
#include "stmmac_ptp.h"
#define INTEL_MGBE_ADHOC_ADDR 0x15
#define INTEL_MGBE_XPCS_ADDR 0x16
/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
#define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3)
#define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
#define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3)
#define PSE_PTP_CLK_FREQ_256MHZ (0)
#define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0)
#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
#define PCH_PTP_CLK_FREQ_200MHZ (0)
/* Cross-timestamping defines */
#define ART_CPUID_LEAF 0x15
#define EHL_PSE_ART_MHZ 19200000
struct intel_priv_data {
int mdio_adhoc_addr; /* mdio address for serdes & etc */
unsigned long crossts_adj;

16
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
View File

@ -34,4 +34,20 @@
#define SERDES_RATE_PCIE_SHIFT 8
#define SERDES_PCLK_SHIFT 12
#define INTEL_MGBE_ADHOC_ADDR 0x15
#define INTEL_MGBE_XPCS_ADDR 0x16
/* Cross-timestamping defines */
#define ART_CPUID_LEAF 0x15
#define EHL_PSE_ART_MHZ 19200000
/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
#define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3)
#define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
#define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3)
#define PSE_PTP_CLK_FREQ_256MHZ (0)
#define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0)
#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
#define PCH_PTP_CLK_FREQ_200MHZ (0)
#endif /* __DWMAC_INTEL_H__ */