korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-18 17:54:13 +08:00
Code Issues Packages Projects Releases Wiki Activity

ARM: S3C64XX: Add support for synchronous clock operation

Browse Source 
Some boards based on S3C6410 use synchronous clocking, which means that HCLKx2
and other system clocks are generated from APLL instead of MPLL.

This patch adds support for such boards, by calculating hclk2 depending on
the status of S3C_OTHERS_SYNCMUXSEL bit in S3C64XX_OTHERS regist

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tomasz Figa 2011-08-19 11:54:31 +02:00 committed by Kukjin Kim
parent d9018df007
commit fb5d375d35
2 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/mach-s3c64xx/clock.c
View File

@ -744,7 +744,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
apll, mpll, epll); apll, mpll, epll);
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
/* Synchronous mode */
hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
else
/* Asynchronous mode */
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);

1
arch/arm/mach-s3c64xx/include/mach/regs-sys.h
View File

@ -26,5 +26,6 @@
#define S3C64XX_OTHERS S3C_SYSREG(0x900) #define S3C64XX_OTHERS S3C_SYSREG(0x900)
#define S3C64XX_OTHERS_USBMASK (1 << 16) #define S3C64XX_OTHERS_USBMASK (1 << 16)
#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6)
#endif /* _PLAT_REGS_SYS_H */ #endif /* _PLAT_REGS_SYS_H */