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arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC
Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220504094456.24386-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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arch/arm64/boot/dts/renesas/r9a09g011.dtsi
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arch/arm64/boot/dts/renesas/r9a09g011.dtsi
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/V2M SoC
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a09g011-cpg.h>
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/ {
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compatible = "renesas,r9a09g011";
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#address-cells = <2>;
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#size-cells = <2>;
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/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0>;
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device_type = "cpu";
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clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@82000000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x82010000 0 0x1000>,
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<0x0 0x82020000 0 0x20000>,
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<0x0 0x82040000 0 0x20000>,
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<0x0 0x82060000 0 0x20000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
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clock-names = "clk";
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};
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cpg: clock-controller@a3500000 {
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compatible = "renesas,r9a09g011-cpg";
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reg = <0 0xa3500000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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uart0: serial@a4040000 {
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compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
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reg = <0 0xa4040000 0 0x80>;
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interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
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<&cpg CPG_MOD R9A09G011_URT_PCLK>;
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clock-names = "sclk", "pclk";
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status = "disabled";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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