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Merge tag 'ras_for_3.21' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras into x86/ras
Pull RAS updates from Borislav Petkov:
"- Enable AMD thresholding IRQ by default if supported. (Aravind Gopalakrishnan)
- Unify mce_panic() message pattern. (Derek Che)
- A bit more involved simplification of the CMCI logic after yet another
report about race condition with the adaptive logic. (Borislav Petkov)
- ACPI APEI EINJ fleshing out of the user documentation. (Borislav Petkov)
- Minor cleanup. (Jan Beulich.)"
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
commit
fa45a45ca3
@ -1,129 +1,177 @@
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APEI Error INJection
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~~~~~~~~~~~~~~~~~~~~
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EINJ provides a hardware error injection mechanism
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It is very useful for debugging and testing of other APEI and RAS features.
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EINJ provides a hardware error injection mechanism. It is very useful
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for debugging and testing APEI and RAS features in general.
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To use EINJ, make sure the following are enabled in your kernel
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You need to check whether your BIOS supports EINJ first. For that, look
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for early boot messages similar to this one:
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ACPI: EINJ 0x000000007370A000 000150 (v01 INTEL 00000001 INTL 00000001)
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which shows that the BIOS is exposing an EINJ table - it is the
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mechanism through which the injection is done.
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Alternatively, look in /sys/firmware/acpi/tables for an "EINJ" file,
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which is a different representation of the same thing.
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It doesn't necessarily mean that EINJ is not supported if those above
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don't exist: before you give up, go into BIOS setup to see if the BIOS
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has an option to enable error injection. Look for something called WHEA
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or similar. Often, you need to enable an ACPI5 support option prior, in
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order to see the APEI,EINJ,... functionality supported and exposed by
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the BIOS menu.
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To use EINJ, make sure the following are options enabled in your kernel
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configuration:
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CONFIG_DEBUG_FS
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CONFIG_ACPI_APEI
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CONFIG_ACPI_APEI_EINJ
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The user interface of EINJ is debug file system, under the
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directory apei/einj. The following files are provided.
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The EINJ user interface is in <debugfs mount point>/apei/einj.
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The following files belong to it:
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- available_error_type
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Reading this file returns the error injection capability of the
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platform, that is, which error types are supported. The error type
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definition is as follow, the left field is the error type value, the
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right field is error description.
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0x00000001 Processor Correctable
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0x00000002 Processor Uncorrectable non-fatal
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0x00000004 Processor Uncorrectable fatal
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0x00000008 Memory Correctable
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0x00000010 Memory Uncorrectable non-fatal
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0x00000020 Memory Uncorrectable fatal
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0x00000040 PCI Express Correctable
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0x00000080 PCI Express Uncorrectable fatal
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0x00000100 PCI Express Uncorrectable non-fatal
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0x00000200 Platform Correctable
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0x00000400 Platform Uncorrectable non-fatal
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0x00000800 Platform Uncorrectable fatal
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This file shows which error types are supported:
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The format of file contents are as above, except there are only the
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available error type lines.
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Error Type Value Error Description
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================ =================
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0x00000001 Processor Correctable
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0x00000002 Processor Uncorrectable non-fatal
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0x00000004 Processor Uncorrectable fatal
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0x00000008 Memory Correctable
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0x00000010 Memory Uncorrectable non-fatal
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0x00000020 Memory Uncorrectable fatal
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0x00000040 PCI Express Correctable
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0x00000080 PCI Express Uncorrectable fatal
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0x00000100 PCI Express Uncorrectable non-fatal
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0x00000200 Platform Correctable
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0x00000400 Platform Uncorrectable non-fatal
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0x00000800 Platform Uncorrectable fatal
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The format of the file contents are as above, except present are only
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the available error types.
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- error_type
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This file is used to set the error type value. The error type value
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is defined in "available_error_type" description.
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Set the value of the error type being injected. Possible error types
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are defined in the file available_error_type above.
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- error_inject
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Write any integer to this file to trigger the error
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injection. Before this, please specify all necessary error
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parameters.
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Write any integer to this file to trigger the error injection. Make
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sure you have specified all necessary error parameters, i.e. this
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write should be the last step when injecting errors.
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- flags
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Present for kernel version 3.13 and above. Used to specify which
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of param{1..4} are valid and should be used by BIOS during injection.
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Value is a bitmask as specified in ACPI5.0 spec for the
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Present for kernel versions 3.13 and above. Used to specify which
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of param{1..4} are valid and should be used by the firmware during
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injection. Value is a bitmask as specified in ACPI5.0 spec for the
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SET_ERROR_TYPE_WITH_ADDRESS data structure:
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Bit 0 - Processor APIC field valid (see param3 below)
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Bit 1 - Memory address and mask valid (param1 and param2)
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Bit 2 - PCIe (seg,bus,dev,fn) valid (param4 below)
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If set to zero, legacy behaviour is used where the type of injection
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specifies just one bit set, and param1 is multiplexed.
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Bit 0 - Processor APIC field valid (see param3 below).
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Bit 1 - Memory address and mask valid (param1 and param2).
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Bit 2 - PCIe (seg,bus,dev,fn) valid (see param4 below).
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If set to zero, legacy behavior is mimicked where the type of
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injection specifies just one bit set, and param1 is multiplexed.
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- param1
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This file is used to set the first error parameter value. Effect of
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parameter depends on error_type specified. For example, if error
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type is memory related type, the param1 should be a valid physical
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memory address. [Unless "flag" is set - see above]
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This file is used to set the first error parameter value. Its effect
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depends on the error type specified in error_type. For example, if
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error type is memory related type, the param1 should be a valid
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physical memory address. [Unless "flag" is set - see above]
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- param2
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This file is used to set the second error parameter value. Effect of
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parameter depends on error_type specified. For example, if error
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type is memory related type, the param2 should be a physical memory
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address mask. Linux requires page or narrower granularity, say,
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0xfffffffffffff000.
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Same use as param1 above. For example, if error type is of memory
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related type, then param2 should be a physical memory address mask.
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Linux requires page or narrower granularity, say, 0xfffffffffffff000.
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- param3
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Used when the 0x1 bit is set in "flag" to specify the APIC id
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Used when the 0x1 bit is set in "flags" to specify the APIC id
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- param4
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Used when the 0x4 bit is set in "flag" to specify target PCIe device
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Used when the 0x4 bit is set in "flags" to specify target PCIe device
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- notrigger
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The EINJ mechanism is a two step process. First inject the error, then
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perform some actions to trigger it. Setting "notrigger" to 1 skips the
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trigger phase, which *may* allow the user to cause the error in some other
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context by a simple access to the cpu, memory location, or device that is
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the target of the error injection. Whether this actually works depends
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on what operations the BIOS actually includes in the trigger phase.
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BIOS versions based in the ACPI 4.0 specification have limited options
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to control where the errors are injected. Your BIOS may support an
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extension (enabled with the param_extension=1 module parameter, or
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boot command line einj.param_extension=1). This allows the address
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and mask for memory injections to be specified by the param1 and
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param2 files in apei/einj.
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The error injection mechanism is a two-step process. First inject the
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error, then perform some actions to trigger it. Setting "notrigger"
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to 1 skips the trigger phase, which *may* allow the user to cause the
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error in some other context by a simple access to the CPU, memory
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location, or device that is the target of the error injection. Whether
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this actually works depends on what operations the BIOS actually
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includes in the trigger phase.
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BIOS versions using the ACPI 5.0 specification have more control over
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the target of the injection. For processor related errors (type 0x1,
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0x2 and 0x4) the APICID of the target should be provided using the
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param1 file in apei/einj. For memory errors (type 0x8, 0x10 and 0x20)
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the address is set using param1 with a mask in param2 (0x0 is equivalent
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to all ones). For PCI express errors (type 0x40, 0x80 and 0x100) the
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segment, bus, device and function are specified using param1:
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BIOS versions based on the ACPI 4.0 specification have limited options
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in controlling where the errors are injected. Your BIOS may support an
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extension (enabled with the param_extension=1 module parameter, or boot
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command line einj.param_extension=1). This allows the address and mask
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for memory injections to be specified by the param1 and param2 files in
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apei/einj.
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BIOS versions based on the ACPI 5.0 specification have more control over
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the target of the injection. For processor-related errors (type 0x1, 0x2
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and 0x4), you can set flags to 0x3 (param3 for bit 0, and param1 and
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param2 for bit 1) so that you have more information added to the error
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signature being injected. The actual data passed is this:
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memory_address = param1;
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memory_address_range = param2;
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apicid = param3;
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pcie_sbdf = param4;
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For memory errors (type 0x8, 0x10 and 0x20) the address is set using
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param1 with a mask in param2 (0x0 is equivalent to all ones). For PCI
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express errors (type 0x40, 0x80 and 0x100) the segment, bus, device and
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function are specified using param1:
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31 24 23 16 15 11 10 8 7 0
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+-------------------------------------------------+
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| segment | bus | device | function | reserved |
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+-------------------------------------------------+
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An ACPI 5.0 BIOS may also allow vendor specific errors to be injected.
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Anyway, you get the idea, if there's doubt just take a look at the code
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in drivers/acpi/apei/einj.c.
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An ACPI 5.0 BIOS may also allow vendor-specific errors to be injected.
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In this case a file named vendor will contain identifying information
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from the BIOS that hopefully will allow an application wishing to use
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the vendor specific extension to tell that they are running on a BIOS
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the vendor-specific extension to tell that they are running on a BIOS
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that supports it. All vendor extensions have the 0x80000000 bit set in
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error_type. A file vendor_flags controls the interpretation of param1
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and param2 (1 = PROCESSOR, 2 = MEMORY, 4 = PCI). See your BIOS vendor
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documentation for details (and expect changes to this API if vendors
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creativity in using this feature expands beyond our expectations).
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Example:
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An error injection example:
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# cd /sys/kernel/debug/apei/einj
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# cat available_error_type # See which errors can be injected
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0x00000002 Processor Uncorrectable non-fatal
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0x00000008 Memory Correctable
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0x00000010 Memory Uncorrectable non-fatal
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# echo 0x12345000 > param1 # Set memory address for injection
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# echo 0xfffffffffffff000 > param2 # Mask - anywhere in this page
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# echo $((-1 << 12)) > param2 # Mask 0xfffffffffffff000 - anywhere in this page
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# echo 0x8 > error_type # Choose correctable memory error
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# echo 1 > error_inject # Inject now
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You should see something like this in dmesg:
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[22715.830801] EDAC sbridge MC3: HANDLING MCE MEMORY ERROR
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[22715.834759] EDAC sbridge MC3: CPU 0: Machine Check Event: 0 Bank 7: 8c00004000010090
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[22715.834759] EDAC sbridge MC3: TSC 0
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[22715.834759] EDAC sbridge MC3: ADDR 12345000 EDAC sbridge MC3: MISC 144780c86
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[22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0
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[22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0)
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For more information about EINJ, please refer to ACPI specification
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version 4.0, section 17.5 and ACPI 5.0, section 18.6.
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@ -183,11 +183,11 @@ typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
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enum mcp_flags {
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MCP_TIMESTAMP = (1 << 0), /* log time stamp */
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MCP_UC = (1 << 1), /* log uncorrected errors */
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MCP_DONTLOG = (1 << 2), /* only clear, don't log */
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MCP_TIMESTAMP = BIT(0), /* log time stamp */
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MCP_UC = BIT(1), /* log uncorrected errors */
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MCP_DONTLOG = BIT(2), /* only clear, don't log */
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};
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void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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int mce_notify_irq(void);
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@ -14,6 +14,7 @@ enum severity_level {
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};
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#define ATTR_LEN 16
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#define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */
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/* One object for each MCE bank, shared by all CPUs */
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struct mce_bank {
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@ -30,13 +31,13 @@ extern struct mce_bank *mce_banks;
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extern mce_banks_t mce_banks_ce_disabled;
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#ifdef CONFIG_X86_MCE_INTEL
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unsigned long mce_intel_adjust_timer(unsigned long interval);
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void mce_intel_cmci_poll(void);
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unsigned long cmci_intel_adjust_timer(unsigned long interval);
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bool mce_intel_cmci_poll(void);
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void mce_intel_hcpu_update(unsigned long cpu);
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void cmci_disable_bank(int bank);
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#else
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# define mce_intel_adjust_timer mce_adjust_timer_default
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static inline void mce_intel_cmci_poll(void) { }
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# define cmci_intel_adjust_timer mce_adjust_timer_default
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static inline bool mce_intel_cmci_poll(void) { return false; }
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static inline void mce_intel_hcpu_update(unsigned long cpu) { }
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static inline void cmci_disable_bank(int bank) { }
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#endif
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@ -59,7 +59,7 @@ static DEFINE_MUTEX(mce_chrdev_read_mutex);
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#define CREATE_TRACE_POINTS
|
||||
#include <trace/events/mce.h>
|
||||
|
||||
#define SPINUNIT 100 /* 100ns */
|
||||
#define SPINUNIT 100 /* 100ns */
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||||
|
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DEFINE_PER_CPU(unsigned, mce_exception_count);
|
||||
|
||||
@ -88,9 +88,6 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
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static DEFINE_PER_CPU(struct mce, mces_seen);
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static int cpu_missing;
|
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|
||||
/* CMCI storm detection filter */
|
||||
static DEFINE_PER_CPU(unsigned long, mce_polled_error);
|
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|
||||
/*
|
||||
* MCA banks polled by the period polling timer for corrected events.
|
||||
* With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
|
||||
@ -624,8 +621,9 @@ DEFINE_PER_CPU(unsigned, mce_poll_count);
|
||||
* is already totally * confused. In this case it's likely it will
|
||||
* not fully execute the machine check handler either.
|
||||
*/
|
||||
void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
|
||||
bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
|
||||
{
|
||||
bool error_logged = false;
|
||||
struct mce m;
|
||||
int severity;
|
||||
int i;
|
||||
@ -648,7 +646,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
|
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if (!(m.status & MCI_STATUS_VAL))
|
||||
continue;
|
||||
|
||||
this_cpu_write(mce_polled_error, 1);
|
||||
|
||||
/*
|
||||
* Uncorrected or signalled events are handled by the exception
|
||||
* handler when it is enabled, so don't process those here.
|
||||
@ -681,8 +679,10 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
|
||||
* Don't get the IP here because it's unlikely to
|
||||
* have anything to do with the actual error location.
|
||||
*/
|
||||
if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
|
||||
if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) {
|
||||
error_logged = true;
|
||||
mce_log(&m);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear state for this bank.
|
||||
@ -696,6 +696,8 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
|
||||
*/
|
||||
|
||||
sync_core();
|
||||
|
||||
return error_logged;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(machine_check_poll);
|
||||
|
||||
@ -815,7 +817,7 @@ static void mce_reign(void)
|
||||
* other CPUs.
|
||||
*/
|
||||
if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
|
||||
mce_panic("Fatal Machine check", m, msg);
|
||||
mce_panic("Fatal machine check", m, msg);
|
||||
|
||||
/*
|
||||
* For UC somewhere we let the CPU who detects it handle it.
|
||||
@ -828,7 +830,7 @@ static void mce_reign(void)
|
||||
* source or one CPU is hung. Panic.
|
||||
*/
|
||||
if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
|
||||
mce_panic("Machine check from unknown source", NULL, NULL);
|
||||
mce_panic("Fatal machine check from unknown source", NULL, NULL);
|
||||
|
||||
/*
|
||||
* Now clear all the mces_seen so that they don't reappear on
|
||||
@ -1260,7 +1262,7 @@ void mce_log_therm_throt_event(__u64 status)
|
||||
* poller finds an MCE, poll 2x faster. When the poller finds no more
|
||||
* errors, poll 2x slower (up to check_interval seconds).
|
||||
*/
|
||||
static unsigned long check_interval = 5 * 60; /* 5 minutes */
|
||||
static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
|
||||
|
||||
static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
|
||||
static DEFINE_PER_CPU(struct timer_list, mce_timer);
|
||||
@ -1270,59 +1272,14 @@ static unsigned long mce_adjust_timer_default(unsigned long interval)
|
||||
return interval;
|
||||
}
|
||||
|
||||
static unsigned long (*mce_adjust_timer)(unsigned long interval) =
|
||||
mce_adjust_timer_default;
|
||||
static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
|
||||
|
||||
static int cmc_error_seen(void)
|
||||
static void __restart_timer(struct timer_list *t, unsigned long interval)
|
||||
{
|
||||
unsigned long *v = this_cpu_ptr(&mce_polled_error);
|
||||
|
||||
return test_and_clear_bit(0, v);
|
||||
}
|
||||
|
||||
static void mce_timer_fn(unsigned long data)
|
||||
{
|
||||
struct timer_list *t = this_cpu_ptr(&mce_timer);
|
||||
unsigned long iv;
|
||||
int notify;
|
||||
|
||||
WARN_ON(smp_processor_id() != data);
|
||||
|
||||
if (mce_available(this_cpu_ptr(&cpu_info))) {
|
||||
machine_check_poll(MCP_TIMESTAMP,
|
||||
this_cpu_ptr(&mce_poll_banks));
|
||||
mce_intel_cmci_poll();
|
||||
}
|
||||
|
||||
/*
|
||||
* Alert userspace if needed. If we logged an MCE, reduce the
|
||||
* polling interval, otherwise increase the polling interval.
|
||||
*/
|
||||
iv = __this_cpu_read(mce_next_interval);
|
||||
notify = mce_notify_irq();
|
||||
notify |= cmc_error_seen();
|
||||
if (notify) {
|
||||
iv = max(iv / 2, (unsigned long) HZ/100);
|
||||
} else {
|
||||
iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
|
||||
iv = mce_adjust_timer(iv);
|
||||
}
|
||||
__this_cpu_write(mce_next_interval, iv);
|
||||
/* Might have become 0 after CMCI storm subsided */
|
||||
if (iv) {
|
||||
t->expires = jiffies + iv;
|
||||
add_timer_on(t, smp_processor_id());
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that the timer is firing in @interval from now.
|
||||
*/
|
||||
void mce_timer_kick(unsigned long interval)
|
||||
{
|
||||
struct timer_list *t = this_cpu_ptr(&mce_timer);
|
||||
unsigned long when = jiffies + interval;
|
||||
unsigned long iv = __this_cpu_read(mce_next_interval);
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
if (timer_pending(t)) {
|
||||
if (time_before(when, t->expires))
|
||||
@ -1331,6 +1288,53 @@ void mce_timer_kick(unsigned long interval)
|
||||
t->expires = round_jiffies(when);
|
||||
add_timer_on(t, smp_processor_id());
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void mce_timer_fn(unsigned long data)
|
||||
{
|
||||
struct timer_list *t = this_cpu_ptr(&mce_timer);
|
||||
int cpu = smp_processor_id();
|
||||
unsigned long iv;
|
||||
|
||||
WARN_ON(cpu != data);
|
||||
|
||||
iv = __this_cpu_read(mce_next_interval);
|
||||
|
||||
if (mce_available(this_cpu_ptr(&cpu_info))) {
|
||||
machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks));
|
||||
|
||||
if (mce_intel_cmci_poll()) {
|
||||
iv = mce_adjust_timer(iv);
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Alert userspace if needed. If we logged an MCE, reduce the polling
|
||||
* interval, otherwise increase the polling interval.
|
||||
*/
|
||||
if (mce_notify_irq())
|
||||
iv = max(iv / 2, (unsigned long) HZ/100);
|
||||
else
|
||||
iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
|
||||
|
||||
done:
|
||||
__this_cpu_write(mce_next_interval, iv);
|
||||
__restart_timer(t, iv);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that the timer is firing in @interval from now.
|
||||
*/
|
||||
void mce_timer_kick(unsigned long interval)
|
||||
{
|
||||
struct timer_list *t = this_cpu_ptr(&mce_timer);
|
||||
unsigned long iv = __this_cpu_read(mce_next_interval);
|
||||
|
||||
__restart_timer(t, interval);
|
||||
|
||||
if (interval < iv)
|
||||
__this_cpu_write(mce_next_interval, interval);
|
||||
}
|
||||
@ -1631,7 +1635,7 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
|
||||
switch (c->x86_vendor) {
|
||||
case X86_VENDOR_INTEL:
|
||||
mce_intel_feature_init(c);
|
||||
mce_adjust_timer = mce_intel_adjust_timer;
|
||||
mce_adjust_timer = cmci_intel_adjust_timer;
|
||||
break;
|
||||
case X86_VENDOR_AMD:
|
||||
mce_amd_feature_init(c);
|
||||
|
||||
@ -79,7 +79,7 @@ static inline bool is_shared_bank(int bank)
|
||||
return (bank == 4);
|
||||
}
|
||||
|
||||
static const char * const bank4_names(struct threshold_block *b)
|
||||
static const char *bank4_names(const struct threshold_block *b)
|
||||
{
|
||||
switch (b->address) {
|
||||
/* MSR4_MISC0 */
|
||||
@ -250,6 +250,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
|
||||
if (!b.interrupt_capable)
|
||||
goto init;
|
||||
|
||||
b.interrupt_enable = 1;
|
||||
new = (high & MASK_LVTOFF_HI) >> 20;
|
||||
offset = setup_APIC_mce(offset, new);
|
||||
|
||||
@ -322,6 +323,8 @@ static void amd_threshold_interrupt(void)
|
||||
log:
|
||||
mce_setup(&m);
|
||||
rdmsrl(MSR_IA32_MCx_STATUS(bank), m.status);
|
||||
if (!(m.status & MCI_STATUS_VAL))
|
||||
return;
|
||||
m.misc = ((u64)high << 32) | low;
|
||||
m.bank = bank;
|
||||
mce_log(&m);
|
||||
@ -497,10 +500,12 @@ static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
|
||||
b->interrupt_capable = lvt_interrupt_supported(bank, high);
|
||||
b->threshold_limit = THRESHOLD_MAX;
|
||||
|
||||
if (b->interrupt_capable)
|
||||
if (b->interrupt_capable) {
|
||||
threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
|
||||
else
|
||||
b->interrupt_enable = 1;
|
||||
} else {
|
||||
threshold_ktype.default_attrs[2] = NULL;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&b->miscj);
|
||||
|
||||
|
||||
@ -38,6 +38,15 @@
|
||||
*/
|
||||
static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
|
||||
|
||||
/*
|
||||
* CMCI storm detection backoff counter
|
||||
*
|
||||
* During storm, we reset this counter to INITIAL_CHECK_INTERVAL in case we've
|
||||
* encountered an error. If not, we decrement it by one. We signal the end of
|
||||
* the CMCI storm when it reaches 0.
|
||||
*/
|
||||
static DEFINE_PER_CPU(int, cmci_backoff_cnt);
|
||||
|
||||
/*
|
||||
* cmci_discover_lock protects against parallel discovery attempts
|
||||
* which could race against each other.
|
||||
@ -46,7 +55,7 @@ static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
|
||||
|
||||
#define CMCI_THRESHOLD 1
|
||||
#define CMCI_POLL_INTERVAL (30 * HZ)
|
||||
#define CMCI_STORM_INTERVAL (1 * HZ)
|
||||
#define CMCI_STORM_INTERVAL (HZ)
|
||||
#define CMCI_STORM_THRESHOLD 15
|
||||
|
||||
static DEFINE_PER_CPU(unsigned long, cmci_time_stamp);
|
||||
@ -82,11 +91,21 @@ static int cmci_supported(int *banks)
|
||||
return !!(cap & MCG_CMCI_P);
|
||||
}
|
||||
|
||||
void mce_intel_cmci_poll(void)
|
||||
bool mce_intel_cmci_poll(void)
|
||||
{
|
||||
if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE)
|
||||
return;
|
||||
machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Reset the counter if we've logged an error in the last poll
|
||||
* during the storm.
|
||||
*/
|
||||
if (machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned)))
|
||||
this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
|
||||
else
|
||||
this_cpu_dec(cmci_backoff_cnt);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void mce_intel_hcpu_update(unsigned long cpu)
|
||||
@ -97,31 +116,32 @@ void mce_intel_hcpu_update(unsigned long cpu)
|
||||
per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE;
|
||||
}
|
||||
|
||||
unsigned long mce_intel_adjust_timer(unsigned long interval)
|
||||
unsigned long cmci_intel_adjust_timer(unsigned long interval)
|
||||
{
|
||||
int r;
|
||||
|
||||
if (interval < CMCI_POLL_INTERVAL)
|
||||
return interval;
|
||||
if ((this_cpu_read(cmci_backoff_cnt) > 0) &&
|
||||
(__this_cpu_read(cmci_storm_state) == CMCI_STORM_ACTIVE)) {
|
||||
mce_notify_irq();
|
||||
return CMCI_STORM_INTERVAL;
|
||||
}
|
||||
|
||||
switch (__this_cpu_read(cmci_storm_state)) {
|
||||
case CMCI_STORM_ACTIVE:
|
||||
|
||||
/*
|
||||
* We switch back to interrupt mode once the poll timer has
|
||||
* silenced itself. That means no events recorded and the
|
||||
* timer interval is back to our poll interval.
|
||||
* silenced itself. That means no events recorded and the timer
|
||||
* interval is back to our poll interval.
|
||||
*/
|
||||
__this_cpu_write(cmci_storm_state, CMCI_STORM_SUBSIDED);
|
||||
r = atomic_sub_return(1, &cmci_storm_on_cpus);
|
||||
if (r == 0)
|
||||
if (!atomic_sub_return(1, &cmci_storm_on_cpus))
|
||||
pr_notice("CMCI storm subsided: switching to interrupt mode\n");
|
||||
|
||||
/* FALLTHROUGH */
|
||||
|
||||
case CMCI_STORM_SUBSIDED:
|
||||
/*
|
||||
* We wait for all cpus to go back to SUBSIDED
|
||||
* state. When that happens we switch back to
|
||||
* interrupt mode.
|
||||
* We wait for all CPUs to go back to SUBSIDED state. When that
|
||||
* happens we switch back to interrupt mode.
|
||||
*/
|
||||
if (!atomic_read(&cmci_storm_on_cpus)) {
|
||||
__this_cpu_write(cmci_storm_state, CMCI_STORM_NONE);
|
||||
@ -130,10 +150,8 @@ unsigned long mce_intel_adjust_timer(unsigned long interval)
|
||||
}
|
||||
return CMCI_POLL_INTERVAL;
|
||||
default:
|
||||
/*
|
||||
* We have shiny weather. Let the poll do whatever it
|
||||
* thinks.
|
||||
*/
|
||||
|
||||
/* We have shiny weather. Let the poll do whatever it thinks. */
|
||||
return interval;
|
||||
}
|
||||
}
|
||||
@ -178,7 +196,8 @@ static bool cmci_storm_detect(void)
|
||||
cmci_storm_disable_banks();
|
||||
__this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
|
||||
r = atomic_add_return(1, &cmci_storm_on_cpus);
|
||||
mce_timer_kick(CMCI_POLL_INTERVAL);
|
||||
mce_timer_kick(CMCI_STORM_INTERVAL);
|
||||
this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
|
||||
|
||||
if (r == 1)
|
||||
pr_notice("CMCI storm detected: switching to poll mode\n");
|
||||
@ -195,6 +214,7 @@ static void intel_threshold_interrupt(void)
|
||||
{
|
||||
if (cmci_storm_detect())
|
||||
return;
|
||||
|
||||
machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
|
||||
mce_notify_irq();
|
||||
}
|
||||
@ -286,6 +306,7 @@ void cmci_recheck(void)
|
||||
|
||||
if (!mce_available(raw_cpu_ptr(&cpu_info)) || !cmci_supported(&banks))
|
||||
return;
|
||||
|
||||
local_irq_save(flags);
|
||||
machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
|
||||
local_irq_restore(flags);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user