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drm/i915: Clean up vlv_program_watermarks()
Add small helpers to make the intent of the staggered enable/disable sequence in vlv_program_watermarks() easier on the eyes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480354637-14209-15-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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@ -1327,55 +1327,63 @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
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}
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}
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static bool is_disabling(int old, int new, int threshold)
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{
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return old >= threshold && new < threshold;
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}
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static bool is_enabling(int old, int new, int threshold)
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{
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return old < threshold && new >= threshold;
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}
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static void vlv_update_wm(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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struct vlv_wm_values wm = {};
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struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
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struct vlv_wm_values new_wm = {};
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vlv_compute_wm(crtc);
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vlv_merge_wm(dev_priv, &wm);
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vlv_merge_wm(dev_priv, &new_wm);
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if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
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if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
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/* FIXME should be part of crtc atomic commit */
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vlv_pipe_set_fifo_size(crtc);
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return;
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}
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if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
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dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
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if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
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chv_set_memory_dvfs(dev_priv, false);
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if (wm.level < VLV_WM_LEVEL_PM5 &&
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dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
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if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
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chv_set_memory_pm5(dev_priv, false);
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if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
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if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
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_intel_set_memory_cxsr(dev_priv, false);
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/* FIXME should be part of crtc atomic commit */
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vlv_pipe_set_fifo_size(crtc);
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vlv_write_wm_values(dev_priv, &wm);
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vlv_write_wm_values(dev_priv, &new_wm);
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DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
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"sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
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pipe_name(pipe), wm.pipe[pipe].plane[PLANE_PRIMARY], wm.pipe[pipe].plane[PLANE_CURSOR],
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wm.pipe[pipe].plane[PLANE_SPRITE0], wm.pipe[pipe].plane[PLANE_SPRITE1],
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wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
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pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
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new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
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new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
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if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
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if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
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_intel_set_memory_cxsr(dev_priv, true);
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if (wm.level >= VLV_WM_LEVEL_PM5 &&
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dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
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if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
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chv_set_memory_pm5(dev_priv, true);
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if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
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dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
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if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
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chv_set_memory_dvfs(dev_priv, true);
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dev_priv->wm.vlv = wm;
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*old_wm = new_wm;
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}
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#define single_plane_enabled(mask) is_power_of_2(mask)
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